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1. 发明申请

US20070198815A1 Programmable digital signal processor having a clustered SIMD microarchitecture including a complex short multiplier and an independent vector load unit 审中-公开
标题翻译：具有集成SIMD微架构的可编程数字信号处理器，其包括复数短乘法器和独立向量负载单元
公开(公告)号：US20070198815A1
公开(公告)日：2007-08-23
申请号：US11201841
申请日：2005-08-11
申请人： Dake Liu , Anders Nilsson , Eric Tell
发明人： Dake Liu , Anders Nilsson , Eric Tell
IPC分类号： G06F9/44
CPC分类号： G06F9/3885 , G06F7/4812 , G06F7/5443 , G06F7/57 , G06F9/3001 , G06F9/325 , G06F9/342 , G06F9/3822 , G06F9/3853 , G06F9/3891 , G06F15/8092
摘要： A programmable digital signal processor with a clustered SIMD microarchitecture includes a plurality of accelerator units, a processor core, and a complex computing unit. Each of the accelerator units may perform one or more dedicated functions. The processor core includes an integer execution unit that may execute integer instructions. The complex computing unit may include a complex arithmetic logic unit execution pipeline that may include one or more datapaths configured to execute complex vector instructions, and a vector load unit. In addition, each datapath may include a complex short multiplier accumulator unit that may be configured to multiply a complex data value by values in the set of numbers including {0, +/−1}+{0, +/−i}. The vector load unit may cause the complex vector instructions to be fetched each clock cycle for use by any datapath in the complex arithmetic logic unit execution pipeline.
摘要翻译：具有集群SIMD微体系结构的可编程数字信号处理器包括多个加速器单元，处理器核心和复合计算单元。每个加速器单元可以执行一个或多个专用功能。处理器核心包括可执行整数指令的整数执行单元。复合计算单元可以包括复杂算术逻辑单元执行流水线，其可以包括被配置为执行复向量指令的一个或多个数据路径和向量加载单元。另外，每个数据路径可以包括复数的短乘法器累加器单元，其可以被配置为将复数数据值乘以包括{0，+/- 1} + {0，+/- i}的数字集合中的值。矢量加载单元可能会导致每个时钟周期提取复矢量指令，以供复杂算术逻辑单元执行流水线中的任何数据路径使用。

2. 发明授权

US07299342B2 Complex vector executing clustered SIMD micro-architecture DSP with accelerator coupled complex ALU paths each further including short multiplier/accumulator using two's complement 有权
标题翻译：复合向量执行集成SIMD微架构DSP，加速器耦合复杂ALU路径，每个进一步包括使用二进制补码的短乘数/累加器
公开(公告)号：US07299342B2
公开(公告)日：2007-11-20
申请号：US11201842
申请日：2005-08-11
申请人： Anders Henrik Nilsson , Eric Johan Tell , Dake Liu
发明人： Anders Henrik Nilsson , Eric Johan Tell , Dake Liu
IPC分类号： G06F9/302
CPC分类号： G06F9/30079 , G06F9/30014 , G06F9/30036 , G06F9/3851 , G06F9/3885 , G06F9/3891 , G06F15/7842 , G06F15/8092
摘要： A programmable digital signal processor including a clustered SIMD microarchitecture includes a plurality of accelerator units, a processor core and a complex computing unit. Each of the accelerator units may be configured to perform one or more dedicated functions. The processor core includes an integer execution unit that may be configured to execute integer instructions. The complex computing unit may be configured to execute complex vector instructions. The complex computing unit may include a first and a second clustered execution pipeline. The first clustered execution pipeline may include one or more complex arithmetic logic unit datapaths configured to execute first complex vector instructions. The second clustered execution pipeline may include one or more complex multiplier accumulator datapaths configured to execute second complex vector instructions.
摘要翻译：包括集群SIMD微体系结构的可编程数字信号处理器包括多个加速器单元，处理器核和复合计算单元。每个加速器单元可以被配置为执行一个或多个专用功能。处理器核心包括可被配置为执行整数指令的整数执行单元。复合计算单元可以被配置为执行复向量指令。复合计算单元可以包括第一和第二群集执行流水线。第一群集执行流水线可以包括被配置为执行第一复合向量指令的一个或多个复杂算术逻辑单元数据路径。第二群集执行流水线可以包括被配置为执行第二复合向量指令的一个或多个复数乘法器累加器数据路径。

3. 发明申请

US20160006283A1 PORTABLE CHARGING DEVICE 审中-公开
标题翻译：便携式充电装置
公开(公告)号：US20160006283A1
公开(公告)日：2016-01-07
申请号：US14323602
申请日：2014-07-03
申请人： Dake Liu
发明人： Dake Liu
IPC分类号： H02J7/00
CPC分类号： H02J7/0052 , H02J7/0014 , H02J7/0026 , H02J2007/0096 , Y02B40/90
摘要： The present utility model discloses a portable charging device that includes a charging module, a battery protection module, a built-in battery pack with multiple battery cells, a voltage regulating output module, a microcontroller module, and an LCD display. Said charging device powers its externally connected electronic devices and in turn charges the batteries of those devices. Said charging module uses an input interface that matches the output interface of a personal computer's AC/DC power adapter. Said charging module charges said built-in battery pack through said battery protection module. Said built-in battery pack are connected to said voltage regulating output module to power externally connected electronic devices. Said microcontroller module connects to said battery protection module and said voltage regulating output module to control the charging and discharging process of said portable charging device. Said portable charging device provides convenience to its user by reusing the user's existing computer AC/DC power adapter as the energy input. It packs multiple battery cells and connects them electronically in series to maximize the energy intake from the computer AC/DC power adapter, improve charging efficiency, and significantly shorten the charging time of said charging device.
摘要翻译：本实用新型公开了一种便携式充电装置，其包括充电模块，电池保护模块，具有多个电池单元的内置电池组，电压调节输出模块，微控制器模块和LCD显示器。所述充电装置为其外部连接的电子设备供电，从而对这些设备的电池充电。所述充电模块使用与个人计算机的AC / DC电源适配器的输出接口相匹配的输入接口。所述充电模块通过所述电池保护模块对所述内置电池组充电。所述内置电池组连接到所述调压输出模块以为外部连接的电子设备供电。所述微控制器模块连接到所述电池保护模块和所述电压调节输出模块以控制所述便携式充电装置的充电和放电过程。所述便携式充电装置通过重新使用用户现有的计算机AC / DC电力适配器作为能量输入来为其用户提供便利。它包装多个电池单元并串联电子地最大化从计算机AC / DC电源适配器的能量摄入，提高充电效率，并显着缩短充电设备的充电时间。

4. 发明申请

US20060271764A1 Programmable digital signal processor including a clustered SIMD microarchitecture configured to execute complex vector instructions 有权
标题翻译：可编程数字信号处理器包括配置成执行复矢量指令的集群SIMD微体系结构
公开(公告)号：US20060271764A1
公开(公告)日：2006-11-30
申请号：US11201842
申请日：2005-08-11
申请人： Anders Nilsson , Eric Tell , Dake Liu
发明人： Anders Nilsson , Eric Tell , Dake Liu
IPC分类号： G06F15/00
CPC分类号： G06F9/30079 , G06F9/30014 , G06F9/30036 , G06F9/3851 , G06F9/3885 , G06F9/3891 , G06F15/7842 , G06F15/8092
摘要： A programmable digital signal processor including a clustered SIMD microarchitecture includes a plurality of accelerator units, a processor core and a complex computing unit. Each of the accelerator units may be configured to perform one or more dedicated functions. The processor core includes an integer execution unit that may be configured to execute integer instructions. The complex computing unit may be configured to execute complex vector instructions. The complex computing unit may include a first and a second clustered execution pipeline. The first clustered execution pipeline may include one or more complex arithmetic logic unit datapaths configured to execute first complex vector instructions. The second clustered execution pipeline may include one or more complex multiplier accumulator datapaths configured to execute second complex vector instructions.
摘要翻译：包括集群SIMD微体系结构的可编程数字信号处理器包括多个加速器单元，处理器核和复合计算单元。每个加速器单元可以被配置为执行一个或多个专用功能。处理器核心包括可被配置为执行整数指令的整数执行单元。复合计算单元可以被配置为执行复向量指令。复合计算单元可以包括第一和第二群集执行流水线。第一群集执行流水线可以包括被配置为执行第一复合向量指令的一个或多个复杂算术逻辑单元数据路径。第二群集执行流水线可以包括被配置为执行第二复合向量指令的一个或多个复数乘法器累加器数据路径。

5. 发明授权

US07415595B2 Data processing without processor core intervention by chain of accelerators selectively coupled by programmable interconnect network and to memory 有权
标题翻译：通过可编程互连网络和存储器选择性耦合的加速器链，无需处理器核心干预的数据处理
公开(公告)号：US07415595B2
公开(公告)日：2008-08-19
申请号：US11135964
申请日：2005-05-24
申请人： Eric Johan Tell , Anders Henrik Nilsson , Dake Liu
发明人： Eric Johan Tell , Anders Henrik Nilsson , Dake Liu
IPC分类号： G06F15/16
CPC分类号： G06F15/7857 , G06F9/30036 , G06F9/30079 , G06F9/3851 , G06F9/3885 , G06F9/3891 , H04B1/0003 , Y02D10/13
摘要： A programmable digital signal processor includes a plurality of memory units, a plurality of accelerator units and a processor core. The digital signal processor also includes a programmable network that may be configured to selectively provide connectivity between the memory units, the accelerator units, and the processor core. Each of the accelerator units may be configured to perform one or more dedicated functions. The processor core may include an execution unit that may be configured to execute instructions that are associated with datapath flow control. The programmable network may be configured to selectively provide the connectivity in response to execution of particular instructions.
摘要翻译：可编程数字信号处理器包括多个存储器单元，多个加速器单元和处理器核。数字信号处理器还包括可配置为选择性地提供存储器单元，加速器单元和处理器核之间的连接的可编程网络。每个加速器单元可以被配置为执行一个或多个专用功能。处理器核心可以包括可被配置为执行与数据路径流控制相关联的指令的执行单元。可编程网络可以被配置为响应于特定指令的执行选择性地提供连接。

6. 发明申请

US20070168408A1 Parallel system and method for acceleration of multiple channel LMS based algorithms 审中-公开
标题翻译：用于加速多通道LMS算法的并行系统和方法
公开(公告)号：US20070168408A1
公开(公告)日：2007-07-19
申请号：US11332750
申请日：2006-01-13
申请人： Nick Skelton , Harald Bergh , Dake Liu , Tommy Eriksson , Niklas Persson , Stig Stuns
发明人： Nick Skelton , Harald Bergh , Dake Liu , Tommy Eriksson , Niklas Persson , Stig Stuns
IPC分类号： G06F17/10
CPC分类号： H03H21/0043 , H03H2021/0056 , H03H2218/06 , H04L2025/03617
摘要： A parallel system for performing LMS coefficient adaptation includes a data memory, a tap memory, and two or more LMS hardware units. The LMS hardware units utilize data stored in the data memory and coefficients stored in the tap memory for performing multiple LMS coefficient adaptations in parallel.
摘要翻译：用于执行LMS系数适配的并行系统包括数据存储器，抽头存储器和两个或更多个LMS硬件单元。 LMS硬件单元利用存储在数据存储器中的数据和存储在抽头存储器中的系数并行执行多个LMS系数适应。

7. 发明申请

US20060271765A1 Digital signal processor including a programmable network 有权
标题翻译：数字信号处理器包括可编程网络
公开(公告)号：US20060271765A1
公开(公告)日：2006-11-30
申请号：US11135964
申请日：2005-05-24
申请人： Eric Tell , Anders Nilsson , Dake Liu
发明人： Eric Tell , Anders Nilsson , Dake Liu
IPC分类号： G06F15/00
CPC分类号： G06F15/7857 , G06F9/30036 , G06F9/30079 , G06F9/3851 , G06F9/3885 , G06F9/3891 , H04B1/0003 , Y02D10/13
摘要： A programmable digital signal processor includes a plurality of memory units, a plurality of accelerator units and a processor core. The digital signal processor also includes a programmable network that may be configured to selectively provide connectivity between the memory units, the accelerator units, and the processor core. Each of the accelerator units may be configured to perform one or more dedicated functions. The processor core may include an execution unit that may be configured to execute instructions that are associated with datapath flow control. The programmable network may be configured to selectively provide the connectivity in response to execution of particular instructions.
摘要翻译：可编程数字信号处理器包括多个存储器单元，多个加速器单元和处理器核。数字信号处理器还包括可配置为选择性地提供存储器单元，加速器单元和处理器核之间的连接的可编程网络。每个加速器单元可以被配置为执行一个或多个专用功能。处理器核心可以包括可被配置为执行与数据路径流控制相关联的指令的执行单元。可编程网络可以被配置为响应于特定指令的执行选择性地提供连接。

8. 发明授权

US06963586B2 Method and apparatus for general-purpose packet reception processing 有权
标题翻译：用于通用分组接收处理的方法和装置
公开(公告)号：US06963586B2
公开(公告)日：2005-11-08
申请号：US09934372
申请日：2001-08-21
申请人： Tomas Henriksson , Dake Liu , Harald Bergh
发明人： Tomas Henriksson , Dake Liu , Harald Bergh
IPC分类号： H04L29/06 , H04J3/26
CPC分类号： H04L69/22
摘要： A protocol processor for processing first header information of a reception packet to provide instructions for processing second header data of a reception packet is provided. For efficient protocol processing, special hardware architectures are necessary. Hardware architectures for dynamic length input buffer, no penalty conditional jump, one clock-cycle case-based jump, accumulated partial comparison, and integrated layer processing on-the-fly are described. The architectures are used in a domain-specific protocol processor, which is based on program controlled execution. The processor does not operate on data stored in a memory, but on an incoming packet-flow with constant speed. The processor performs every instruction in one clock-cycle, including conditional jump (taken and not taken) and case based jump.
摘要翻译：提供了一种用于处理接收分组的第一报头信息以提供用于处理接收分组的第二报头数据的指令的协议处理器。为了有效的协议处理，需要特殊的硬件架构。描述了用于动态长度输入缓冲器的硬件架构，无罚币条件跳转，一个基于时钟周期的基于情况的跳转，累积部分比较和集成层处理。架构在特定于域的协议处理器中使用，该处理器基于程序控制执行。处理器不对存储在存储器中的数据进行操作，而是对具有恒定速度的传入分组流进行操作。处理器在一个时钟周期内执行每个指令，包括条件跳转（已采取和未采用）和基于情况的跳转。

9. 发明授权

US06714956B1 Hardware accelerator for normal least-mean-square algorithm-based coefficient adaptation 有权
标题翻译：用于正态最小均方算法的系数适应的硬件加速器
公开(公告)号：US06714956B1
公开(公告)日：2004-03-30
申请号：US09624430
申请日：2000-07-24
申请人： Dake Liu , Stig Stuns , Harald Bergh , Nick Skelton
发明人： Dake Liu , Stig Stuns , Harald Bergh , Nick Skelton
IPC分类号： G06F1710
CPC分类号： H03H21/0043
摘要： A system and method for accelerating least-mean-square algorithm-based coefficient adaptation which executes in one machine clock cycle one tap of the least-mean-square algorithm including data fetch, coefficient fetch, coefficient adaptation, convolution, and write-back of a new coefficient vector. A data memory stores an input signal. A coefficient memory stores a coefficient vector. A multiplication and accumulation unit reads the input signal from the data memory and the coefficient vector from the coefficient memory to perform convolution. A coefficient adaptation unit separate from the multiplication and accumulation unit reads the input signal from the data memory and reads the coefficient vector from the coefficient memory to perform coefficient adaptation at the same time that the multiplication and accumulation unit performs the reading to produce an adapted coefficient vector which is written back into the coefficient memory for use by the multiplication and accumulation unit during a next iteration of convolution to produce an output signal, wherein each tap is executed in one machine clock cycle.
摘要翻译：一种用于加速基于最小均方算法的系数适应的系统和方法，其在一个机器时钟周期中执行最小均方算法的一个抽头，包括数据提取，系数取数，系数适应，卷积和回写一个新的系数向量。数据存储器存储输入信号。系数存储器存储系数向量。乘法和累加单元从数据存储器读取输入信号和从系数存储器读取系数向量以进行卷积。与乘法和累加单元分离的系数适配单元从数据存储器读取输入信号，并从系数存储器读取系数向量，以在乘法和累加单元执行读取以产生适应系数的同时执行系数自适应向量，其被写回到系数存储器中，以在下一次卷积迭代期间由乘法和累积单元使用以产生输出信号，其中每个抽头在一个机器时钟周期中执行。

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