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1. 发明授权

US5683941A Self-aligned polycide process that utilizes a planarized layer of material to expose polysilicon structures to a subsequently deposited metal layer that is reacted to form the metal silicide 失效
标题翻译：自对准多晶硅方法，其利用平坦化的材料层将多晶硅结构暴露于随后沉积的金属层，其反应形成金属硅化物
公开(公告)号：US5683941A
公开(公告)日：1997-11-04
申请号：US678417
申请日：1996-07-02
申请人： Dah-Bin Kao , John Pierce
发明人： Dah-Bin Kao , John Pierce
IPC分类号： H01L21/28 , H01L21/321 , H01L21/768 , H01L21/8234 , H01L21/8238 , H01L21/44
CPC分类号： H01L21/76889 , H01L21/28052 , H01L21/321 , H01L21/823443 , H01L21/823835
摘要： The process for forming a layer of metal silicide over polysilicon structures, such as gates and interconnect lines, is simplified by forming a layer of insulation material over the polysilicon structures, removing the layer of insulation material until the layer of insulation material is substantially planar and the thickness of the insulation material over the polysilicon structures is within a predetermined thickness range, etching the planarized layer of insulation material until portions of the polysilicon structures are exposed, depositing a layer of metal over the resulting structure, and then reacting the metal layer with the polysilicon structures to form the layer of metal silicide.
摘要翻译：通过在多晶硅结构上形成绝缘材料层，去除绝缘材料层直到绝缘材料层基本上是平面的，简化了在多晶硅结构上形成金属硅化物层（例如栅极和互连线）的工艺，多晶硅结构上的绝缘材料的厚度在预定的厚度范围内，蚀刻绝缘材料的平坦化层，直到多晶硅结构的部分露出，在所得结构上沉积一层金属，然后使金属层与多晶硅结构形成金属硅化物层。

2. 发明授权

US5759882A Method of fabricating self-aligned contacts and local interconnects in CMOS and BICMOS processes using chemical mechanical polishing (CMP) 失效
标题翻译：在CMOS和BICMOS工艺中使用化学机械抛光（CMP）制造自对准触点和局部互连的方法
公开(公告)号：US5759882A
公开(公告)日：1998-06-02
申请号：US732018
申请日：1996-10-16
申请人： Dah-Bin Kao , John Pierce
发明人： Dah-Bin Kao , John Pierce
IPC分类号： H01L21/768 , H01L21/8249
CPC分类号： H01L21/768
摘要： A method of fabricating external contacts in an integrated circuit structure utilizes chemical mechanical polishing (CMP). The structure includes an active device substrate region defined by field oxides. First and second diffusions formed in the active region define a substrate surface region therebetween. In accordance with the method, a layer of amorphous or polycrystalline silicon is formed in contact with the diffusion regions, subjected to a chemical mechanical polishing (CMP) step and then etched to form external contacts. The process flow can be applied to CMOS technologies and adapted to bipolar technologies to provide a BiCMOS flow.
摘要翻译：在集成电路结构中制造外部触点的方法采用化学机械抛光（CMP）。该结构包括由场氧化物限定的有源器件衬底区域。在有源区域中形成的第一和第二扩散限定了它们之间的衬底表面区域。根据该方法，形成与扩散区接触的非晶或多晶硅层，经受化学机械抛光（CMP）步骤，然后蚀刻以形成外部触点。工艺流程可以应用于CMOS技术，并适用于双极技术以提供BiCMOS流程。

3. 发明授权

US06323089B1 Semiconductor memory array with buried drain lines and processing methods therefor 失效
标题翻译：具有埋地漏极线的半导体存储器阵列及其处理方法
公开(公告)号：US06323089B1
公开(公告)日：2001-11-27
申请号：US09309242
申请日：1999-05-10
申请人： Dah-Bin Kao , Loc B. Hoang , Albert T. Wu , Tung-Yi Chan
发明人： Dah-Bin Kao , Loc B. Hoang , Albert T. Wu , Tung-Yi Chan
IPC分类号： H01L218247
CPC分类号： H01L27/11521 , G11C16/0425 , H01L27/115 , H01L29/42324
摘要： A semiconductor memory array and methods therefor is provided herein comprising a substrate; a plurality of memory cell field effect transistors formed on said substrate and being arranged thereon into rows and columns of transistors, each transistor includes a channel region interposed between drain and source regions, and overlaid by a control gate region; a plurality of first diffused elongated regions formed within said substrate that electrically connect in common the drain regions of transistors in respective columns; a plurality of second diffused elongated region formed within said substrate that electrically connect in common the source regions of transistors in respective columns; and a plurality of elongated conductive line formed over said substrate that electrically connect in common the control gate regions of transistors in respective rows.
摘要翻译：本文提供了一种半导体存储器阵列及其方法，包括：衬底; 多个存储单元场效应晶体管，形成在所述基板上并被布置在晶体管的行和列中，每个晶体管包括介于漏极和源极区之间并由控制栅极区重叠的沟道区; 形成在所述基板内的多个第一扩散细长区域，其共同地将各个晶体管的漏极区域电连接; 形成在所述衬底内的多个第二扩散细长区域，其共同地将各个晶体管的源极区域电连接; 以及形成在所述衬底上的多个细长导电线，其共同地电连接相应行中的晶体管的控制栅极区域。

4. 发明授权

US5762755A Organic preclean for improving vapor phase wafer etch uniformity 失效
标题翻译：用于改善气相晶片蚀刻均匀性的有机预清洁剂
公开(公告)号：US5762755A
公开(公告)日：1998-06-09
申请号：US994604
申请日：1992-12-21
申请人： Michael A. McNeilly , John M. deLarios , Glenn L. Nobinger , Wilbur C. Krusell , Dah-Bin Kao , Ralph K. Manriquez , Chiko Fan
发明人： Michael A. McNeilly , John M. deLarios , Glenn L. Nobinger , Wilbur C. Krusell , Dah-Bin Kao , Ralph K. Manriquez , Chiko Fan
IPC分类号： H01L21/00 , H01L21/306 , H01L21/311 , H01L21/302
CPC分类号： H01L21/02046 , H01L21/02019 , H01L21/02049 , H01L21/02052 , H01L21/30604 , H01L21/31116 , H01L21/67069 , Y10S438/906
摘要： A method for achieving greater uniformity and control in vapor phase etching of silicon, silicon oxide layers and related materials associated with wafers used for semiconductor devices comprises the steps of first cleaning the wafer surface to remove organics, followed by vapor phase etching. An integrated apparatus for cleaning organic and, subsequently, vapor phase etching, is also described. In embodiments of the invention cooling steps are incorporated to increase throughput, an on-demand vaporizer is provided to repeatably supply vapor at other than azeotropic concentration, and a residue-free etch process is provided.
摘要翻译：用于实现与用于半导体器件的晶片相关联的硅，氧化硅层和相关材料的气相蚀刻中更大的均匀性和控制的方法包括以下步骤：首先清洁晶片表面以去除有机物，随后进行气相蚀刻。还描述了一种用于清洁有机物并随后进行气相蚀刻的集成设备。在本发明的实施例中，结合冷却步骤以增加生产量，提供按需蒸发器以在不同于共沸浓度的情况下重复地供应蒸气，并且提供无残留的蚀刻工艺。

5. 发明授权

US5492847A Counter-implantation method of manufacturing a semiconductor device with self-aligned anti-punchthrough pockets 失效
标题翻译：用于制造具有自对准反穿孔袋的半导体器件的对置方法
公开(公告)号：US5492847A
公开(公告)日：1996-02-20
申请号：US283458
申请日：1994-08-01
申请人： Dah-Bin Kao , Gregory S. Scott
发明人： Dah-Bin Kao , Gregory S. Scott
IPC分类号： H01L21/336 , H01L29/10 , H01L29/78 , H01L21/266
CPC分类号： H01L29/66492 , H01L29/1083 , H01L29/6659 , H01L29/7836 , Y10S438/919
摘要： A method of processing a semiconductor device shapes a layer buried within a substrate of the semiconductor device. This layer has a conductivity the same as that of the substrate but has a higher doping level. In this process, a region of the layer is selected and ions of an opposite conductivity to the selected layer are counter-implanted in the region so that the doping level of the region is substantially canceled. A region of the layer adjacent to the counter-implanted region retains a higher doping level. Alternative techniques are employed to protect the doped region against the counter-implant. In a first approach, the layer is doped and subsequently a mask is formed on the surface of the substrate. The mask is furnished by a part of the semiconductor device, such as a spacer which is connected to the gate electrode after the dopant layer is formed in the substrate. After the mask is formed, ions are counter-implanted with the mask protecting the doped region. In a second approach, both the ion implant forming the doped layer and the counter-implant are performed after masking structures are formed, however the ion implant is a large-angle implant which implants ions beneath the masking structure while the counter-implant is a perpendicular implant so that regions beneath the masking structure are protected from cancellation.
摘要翻译：半导体器件的处理方法对埋在半导体器件的衬底内的层进行成形。该层具有与衬底相同的导电性，但具有较高的掺杂水平。在该过程中，选择该层的区域，并且与所选择的层具有相反导电性的离子在该区域中反向注入，使得区域的掺杂水平基本上被抵消。与反注入区相邻的层的区域保持较高的掺杂水平。采用替代技术来保护掺杂区域免受反向植入。在第一种方法中，该层被掺杂，随后在衬底的表面上形成掩模。掩模由半导体器件的一部分提供，例如在衬底中形成掺杂剂层之后连接到栅电极的间隔物。在形成掩模之后，用保护掺杂区域的掩模对离子进行反注入。在第二种方法中，形成掺杂层和对置注入的离子注入都是在形成掩模结构之后进行的，然而离子注入是在掩模结构下面植入离子的大角度注入，而反植入物是使得掩蔽结构下面的区域被保护而不被抵消。

6. 发明授权

US5294568A Method of selective etching native oxide 失效
标题翻译：选择性蚀刻天然氧化物的方法
公开(公告)号：US5294568A
公开(公告)日：1994-03-15
申请号：US867299
申请日：1992-04-10
申请人： Michael A. McNeilly , Bruce E. Deal , Dah-Bin Kao , John de Larios
发明人： Michael A. McNeilly , Bruce E. Deal , Dah-Bin Kao , John de Larios
IPC分类号： C04B41/53 , H01L21/00 , H01L21/306 , H01L21/311 , H01L21/02
CPC分类号： H01L21/02046 , C04B41/5346 , H01L21/31116 , H01L21/67069 , Y10S148/017 , Y10S148/051 , Y10S438/906 , Y10S438/974
摘要： A method of selective etching of native oxide on a substrate is disclosed in which hydrogen halide vapor and water vapor are exposed to the substrate surface under appropriate conditions and long enough to remove native oxide but not long enough to remove any significant amount of other oxides. Treating conditions are maintained to prevent water vapor from condensing on the substrate until sufficient native oxide is etched so that substantially all the native oxide will be etched before appreciable other oxides are etched.
摘要翻译：公开了一种在衬底上选择性蚀刻天然氧化物的方法，其中卤化氢蒸汽和水蒸汽在合适的条件下暴露于衬底表面，并足够长的时间以除去天然氧化物，但不足以除去任何显着量的其它氧化物。保持处理条件以防止水蒸汽在基底上冷凝，直到蚀刻足够的自然氧化物，使得在可观的其它氧化物被蚀刻之前基本上所有的天然氧化物将被蚀刻。

7. 发明授权

US06274436B1 Method for forming minute openings in semiconductor devices 有权
标题翻译：在半导体器件中形成微小开口的方法
公开(公告)号：US06274436B1
公开(公告)日：2001-08-14
申请号：US09256264
申请日：1999-02-23
申请人： Dah-Bin Kao , Albert T. Wu , Tung-Yi Chan
发明人： Dah-Bin Kao , Albert T. Wu , Tung-Yi Chan
IPC分类号： H01L218247
CPC分类号： H01L27/11521 , G11C16/0416 , H01L29/42324
摘要： A method is disclosed for creating a sub-minimum opening in a semiconductor device, comprising the steps of: a) providing a first layer; b) providing a second layer over said first layer; c) providing a third layer over said second layer; d) providing a photoresist mask over said third layer; e) etching said third layer to form defined structures; f) depositing a fourth layer for forming spacers; g) etching said fourth layer to form said spacers; and h) etching said first layer to form an opening in said first layer. In etching the fourth layer to form the spacers, the third layer is generally etched away to form an opening to the first layer, and, in the following step, an opening (or feature) can be etched on the first layer. Generally speaking, the first and third layers can be of any material and should have similar etching rate; the second and fourth layers can be of any material and should have similar etching rate. However, the material for the first and third layers versus the material for the second and fourth layers should have highly dissimilar etching rates. Materials for these layers include and are not limited to polysilicon, oxide, nitride, and metal.
摘要翻译：公开了一种用于在半导体器件中产生次最小开口的方法，包括以下步骤：a）提供第一层; b）在所述第一层上提供第二层; c）在所述第二层上提供第三层; d）在所述第三层上提供光刻胶掩模; e）蚀刻所述第三层以形成限定的结构; f）沉积用于形成间隔物的第四层; g）蚀刻所述第四层以形成所述间隔物; 以及h）蚀刻所述第一层以在所述第一层中形成开口。在蚀刻第四层以形成间隔物时，通常蚀刻掉第三层以形成到第一层的开口，并且在随后的步骤中，可以在第一层上蚀刻开口（或特征）。一般来说，第一层和第三层可以是任何材料，并且应该具有相似的蚀刻速率; 第二层和第四层可以是任何材料，并且应该具有相似的蚀刻速率。然而，第一层和第三层的材料与第二层和第四层的材料应具有高度不同的蚀刻速率。这些层的材料包括但不限于多晶硅，氧化物，氮化物和金属。

8. 发明授权

US06876031B1 Method and apparatus for split gate source side injection flash memory cell and array with dedicated erase gates 有权
标题翻译：用于具有专用擦除栅极的分离栅极源侧注入闪存单元和阵列的方法和装置
公开(公告)号：US06876031B1
公开(公告)日：2005-04-05
申请号：US09256265
申请日：1999-02-23
申请人： Dah-Bin Kao , Loc B. Hoang , Albert T. Wu , Tung-Yi Chan
发明人： Dah-Bin Kao , Loc B. Hoang , Albert T. Wu , Tung-Yi Chan
IPC分类号： G11C16/04 , H01L21/8247 , H01L27/115 , H01L29/423 , H01L29/788
CPC分类号： H01L27/11521 , G11C16/0416 , H01L27/115 , H01L29/42324
摘要： A transistor structure having a dedicated erase gate where the transistor can be used as a memory cell is disclosed. The presently preferred embodiment of the transistor comprises a floating gate disposed on a substrate and having a control gate and an erase gate overlapping said floating gate, with drain and source regions doped on the substrate. By providing a dedicated erase gate, the gate oxide underneath the control gate can be made thinner and can have a thickness that is conducive to the scaling of the transistor. The overall cell size of the transistor remains the same and the program and read operation can remain the same. Both the common source and buried bitline architecture can be used, namely twin well or triple well architectures. A memory circuit using the transistors of the present invention is disclosed as well for flash memory circuit applications.
摘要翻译：公开了具有专用擦除栅极的晶体管结构，其中晶体管可用作存储单元。晶体管的当前优选实施例包括设置在衬底上的浮置栅极，并且具有与所述浮置栅极重叠的控制栅极和擦除栅极，掺杂在衬底上的漏极和源极区域。通过提供专用的擦除栅极，可以使控制栅极下方的栅极氧化物变得更薄，并且可以具有有利于晶体管缩放的厚度。晶体管的整体单元尺寸保持相同，并且程序和读取操作可以保持不变。可以使用共同的源和掩埋位线架构，即双阱或三阱架构。对于闪存电路应用也公开了使用本发明的晶体管的存储电路。

9. 发明授权

US06211547B1 Semiconductor memory array with buried drain lines and processing methods therefor 失效
标题翻译：具有埋地漏极线的半导体存储器阵列及其处理方法
公开(公告)号：US06211547B1
公开(公告)日：2001-04-03
申请号：US08976751
申请日：1997-11-24
申请人： Dah-Bin Kao , Loc B. Hoang , Albert T. Wu , Tung-Yi Chan
发明人： Dah-Bin Kao , Loc B. Hoang , Albert T. Wu , Tung-Yi Chan
IPC分类号： H01L29788
CPC分类号： H01L27/11521 , G11C16/0425 , H01L27/115 , H01L29/42324
摘要： A semiconductor memory array and methods therefor is provided herein comprising a substrate; a plurality of memory cell field effect transistors formed on said substrate and being arranged thereon into rows and columns of transistors, each transistor includes a channel region interposed between drain and source regions, and overlaid by a control gate region; a plurality of first diffused elongated regions formed within said substrate that electrically connect in common the drain regions of transistors in respective columns; a plurality of second diffused elongated regions formed within said substrate that electrically connect in common the source regions of transistors in respective columns; and a plurality of elongated conductive line formed over said substrate that electrically connect in common the control gate regions of transistors in respective rows.
摘要翻译：本文提供了一种半导体存储器阵列及其方法，包括：衬底; 多个存储单元场效应晶体管，形成在所述基板上并被布置在晶体管的行和列中，每个晶体管包括介于漏极和源极区之间并由控制栅极区重叠的沟道区; 形成在所述基板内的多个第一扩散细长区域，其共同地将各个晶体管的漏极区域电连接; 形成在所述衬底内的多个第二扩散细长区域，其共同地将各个晶体管的源极区域电连接; 以及形成在所述衬底上的多个细长导电线，其共同地电连接相应行中的晶体管的控制栅极区域。

10. 发明授权

US5986934A Semiconductor memory array with buried drain lines and methods therefor 失效
标题翻译：具有埋漏极线的半导体存储器阵列及其方法
公开(公告)号：US5986934A
公开(公告)日：1999-11-16
申请号：US977647
申请日：1997-11-24
申请人： Dah-Bin Kao , Loc B. Hoang , Albert Wu , Tung-Yi Chan
发明人： Dah-Bin Kao , Loc B. Hoang , Albert Wu , Tung-Yi Chan
IPC分类号： G11C16/04 , G11C16/10 , G11C16/16 , G11C16/26 , H01L27/115
CPC分类号： H01L27/115 , G11C16/0491 , G11C16/10 , G11C16/16 , G11C16/26 , G11C2216/28
摘要： A semiconductor memory array and methods therefor is provided herein comprising a substrate; a plurality of memory cell field effect transistors formed on said substrate and being arranged thereon into rows and columns of transistors, each transistor includes a channel region interposed between drain and source regions, and overlaid by a control gate region; a plurality of first diffused elongated regions formed within said substrate that electrically connect in common the drain regions of transistors in respective columns; a plurality of second diffused elongated regions formed within said substrate that electrically connect in common the source regions of transistors in respective columns; and a plurality of elongated conductive line formed over said substrate that electrically connect in common the control gate regions of transistors in respective rows.
摘要翻译：本文提供了一种半导体存储器阵列及其方法，包括：衬底; 多个存储单元场效应晶体管，形成在所述基板上并被布置在晶体管的行和列中，每个晶体管包括介于漏极和源极区之间并由控制栅极区重叠的沟道区; 形成在所述基板内的多个第一扩散细长区域，其共同地将各个晶体管的漏极区域电连接; 形成在所述衬底内的多个第二扩散细长区域，其共同地将各个晶体管的源极区域电连接; 以及形成在所述衬底上的多个细长导电线，其共同地电连接相应行中的晶体管的控制栅极区域。

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