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1. 发明授权

US08923067B2 Memory system and method of operating memory system using soft read voltages 有权
标题翻译：使用软读取电压操作存储器系统的存储器系统和方法
公开(公告)号：US08923067B2
公开(公告)日：2014-12-30
申请号：US14050430
申请日：2013-10-10
申请人： Dae-seok Byeon , Bo-geun Kim , Jae-woo Park
发明人： Dae-seok Byeon , Bo-geun Kim , Jae-woo Park
IPC分类号： G11C16/28 , G11C16/04 , G11C16/26 , G11C16/34
CPC分类号： G11C16/0483 , G11C16/26 , G11C16/28 , G11C16/3404 , G11C16/3422
摘要： A method is provided for operating a memory system. The method includes reading nonvolatile memory cells using a first soft read voltage, a voltage level difference between the first soft read voltage and a first hard read voltage being indicated by a first voltage value; and reading the nonvolatile memory cells using a second soft read voltage paired with the first soft read voltage, a voltage level difference between the second soft read voltage and the first hard read voltage being indicated by a second voltage value. The second voltage value is different than the first voltage value. Also, a difference between the first voltage value and the second voltage value corresponds to the degree of asymmetry of adjacent threshold voltage distributions among multiple threshold voltage distributions set for the nonvolatile memory cells of the memory system.
摘要翻译：提供了一种用于操作存储器系统的方法。该方法包括使用第一软读取电压读取非易失性存储器单元，由第一电压值表示第一软读取电压和第一硬读取电压之间的电压电平差; 以及使用与第一软读取电压成对的第二软读取电压读取非易失性存储单元，第二软读取电压和第一硬读取电压之间的电压电平差由第二电压值指示。第二电压值不同于第一电压值。此外，第一电压值和第二电压值之间的差异对应于针对存储器系统的非易失性存储器单元设置的多个阈值电压分布中的相邻阈值电压分布的不对称程度。

2. 发明申请

US20140153338A1 MEMORY SYSTEM AND METHOD OF OPERATING MEMORY SYSTEM USING SOFT READ VOLTAGES 有权
标题翻译：使用软读取电压操作存储器系统的存储器系统和方法
公开(公告)号：US20140153338A1
公开(公告)日：2014-06-05
申请号：US14050430
申请日：2013-10-10
申请人： Dae-seok Byeon , Bo-geun Kim , Jae-woo Park
发明人： Dae-seok Byeon , Bo-geun Kim , Jae-woo Park
IPC分类号： G11C16/28
CPC分类号： G11C16/0483 , G11C16/26 , G11C16/28 , G11C16/3404 , G11C16/3422
摘要： A method is provided for operating a memory system. The method includes reading nonvolatile memory cells using a first soft read voltage, a voltage level difference between the first soft read voltage and a first hard read voltage being indicated by a first voltage value; and reading the nonvolatile memory cells using a second soft read voltage paired with the first soft read voltage, a voltage level difference between the second soft read voltage and the first hard read voltage being indicated by a second voltage value. The second voltage value is different than the first voltage value. Also, a difference between the first voltage value and the second voltage value corresponds to the degree of asymmetry of adjacent threshold voltage distributions among multiple threshold voltage distributions set for the nonvolatile memory cells of the memory system.
摘要翻译：提供了一种用于操作存储器系统的方法。该方法包括使用第一软读取电压读取非易失性存储器单元，由第一电压值表示第一软读取电压和第一硬读取电压之间的电压电平差; 以及使用与第一软读取电压成对的第二软读取电压读取非易失性存储单元，第二软读取电压和第一硬读取电压之间的电压电平差由第二电压值指示。第二电压值不同于第一电压值。此外，第一电压值和第二电压值之间的差异对应于针对存储器系统的非易失性存储器单元设置的多个阈值电压分布中的相邻阈值电压分布的不对称程度。

3. 发明授权

US08773914B2 Semiconductor memory device and related methods for performing read and verification operations 有权
标题翻译：半导体存储器件和用于执行读取和验证操作的相关方法
公开(公告)号：US08773914B2
公开(公告)日：2014-07-08
申请号：US13116036
申请日：2011-05-26
申请人： Hwa-seok Lee , Bo-geun Kim
发明人： Hwa-seok Lee , Bo-geun Kim
IPC分类号： G11C11/34
CPC分类号： G11C16/26 , G11C16/32
摘要： A semiconductor memory device comprises a memory cell array configured to store data, a sensing unit configured to perform a read operation the memory cell array by sensing a bitline in a plurality of reading steps in response to a single read command, and a sensing time controller configured to generate a control signal to control a variable reading time for each reading step of the sensing unit.
摘要翻译：半导体存储器件包括：存储单元阵列，被配置为存储数据;感测单元，被配置为通过响应于单个读取命令感测多个读取步骤中的位线来执行存储单元阵列的读取操作;以及感测时间控制器被配置为产生控制信号以控制感测单元的每个读取步骤的可变读取时间。

4. 发明授权

US08149621B2 Flash memory device and method of testing the flash memory device 有权
标题翻译：闪存设备和测试闪存设备的方法
公开(公告)号：US08149621B2
公开(公告)日：2012-04-03
申请号：US12585725
申请日：2009-09-23
申请人： Bo-geun Kim , Dae-yong Kim , Jun-yong Park
发明人： Bo-geun Kim , Dae-yong Kim , Jun-yong Park
IPC分类号： G11C11/34
CPC分类号： G11C29/12 , G11C16/04 , G11C2029/1208
摘要： A flash memory device and a method of testing the flash memory device are provided. The flash memory device may include a memory cell array including a plurality of bit lines, a control unit configured to output estimated data and an input/output buffer unit including a plurality of page buffers. Each of the plurality of page buffers corresponds to one of the plurality of bit lines in the memory cell array and is configured to read test data programmed in at least a first page of a memory cell array, compare the read-out test data with the estimated data to determine whether the corresponding bit line is in a pass or failure state and output a test result signal. A voltage of the test result signal is maintained when test data of a second page of the memory cell array is read if the corresponding bit line in the first page is in a failure state.
摘要翻译：提供一种闪存设备和测试闪存设备的方法。闪存器件可以包括包括多个位线的存储单元阵列，被配置为输出估计数据的控制单元和包括多个页缓冲器的输入/输出缓冲单元。多个页缓冲器中的每一个对应于存储单元阵列中的多个位线之一，并且被配置为读取在存储单元阵列的至少第一页中编程的测试数据，将读出的测试数据与估计数据，以确定对应的位线是否处于通过或故障状态，并输出测试结果信号。如果第一页中的相应位线处于故障状态，则读取存储单元阵列的第二页的测试数据时，维持测试结果信号的电压。

5. 发明申请

US20100103743A1 Flash memory device and method of testing the flash memory device 有权
标题翻译：闪存设备和测试闪存设备的方法
公开(公告)号：US20100103743A1
公开(公告)日：2010-04-29
申请号：US12585725
申请日：2009-09-23
申请人： Bo-geun Kim , Dae-yong Kim , Jun-yong Park
发明人： Bo-geun Kim , Dae-yong Kim , Jun-yong Park
IPC分类号： G11C16/06 , G11C7/10 , G11C29/00 , G11C7/00
CPC分类号： G11C29/12 , G11C16/04 , G11C2029/1208
摘要： A flash memory device and a method of testing the flash memory device are provided. The flash memory device may include a memory cell array including a plurality of bit lines, a control unit configured to output estimated data and an input/output buffer unit including a plurality of page buffers. Each of the plurality of page buffers corresponds to one of the plurality of bit lines in the memory cell array and is configured to read test data programmed in at least a first page of a memory cell array, compare the read-out test data with the estimated data to determine whether the corresponding bit line is in a pass or failure state and output a test result signal. A voltage of the test result signal is maintained when test data of a second page of the memory cell array is read if the corresponding bit line in the first page is in a failure state.
摘要翻译：提供一种闪存设备和测试闪存设备的方法。闪存器件可以包括包括多个位线的存储单元阵列，被配置为输出估计数据的控制单元和包括多个页缓冲器的输入/输出缓冲单元。多个页缓冲器中的每一个对应于存储单元阵列中的多个位线之一，并且被配置为读取在存储单元阵列的至少第一页中编程的测试数据，将读出的测试数据与估计数据，以确定对应的位线是否处于通过或故障状态，并输出测试结果信号。如果第一页中的相应位线处于故障状态，则读取存储单元阵列的第二页的测试数据时，维持测试结果信号的电压。

6. 发明授权

US09261940B2 Memory system controlling peak current generation for a plurality of memories by monitoring a peak signal to synchronize an internal clock of each memory by a processor clock at different times 有权
标题翻译：存储器系统通过监视峰值信号来控制多个存储器的峰值电流产生，以使每个存储器的内部时钟以不同时间的处理器时钟同步
公开(公告)号：US09261940B2
公开(公告)日：2016-02-16
申请号：US13396618
申请日：2012-02-15
申请人： Bo-geun Kim , Kye-hyun Kyung , Jae-yong Jeong , Seung-hun Choi , Seok-cheon Kwon , Chul-ho Lee
发明人： Bo-geun Kim , Kye-hyun Kyung , Jae-yong Jeong , Seung-hun Choi , Seok-cheon Kwon , Chul-ho Lee
IPC分类号： G06F1/12 , G06F13/42 , H04L5/00 , H04L7/00 , G06F1/32 , G06F1/14 , G06F13/16 , G06F1/04 , G11C7/22
CPC分类号： G06F1/12 , G06F1/04 , G06F1/14 , G06F1/3203 , G06F1/3225 , G06F1/3275 , G06F3/0604 , G06F3/0629 , G06F3/0683 , G06F13/1689 , G11C7/222 , Y02D10/14
摘要： A memory system includes a controller that generates a processor clock, and a plurality of memory devices each including an internal clock generator that generates an internal clock in synchronization with the processor clock, and a memory that performs a peak current generation operation in synchronization with the internal clock, wherein at least two of the memory devices generate their respective internal clocks at different times such that the corresponding peak current generation operations are performed at different times.
摘要翻译：存储器系统包括产生处理器时钟的控制器和多个存储器件，每个存储器件包括与处理器时钟同步地产生内部时钟的内部时钟发生器，以及与该处理器时钟同步地执行峰值电流产生操作的存储器内部时钟，其中至少两个存储器件在不同时间产生它们各自的内部时钟，使得相应的峰值电流产生操作在不同的时间执行。

7. 发明申请

US20110305091A1 SEMICONDUCTOR MEMORY DEVICE AND RELATED METHODS FOR PERFORMING READ AND VERIFICATION OPERATIONS 有权
标题翻译：半导体存储器件以及执行读取和验证操作的相关方法
公开(公告)号：US20110305091A1
公开(公告)日：2011-12-15
申请号：US13116036
申请日：2011-05-26
申请人： Hwa-seok Lee , Bo-geun Kim
发明人： Hwa-seok Lee , Bo-geun Kim
IPC分类号： G11C16/26 , G11C16/06
CPC分类号： G11C16/26 , G11C16/32
摘要： A semiconductor memory device comprises a memory cell array configured to store data, a sensing unit configured to perform a read operation the memory cell array by sensing a bitline in a plurality of reading steps in response to a single read command, and a sensing time controller configured to generate a control signal to control a variable reading time for each reading step of the sensing unit.
摘要翻译：半导体存储器件包括：存储单元阵列，被配置为存储数据;感测单元，被配置为通过响应于单个读取命令感测多个读取步骤中的位线来执行存储单元阵列的读取操作;以及感测时间控制器被配置为产生控制信号以控制感测单元的每个读取步骤的可变读取时间。

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