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1. 发明申请

US20120221880A1 MEMORY SYSTEM AND METHOD OF CONTROLLING SAME 有权
标题翻译：记忆系统及其控制方法
公开(公告)号：US20120221880A1
公开(公告)日：2012-08-30
申请号：US13396618
申请日：2012-02-15
申请人： BO-GEUN KIM , Kye-hyun Kyung , Jae-yong Jeong , Seung-hun Choi , Seok-cheon Kwon , Chul-ho Lee
发明人： BO-GEUN KIM , Kye-hyun Kyung , Jae-yong Jeong , Seung-hun Choi , Seok-cheon Kwon , Chul-ho Lee
IPC分类号： G06F1/12
CPC分类号： G06F1/12 , G06F1/04 , G06F1/14 , G06F1/3203 , G06F1/3225 , G06F1/3275 , G06F3/0604 , G06F3/0629 , G06F3/0683 , G06F13/1689 , G11C7/222 , Y02D10/14
摘要： A memory system comprises a controller that generates a processor clock, and a plurality of memory devices each comprising an internal clock generator that generates an internal clock in synchronization with the processor clock, and a memory that performs a peak current generation operation in synchronization with the internal clock, wherein at least two of the memory devices generate their respective internal clocks at different times such that the corresponding peak current generation operations are performed at different times.
摘要翻译：存储器系统包括产生处理器时钟的控制器和多个存储器件，每个存储器件包括与处理器时钟同步地产生内部时钟的内部时钟发生器，以及与所述处理器时钟同步地执行峰值电流产生操作的存储器内部时钟，其中至少两个存储器件在不同时间产生它们各自的内部时钟，使得相应的峰值电流产生操作在不同的时间执行。

2. 发明授权

US09261940B2 Memory system controlling peak current generation for a plurality of memories by monitoring a peak signal to synchronize an internal clock of each memory by a processor clock at different times 有权
标题翻译：存储器系统通过监视峰值信号来控制多个存储器的峰值电流产生，以使每个存储器的内部时钟以不同时间的处理器时钟同步
公开(公告)号：US09261940B2
公开(公告)日：2016-02-16
申请号：US13396618
申请日：2012-02-15
申请人： Bo-geun Kim , Kye-hyun Kyung , Jae-yong Jeong , Seung-hun Choi , Seok-cheon Kwon , Chul-ho Lee
发明人： Bo-geun Kim , Kye-hyun Kyung , Jae-yong Jeong , Seung-hun Choi , Seok-cheon Kwon , Chul-ho Lee
IPC分类号： G06F1/12 , G06F13/42 , H04L5/00 , H04L7/00 , G06F1/32 , G06F1/14 , G06F13/16 , G06F1/04 , G11C7/22
CPC分类号： G06F1/12 , G06F1/04 , G06F1/14 , G06F1/3203 , G06F1/3225 , G06F1/3275 , G06F3/0604 , G06F3/0629 , G06F3/0683 , G06F13/1689 , G11C7/222 , Y02D10/14
摘要： A memory system includes a controller that generates a processor clock, and a plurality of memory devices each including an internal clock generator that generates an internal clock in synchronization with the processor clock, and a memory that performs a peak current generation operation in synchronization with the internal clock, wherein at least two of the memory devices generate their respective internal clocks at different times such that the corresponding peak current generation operations are performed at different times.
摘要翻译：存储器系统包括产生处理器时钟的控制器和多个存储器件，每个存储器件包括与处理器时钟同步地产生内部时钟的内部时钟发生器，以及与该处理器时钟同步地执行峰值电流产生操作的存储器内部时钟，其中至少两个存储器件在不同时间产生它们各自的内部时钟，使得相应的峰值电流产生操作在不同的时间执行。

3. 再颁专利

USRE45222E1 Method of writing of writing to a flash memory including data blocks and log blocks, using a logical address having a block address portion and page identifying portion, a block address table and a page table 有权
标题翻译：使用具有块地址部分和页面识别部分的逻辑地址写入包括数据块和日志块的闪速存储器的方法，块地址表和页表
公开(公告)号：USRE45222E1
公开(公告)日：2014-10-28
申请号：US13134225
申请日：2011-06-02
申请人： Bum-soo Kim , Gui-young Lee , Jong-Min Kim , Ji-hyun In , Je-sung Kim , Sam-hyuk Noh , Sang-Iyul Min , Dong-hee Lee , Jae-yong Jeong , Yoo-kun Cho , Jong-moo Choi
发明人： Bum-soo Kim , Gui-young Lee , Jong-Min Kim , Ji-hyun In , Je-sung Kim , Sam-hyuk Noh , Sang-Iyul Min , Dong-hee Lee , Jae-yong Jeong , Yoo-kun Cho , Jong-moo Choi
IPC分类号： G06F12/00
CPC分类号： G06F12/0246 , G06F3/0679 , G06F13/4239 , G06F2212/2022 , G06F2212/7203
摘要： A flash memory management method is provided. According to the method, when a request to write the predetermined data to a page to which data has been written is made, the predetermined data is written to a log block corresponding to a data block containing the page. When a request to write the predetermined data to the page again is received, the predetermined data is written to an empty free page in the log block. Even if the same page is requested to be continuously written to, the management method allows this to be processed in one log block, thereby improving the effectiveness in the use of flash memory resources.
摘要翻译：提供闪存管理方法。根据该方法，当向预先写入数据的页面写入预定数据的请求时，将预定数据写入对应于包含页面的数据块的日志块。当接收到将预定数据再次写入页面的请求时，将预定数据写入日志块中的空闲空闲页面。即使请求连续写入同一页面，管理方法也可以在一个日志块中进行处理，从而提高闪存资源的使用效率。

4. 发明申请

US20090055579A1 Semiconductor memory device for simultaneously programming plurality of banks 审中-公开
标题翻译：用于同时编程多个存储体的半导体存储器件
公开(公告)号：US20090055579A1
公开(公告)日：2009-02-26
申请号：US12230142
申请日：2008-08-25
申请人： June-hong Park , Jae-yong Jeong , Chi-weon Yoon
发明人： June-hong Park , Jae-yong Jeong , Chi-weon Yoon
IPC分类号： G06F12/02
CPC分类号： G06F12/0246 , G06F2212/7202 , G11C11/5628 , G11C16/10 , G11C2216/14
摘要： Provided is a semiconductor memory device for simultaneously programming a plurality of banks. The semiconductor memory device includes: a memory cell array comprising a plurality of banks; a plurality of data buffers storing a plurality of pieces of program data to be programmed in the corresponding banks; and a plurality of scan latches configured to scan the plurality of program data transmitted from the corresponding data buffers, and configured to generate 1st through n−1th sub program data, n being a natural number greater than 2.
摘要翻译：提供了一种用于同时编程多个存储体的半导体存储器件。半导体存储器件包括：包括多个存储体的存储单元阵列; 多个数据缓冲器，存储要在对应的存储体中编程的多个程序数据; 以及多个扫描锁存器，被配置为扫描从相应的数据缓冲器发送的多个节目数据，并且被配置为生成第1到第n个第1个子节目数据，n是大于2的自然数。

5. 发明申请

US20060087889A1 Nonvolatile memory device and method of improving programming characteristic 失效
标题翻译：非易失性存储器件和改进编程特性的方法
公开(公告)号：US20060087889A1
公开(公告)日：2006-04-27
申请号：US11133286
申请日：2005-05-20
申请人： Jae-yong Jeong
发明人： Jae-yong Jeong
IPC分类号： G11C16/04
CPC分类号： G11C16/102 , G11C16/30
摘要： A method of programming a non-volatile memory device includes activating a first pump to generate a bitline voltage, and after the bulk voltage reaches a target voltage, detecting whether the bitline voltage is less than a detection voltage. When the bitline voltage is less than the detection voltage, a second pump becomes active.
摘要翻译：一种编程非易失性存储器件的方法包括激活第一泵以产生位线电压，并且在体电压达到目标电压之后，检测位线电压是否小于检测电压。当位线电压小于检测电压时，第二个泵变为有效。

6. 发明授权

US06938116B2 Flash memory management method 有权
标题翻译：闪存管理方法
公开(公告)号：US06938116B2
公开(公告)日：2005-08-30
申请号：US10029966
申请日：2001-12-31
申请人： Bum-soo Kim , Gui-young Lee , Jong-min Kim , Ji-hyun In , Je-sung Kim , Sam-hyuk Noh , Sang-lyul Min , Dong-hee Lee , Jae-yong Jeong , Yoo-kun Cho , Jong-moo Choi
发明人： Bum-soo Kim , Gui-young Lee , Jong-min Kim , Ji-hyun In , Je-sung Kim , Sam-hyuk Noh , Sang-lyul Min , Dong-hee Lee , Jae-yong Jeong , Yoo-kun Cho , Jong-moo Choi
IPC分类号： G06F12/16 , G06F12/00 , G06F12/02 , G06F13/42 , G11C16/02
CPC分类号： G06F12/0246 , G06F3/0679 , G06F13/4239 , G06F2212/2022 , G06F2212/7203
摘要： A flash memory management method is provided. According to the method, when a request to write the predetermined data to a page to which data has been written is made, the predetermined data is written to a log block corresponding to a data block containing the page. When a request to write the predetermined data to the page again is received, the predetermined data is written to an empty free page in the log block. Even if the same page is requested to be continuously written to, the management method allows this to be processed in one log block, thereby improving the effectiveness in the use of flash memory resources.
摘要翻译：提供闪存管理方法。根据该方法，当向预先写入数据的页面写入预定数据的请求时，将预定数据写入对应于包含页面的数据块的日志块。当接收到将预定数据再次写入页面的请求时，将预定数据写入日志块中的空闲空闲页面。即使请求连续写入同一页面，管理方法也可以在一个日志块中进行处理，从而提高闪存资源的使用效率。

7. 再颁专利

USRE44052E1 Flash memory management method 有权
公开(公告)号：USRE44052E1
公开(公告)日：2013-03-05
申请号：US11848005
申请日：2007-08-30
申请人： Bum-Soo Kim , Gui-Yong Lee , Jong-Min Kim , Ji-hyun In , Jesung Kim , Sam-hyuk Noh , Sang-Iyul Min , Dong-hee Lee , Jae-yong Jeong , Yoo-kun Cho , Jong-moo Choi
发明人： Bum-Soo Kim , Gui-Yong Lee , Jong-Min Kim , Ji-hyun In , Jesung Kim , Sam-hyuk Noh , Sang-Iyul Min , Dong-hee Lee , Jae-yong Jeong , Yoo-kun Cho , Jong-moo Choi
IPC分类号： G06F12/00
CPC分类号： G06F12/0246 , G06F3/0679 , G06F13/4239 , G06F2212/2022 , G06F2212/7203
摘要： A flash memory management method is provided. According to the method, when a request to write the predetermined data to a page to which data has been written is made, the predetermined data is written to a log block corresponding to a data block containing the page. When a request to write the predetermined data to the page again is received, the predetermined data is written to an empty free page in the log block. Even if the same page is requested to be continuously written to, the management method allows this to be processed in one log block, thereby improving the effectiveness in the use of flash memory resources.

8. 发明授权

US07782680B2 Flash memory device having a verify data buffer capable of being employed as a program data buffer, and a method thereof 有权
标题翻译：具有能够被用作程序数据缓冲器的验证数据缓冲器的闪速存储器件及其方法
公开(公告)号：US07782680B2
公开(公告)日：2010-08-24
申请号：US12003589
申请日：2007-12-28
申请人： Kee-ho Jung , Jae-yong Jeong , Chi-weon Yoon
发明人： Kee-ho Jung , Jae-yong Jeong , Chi-weon Yoon
IPC分类号： G11C11/34
CPC分类号： G11C16/3454
摘要： A flash memory device includes a program data buffer configured to buffer program data to be programmed in a memory cell array, and a verify data buffer configured to compare verify data to confirm whether the program data is accurately programmed in the memory cell array, wherein at least a portion of the verify data buffer is selectively enabled as a verify data buffer or a program data buffer responsive to a buffer control signal.
摘要翻译：闪速存储器件包括被配置为缓冲要在存储器单元阵列中编程的程序数据的程序数据缓冲器，以及配置为比较验证数据以确认程序数据是否被精确地编程在存储单元阵列中的校验数据缓冲器，其中，验证数据缓冲器的至少一部分被有选择地启用为响应于缓冲器控制信号的验证数据缓冲器或程序数据缓冲器。

9. 发明申请

US20100118613A1 Method of erasing data in flash memory device 失效
标题翻译：擦除闪存设备中数据的方法
公开(公告)号：US20100118613A1
公开(公告)日：2010-05-13
申请号：US12458502
申请日：2009-07-14
申请人： Jin-young Chun , Jae-yong Jeong
发明人： Jin-young Chun , Jae-yong Jeong
IPC分类号： G11C16/14 , G11C16/04 , G11C29/00 , G11C16/06
CPC分类号： G11C16/16 , G11C16/344 , G11C16/3445
摘要： A method of erasing data in a flash memory device, including erasing data in at least one flash memory cell using a first erase voltage; detecting whether the at least one flash memory cell has a threshold voltage less than a first voltage; programming the at least one flash memory cell by varying the threshold voltage of the at least one flash memory cell using a second voltage that is greater than the first voltage if the detecting step detects the threshold voltage is less than the first voltage; maintaining the threshold voltage of the at least one flash memory cell if the detecting step detects the threshold voltage is greater than the first voltage; and verifying the at least one flash memory cell using a first verification voltage.
摘要翻译：一种擦除闪速存储器件中的数据的方法，包括使用第一擦除电压擦除至少一个闪存单元中的数据; 检测所述至少一个闪存单元是否具有小于第一电压的阈值电压; 如果所述检测步骤检测到所述阈值电压小于所述第一电压，则使用大于所述第一电压的第二电压改变所述至少一个闪存单元的阈值电压来对所述至少一个闪存单元进行编程; 如果所述检测步骤检测到所述阈值电压大于所述第一电压，则保持所述至少一个闪存单元的阈值电压; 以及使用第一验证电压验证所述至少一个闪存单元。

10. 发明授权

US07668015B2 Nonvolatile memory devices capable of reducing data programming time and methods of driving the same 失效
标题翻译：能够减少数据编程时间的非易失性存储器件及其驱动方法
公开(公告)号：US07668015B2
公开(公告)日：2010-02-23
申请号：US12005366
申请日：2007-12-27
申请人： Jae-phil Kong , Heung-soo Lim , Jae-yong Jeong , Chi-weon Yoon
发明人： Jae-phil Kong , Heung-soo Lim , Jae-yong Jeong , Chi-weon Yoon
IPC分类号： G11C16/04
CPC分类号： G11C11/5628
摘要： In a method of driving a nonvolatile memory device a first data state is determined from among the plurality of data states. The number of simultaneously programmed bits is set according to the determined first data state and a scanning operation is performed on data input from an external device to search data bits to be programmed. The searched data bits are programmed in response to the number of simultaneously programmed bits. The number of simultaneously programmed bits corresponding to the first data state is different from a number of simultaneously programmed bits corresponding to at least a second of the plurality of data states.
摘要翻译：在驱动非易失性存储器件的方法中，从多个数据状态中确定第一数据状态。根据确定的第一数据状态来设置同时编程的位的数量，并且对从外部设备输入的数据执行扫描操作以搜索要编程的数据位。搜索到的数据位被编程为响应于同时编程的位的数量。对应于第一数据状态的同时被编程的位的数量与对应于多个数据状态中的至少一个数据状态的同时被编程的位的数量不同。

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