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1. 发明申请

US20050154188A1 Cytoplasmic tranduction peptides and uses thereof 有权
标题翻译：细胞质转导肽及其用途
公开(公告)号：US20050154188A1
公开(公告)日：2005-07-14
申请号：US10509620
申请日：2003-03-28
申请人： Dae-You Kim , Hae-Keun Oh , Chang-Hyun Kim , Jung-Hwan Kim , Choon-Ju Jeon , Yong-Soo Bae , In-Soo Choi
发明人： Dae-You Kim , Hae-Keun Oh , Chang-Hyun Kim , Jung-Hwan Kim , Choon-Ju Jeon , Yong-Soo Bae , In-Soo Choi
IPC分类号： A61K38/00 , C07K7/06 , C07K14/705
摘要： The present invention relates to a cytoplasmic transduction peptide (CTP) showing transduction potential, as well as cytoplasmic remaining potential and various uses thereof. The CTP of this invention exhibits a transduction potential identical or higher than the conventional protein transduction, PTD, and a strong tendency to remain in the cytoplasm, so that it is very useful in inducing cytotoxic T lymphocytes (CTL) and a drug delivery system (DDS) targeting cytoplasm.
摘要翻译：本发明涉及显示转导电位的细胞质转导肽（CTP），以及细胞质剩余电位及其各种用途。本发明的CTP显示出与常规蛋白转导（PTD）相同或更高的转导电位，并且具有保留在细胞质中的强烈倾向，因此其在诱导细胞毒性T淋巴细胞（CTL）和药物递送系统 DDS）靶向细胞质。

2. 发明授权

US07101844B2 Cytoplasmic transduction peptides and uses thereof 有权
标题翻译：细胞质转导肽及其用途
公开(公告)号：US07101844B2
公开(公告)日：2006-09-05
申请号：US10509620
申请日：2003-03-28
申请人： Dae-You Kim , Hae-Keun Oh , Chang-Hyun Kim , Jung-Hwan Kim , Choon-Ju Jeon , Ki-Tae Kim , Yong-Soo Bae , In-Soo Choi
发明人： Dae-You Kim , Hae-Keun Oh , Chang-Hyun Kim , Jung-Hwan Kim , Choon-Ju Jeon , Ki-Tae Kim , Yong-Soo Bae , In-Soo Choi
IPC分类号： A01N37/18
摘要： The present invention relates to a cytoplasmic transduction peptide (CTP) showing transduction potential, as well as cytoplasmic remaining potential and various uses thereof. The CTP of this invention exhibits a transduction potential identical or higher than the conventional protein transduction, PTD, and a strong tendency to remain in the cytoplasm, so that it is very useful in inducing cytotoxic T lymphocytes (CTL) and a drug delivery system (DDS) targeting cytoplasm.
摘要翻译：本发明涉及显示转导电位的细胞质转导肽（CTP），以及细胞质剩余电位及其各种用途。本发明的CTP显示出与常规蛋白转导（PTD）相同或更高的转导电位，并且具有保留在细胞质中的强烈倾向，因此其在诱导细胞毒性T淋巴细胞（CTL）和药物递送系统 DDS）靶向细胞质。

3. 发明授权

US08890325B2 Heterojunction structures of different substrates joined and methods of fabricating the same 有权
标题翻译：不同基底的异质结结构与其制造方法相同
公开(公告)号：US08890325B2
公开(公告)日：2014-11-18
申请号：US13244544
申请日：2011-09-25
申请人： Un-Byoung Kang , Kwang-chul Choi , Jung-Hwan Kim , Tae Hong Min
发明人： Un-Byoung Kang , Kwang-chul Choi , Jung-Hwan Kim , Tae Hong Min
IPC分类号： H01L23/48 , H01L33/48 , H01L33/62 , H01L33/00
CPC分类号： H01L33/486 , H01L33/0079 , H01L33/62 , H01L2224/16 , H01L2933/0066
摘要： In one embodiment, a heterojunction structure includes a first substrate; a second substrate comprising an electrode pad, the second substrate joined to the first substrate by an adhesive layer interposed between the first and second substrates, the first substrate and the adhesive layer having a via hole penetrating therethrough to expose a region of the electrode pad; a connection electrode disposed in the via hole and contacting the electrode pad; and an insulation layer electrically insulating the connection electrode from the first substrate. One of the first and second substrates has a thermal expansion coefficient different than a thermal expansion coefficient of the other of the first and second substrates, and at least one of the adhesive layer or the insulation layer comprises an organic material.
摘要翻译：在一个实施例中，异质结结构包括第一衬底; 第二基板，其包括电极焊盘，所述第二基板通过插入在所述第一和第二基板之间的粘合剂层连接到所述第一基板，所述第一基板和所述粘合剂层具有贯穿其中的通孔，以暴露所述电极焊盘的区域; 连接电极，设置在所述通孔中并与所述电极焊盘接触; 以及将连接电极与第一基板电绝缘的绝缘层。第一和第二基板中的一个具有不同于第一和第二基板中的另一个的热膨胀系数的热膨胀系数，并且粘合剂层或绝缘层中的至少一个包括有机材料。

4. 发明授权

US08450856B2 Semiconductor device and method of forming the same 有权
公开(公告)号：US08450856B2
公开(公告)日：2013-05-28
申请号：US13240533
申请日：2011-09-22
申请人： Un-Byoung Kang , Kwang-chul Choi , Jung-Hwan Kim , Tae Hong Min , Hojin Lee , Minseung Yoon
发明人： Un-Byoung Kang , Kwang-chul Choi , Jung-Hwan Kim , Tae Hong Min , Hojin Lee , Minseung Yoon
IPC分类号： H01L23/48
CPC分类号： H01L21/4835 , H01L21/6836 , H01L21/76898 , H01L23/3114 , H01L23/3192 , H01L23/49827 , H01L24/06 , H01L24/45 , H01L24/48 , H01L25/0657 , H01L27/14618 , H01L2221/68327 , H01L2221/6834 , H01L2224/02166 , H01L2224/02313 , H01L2224/02372 , H01L2224/02375 , H01L2224/02381 , H01L2224/024 , H01L2224/03462 , H01L2224/03466 , H01L2224/03602 , H01L2224/0401 , H01L2224/04042 , H01L2224/05008 , H01L2224/05022 , H01L2224/05026 , H01L2224/05147 , H01L2224/05548 , H01L2224/05567 , H01L2224/05571 , H01L2224/05647 , H01L2224/06131 , H01L2224/06135 , H01L2224/06138 , H01L2224/06181 , H01L2224/13007 , H01L2224/13022 , H01L2224/13024 , H01L2224/13025 , H01L2224/16147 , H01L2224/16225 , H01L2224/16227 , H01L2224/29011 , H01L2224/32225 , H01L2224/45139 , H01L2224/48105 , H01L2224/48227 , H01L2224/48228 , H01L2224/73253 , H01L2224/73265 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2225/06565 , H01L2924/00014 , H01L2924/01006 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/0105 , H01L2924/01073 , H01L2924/014 , H01L2924/12042 , H01L2924/12044 , H01L2924/14 , H01L2924/15183 , H01L2924/15311 , H01L2924/181 , H01L2924/00 , H01L2224/05552 , H01L2224/45099 , H01L2224/05599 , H01L2924/00012
摘要： In a semiconductor device, an organic insulation pattern is disposed between first and second rerouting patterns. The organic insulation pattern may absorb the physical stress that occurs when the first and second rerouting patterns expand under heat. Since the organic insulation pattern is disposed between the first and second rerouting patterns, insulating properties can be increased relative to a semiconductor device in which a semiconductor pattern is disposed between rerouting patterns. Also, since a seed layer pattern is disposed between the first and second rerouting patterns and the organic insulation pattern and between the substrate and the organic insulation pattern, the adhesive strength of the first and second rerouting patterns is enhanced. This also reduces any issues with delamination. Also, the seed layer pattern prevents the metal that forms the rerouting pattern from being diffused to the organic insulation pattern. Therefore, a semiconductor device with enhanced reliability may be implemented.

5. 发明申请

US20120153498A1 Semiconductor Device and Method of Forming the Same 有权
标题翻译：半导体器件及其形成方法
公开(公告)号：US20120153498A1
公开(公告)日：2012-06-21
申请号：US13240533
申请日：2011-09-22
申请人： Un-Byoung Kang , Kwang-chul Choi , Jung-Hwan Kim , Tae Hong Min , Hojin Lee , Minseung Yoon
发明人： Un-Byoung Kang , Kwang-chul Choi , Jung-Hwan Kim , Tae Hong Min , Hojin Lee , Minseung Yoon
IPC分类号： H01L23/48
CPC分类号： H01L21/4835 , H01L21/6836 , H01L21/76898 , H01L23/3114 , H01L23/3192 , H01L23/49827 , H01L24/06 , H01L24/45 , H01L24/48 , H01L25/0657 , H01L27/14618 , H01L2221/68327 , H01L2221/6834 , H01L2224/02166 , H01L2224/02313 , H01L2224/02372 , H01L2224/02375 , H01L2224/02381 , H01L2224/024 , H01L2224/03462 , H01L2224/03466 , H01L2224/03602 , H01L2224/0401 , H01L2224/04042 , H01L2224/05008 , H01L2224/05022 , H01L2224/05026 , H01L2224/05147 , H01L2224/05548 , H01L2224/05567 , H01L2224/05571 , H01L2224/05647 , H01L2224/06131 , H01L2224/06135 , H01L2224/06138 , H01L2224/06181 , H01L2224/13007 , H01L2224/13022 , H01L2224/13024 , H01L2224/13025 , H01L2224/16147 , H01L2224/16225 , H01L2224/16227 , H01L2224/29011 , H01L2224/32225 , H01L2224/45139 , H01L2224/48105 , H01L2224/48227 , H01L2224/48228 , H01L2224/73253 , H01L2224/73265 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2225/06565 , H01L2924/00014 , H01L2924/01006 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/0105 , H01L2924/01073 , H01L2924/014 , H01L2924/12042 , H01L2924/12044 , H01L2924/14 , H01L2924/15183 , H01L2924/15311 , H01L2924/181 , H01L2924/00 , H01L2224/05552 , H01L2224/45099 , H01L2224/05599 , H01L2924/00012
摘要： In a semiconductor device, an organic insulation pattern is disposed between first and second rerouting patterns. The organic insulation pattern may absorb the physical stress that occurs when the first and second rerouting patterns expand under heat. Since the organic insulation pattern is disposed between the first and second rerouting patterns, insulating properties can be increased relative to a semiconductor device in which a semiconductor pattern is disposed between rerouting patterns. Also, since a seed layer pattern is disposed between the first and second rerouting patterns and the organic insulation pattern and between the substrate and the organic insulation pattern, the adhesive strength of the first and second rerouting patterns is enhanced. This also reduces any issues with delamination. Also, the seed layer pattern prevents the metal that forms the rerouting pattern from being diffused to the organic insulation pattern. Therefore, a semiconductor device with enhanced reliability may be implemented.
摘要翻译：在半导体器件中，有机绝缘图案设置在第一和第二重新布线图案之间。有机绝缘图案可以吸收当第一和第二重新布线图案在加热下膨胀时发生的物理应力。由于有机绝缘图案设置在第一和第二重新布线图案之间，所以可以相对于其中在重新布线图案之间设置半导体图案的半导体器件来增加绝缘性能。此外，由于在第一和第二重新布线图案和有机绝缘图案之间以及基板和有机绝缘图案之间设置种子层图案，所以第一和第二布线图案的粘合强度提高。这也减少了分层问题。此外，种子层图案防止形成重新布线图案的金属扩散到有机绝缘图案。因此，可以实现具有增强的可靠性的半导体器件。

6. 发明申请

US20120018885A1 SEMICONDUCTOR APPARATUS HAVING THROUGH VIAS 有权
标题翻译：具有VIAS的半导体设备
公开(公告)号：US20120018885A1
公开(公告)日：2012-01-26
申请号：US12960843
申请日：2010-12-06
申请人： Go Eun Lee , Taeje Cho , Un-Byoung Kang , Seongmin Ryu , Jung-Hwan Kim , Tae Hong Min
发明人： Go Eun Lee , Taeje Cho , Un-Byoung Kang , Seongmin Ryu , Jung-Hwan Kim , Tae Hong Min
IPC分类号： H01L23/498
CPC分类号： H01L23/481 , H01L23/49816 , H01L23/49855 , H01L24/48 , H01L24/73 , H01L25/0657 , H01L2224/0401 , H01L2224/04042 , H01L2224/0557 , H01L2224/06181 , H01L2224/13025 , H01L2224/16145 , H01L2224/16146 , H01L2224/16225 , H01L2224/16227 , H01L2224/16235 , H01L2224/17181 , H01L2224/32145 , H01L2224/48145 , H01L2224/48227 , H01L2224/73207 , H01L2224/73253 , H01L2224/73257 , H01L2224/73265 , H01L2225/06541 , H01L2924/00014 , H01L2924/01322 , H01L2924/10253 , H01L2924/14 , H01L2924/1431 , H01L2924/1434 , H01L2924/15311 , H01L2924/181 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A semiconductor apparatus includes a base substrate and a logic chip disposed on the base substrate. The logic chip includes a memory control circuit, a first through silicon via, and a second through silicon via. The memory control circuit is disposed on a first surface of a substrate of the logic chip, and a memory chip is disposed on a second surface of the substrate of the logic chip. The first through silicon via electrically connects the memory control circuit and the memory chip, the second through silicon via is electrically connected to the memory chip and is configured to transmit power for the memory chip, the second through silicon via is electrically insulated from the logic chip, and the first surface of the substrate of the logic chip faces the base substrate.
摘要翻译：半导体装置包括基底基板和布置在基底基板上的逻辑芯片。逻辑芯片包括存储器控制电路，第一通孔硅通孔和第二硅通孔。存储器控制电路设置在逻辑芯片的基板的第一表面上，并且存储芯片设置在逻辑芯片的基板的第二表面上。第一通孔硅通过电连接存储器控制电路和存储器芯片，第二通孔硅通孔电连接到存储器芯片，并被配置为向存储器芯片发送功率，第二通孔硅通孔与逻辑电绝缘芯片，并且逻辑芯片的基板的第一表面面向基底。

7. 发明申请

US20110262778A1 SECONDARY BATTERY PACK 有权
标题翻译：二次电池组
公开(公告)号：US20110262778A1
公开(公告)日：2011-10-27
申请号：US13122302
申请日：2009-10-13
申请人： Seogjin Yoon , Ki Eob Moon , Jung-Hwan Kim
发明人： Seogjin Yoon , Ki Eob Moon , Jung-Hwan Kim
IPC分类号： H01M10/42
CPC分类号： H01M2/0404 , H01M2/0473 , H01M2/1061 , H01M10/052 , H01M10/425 , H01M2200/103 , H01M2200/106
摘要： Disclosed herein is a secondary battery pack including a battery cell having an electrode assembly of a cathode/separator/anode structure mounted in a battery case together with an electrolyte in a sealed state, an insulative mounting member having openings, through which electrode terminals of the battery cell are exposed to the outside, the insulative mounting member being configured to have a structure in which a safety element is mounted to the top of the insulative mounting member, the insulative mounting member being disposed in direct contact with the top of the battery cell, and an insulative cap coupled to the top of the battery cell so that the insulative cap surrounds the insulative mounting member in a state in which the safety element is mounted to the insulative mounting member, wherein the battery case is provided at the top thereof with a coupling groove, and the insulative cap is provided at the bottom thereof with a coupling protrusion formed in a shape corresponding to the coupling groove, the coupling of the insulative cap to the battery cell being achieved by the insertion of the coupling protrusion into the coupling groove.
摘要翻译：本文公开了一种二次电池组，其包括具有阴极/隔板/阳极结构的电极组件的电池组，阴极/隔板/阳极结构与密封状态的电解质一起安装在电池壳体中，具有开口的绝缘安装构件，电池单元暴露于外部，绝缘安装构件被构造成具有将安全元件安装到绝缘安装构件的顶部的结构，绝缘安装构件设置成与电池单元的顶部直接接触以及耦合到电池单元的顶部的绝缘帽，使得绝缘帽在安全元件安装到绝缘安装构件的状态下围绕绝缘安装构件，其中电池壳体在其顶部设置有耦合槽，并且绝缘帽在其底部设置有形成为相应形状的联接突起通过将耦合突起插入耦合槽来实现绝缘帽与电池单元的耦合。

8. 发明授权

US07928495B2 Semiconductor device and method of fabricating the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US07928495B2
公开(公告)日：2011-04-19
申请号：US12906652
申请日：2010-10-18
申请人： Jung-Hwan Kim , Hun-Hyeoung Leam , Tae-Hyun Kim , Seok-Woo Nam , Hyun Namkoong , Yong-Seok Kim , Tea-Kwang Yu
发明人： Jung-Hwan Kim , Hun-Hyeoung Leam , Tae-Hyun Kim , Seok-Woo Nam , Hyun Namkoong , Yong-Seok Kim , Tea-Kwang Yu
IPC分类号： H01L29/76
CPC分类号： H01L29/785 , H01L21/28282 , H01L21/308 , H01L21/76224 , H01L21/76232 , H01L21/823481 , H01L27/115 , H01L27/11521 , H01L27/11568 , H01L29/0649 , H01L29/0653 , H01L29/0657 , H01L29/1079 , H01L29/42352 , H01L29/66818 , H01L29/66833 , H01L29/7851 , H01L29/7854 , H01L2029/7858
摘要： A semiconductor device includes an isolation layer defining an active region formed in a semiconductor substrate. A first recessing process is performed on the isolation layer to expose edge portions of the active region. A first rounding process is performed to round the edge portions of the active region. A second recessing process is performed on the isolation layer. A second rounding process is performed to round the edge portions of the active region.
摘要翻译：半导体器件包括限定形成在半导体衬底中的有源区的隔离层。在隔离层上执行第一凹陷处理以暴露活性区域的边缘部分。执行第一舍入处理以围绕活动区域的边缘部分。在隔离层上进行第二凹陷处理。执行第二舍入处理以围绕活动区域的边缘部分。

9. 发明授权

US07161918B2 Mobile station service in mobile communication system 失效
标题翻译：移动通信系统中的移动台服务
公开(公告)号：US07161918B2
公开(公告)日：2007-01-09
申请号：US10029279
申请日：2001-12-28
申请人： Jung-Hwan Kim
发明人： Jung-Hwan Kim
IPC分类号： H04B7/216
CPC分类号： H04B7/2634
摘要： A mobile communication system and a mobile station service method in the mobile communication system is disclosed, and enables mobile terminals of a second generation (IS-95, IS-95B) and a third generation (IS-2000) to be operated using a CDMA Channel List and an Extended CDMA Channel List. The method preferably includes checking whether a frequency on service presently exists on a CDMA Channel List and an Extended CDMA Channel List when a service frequency of a base station is changed, copying the frequency allocated to the Extended CDMA Channel List to the CDMA Channel List if the frequency on service fails to exist on the CDMA Channel List, copying the frequency allocated to the CDMA Channel List to the Extended CDMA Channel List if the frequency on service fails to exist on the Extended CDMA Channel List, and transmitting the CDMA and Extended CDMA Channel Lists to which the frequency is copied to a terminal.
摘要翻译：公开了移动通信系统中的移动通信系统和移动台服务方法，并且使用CDMA技术来操作第二代移动终端（IS-95，IS-95B）和第三代（IS-2000）频道列表和扩展CDMA频道列表。该方法优选地包括：当基站的服务频率改变时，检查在CDMA信道列表和扩频CDMA信道列表上当前是否存在服务频率，如果分配给扩频CDMA信道列表的频率复制到CDMA信道列表中服务频率不能存在于CDMA频道列表上，如果服务频率不能存在于扩展CDMA频道列表上，则将分配给CDMA频道列表的频率复制到扩展CDMA频道列表，并且发送CDMA和扩展CDMA 通道列表将频率复制到终端。

10. 发明申请

US20050277248A1 Methods of forming void-free layers in openings of semiconductor substrates 有权
标题翻译：在半导体衬底的开口中形成无空隙层的方法
公开(公告)号：US20050277248A1
公开(公告)日：2005-12-15
申请号：US11107529
申请日：2005-04-15
申请人： Jung-Hwan Kim , Hun-Hyeoung Leam , Jai-Dong Lee , Young-Seok Kim , Young-Sub You , Ki-Su Na , Woong Lee
发明人： Jung-Hwan Kim , Hun-Hyeoung Leam , Jai-Dong Lee , Young-Seok Kim , Young-Sub You , Ki-Su Na , Woong Lee
IPC分类号： H01L21/8242 , H01L21/8247 , H01L27/115
CPC分类号： H01L27/11521 , H01L27/115
摘要： In a method of manufacturing a floating gate of a non-volatile semiconductor memory, a pattern is formed on a substrate to have an opening that exposes a portion of the substrate. A first preliminary polysilicon layer is formed on the pattern and the exposed portion of the substrate to substantially fill the opening. A first polysilicon layer is formed by partially etching the first preliminary polysilicon layer until a first void formed in the first preliminary polysilicon layer is exposed. A second polysilicon layer is formed on the first polysilicon layer.
摘要翻译：在制造非易失性半导体存储器的浮置栅极的方法中，在衬底上形成图案以具有露出衬底的一部分的开口。在图案和基板的暴露部分上形成第一初步多晶硅层以基本上填充开口。通过部分地蚀刻第一初步多晶硅层直到形成在第一初步多晶硅层中的第一空穴露出来形成第一多晶硅层。在第一多晶硅层上形成第二多晶硅层。

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