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1. 发明授权

US06506676B2 Method of manufacturing semiconductor devices with titanium aluminum nitride work function 有权
标题翻译：制造具有钛氮化铝功能的半导体器件的方法
公开(公告)号：US06506676B2
公开(公告)日：2003-01-14
申请号：US10033509
申请日：2001-12-27
申请人： Dae Gyu Park , Tae Ho Cha , Se Aug Jang , Heung Jae Cho , Tae Kyun Kim , Kwan Yong Lim , In Seok Yeo , Jin Won Park
发明人： Dae Gyu Park , Tae Ho Cha , Se Aug Jang , Heung Jae Cho , Tae Kyun Kim , Kwan Yong Lim , In Seok Yeo , Jin Won Park
IPC分类号： H01L2144
CPC分类号： H01L21/28194 , C23C14/048 , C23C16/34 , H01L21/28556 , H01L21/823842 , H01L29/4966 , H01L29/513 , H01L29/518
摘要： A method of manufacturing semiconductor devices forms a surface channel CMOSFET in the process of manufacturing a metal gate. The method forms a (TixAly)1-zNz film (where z ranges from about 0.0 to about 0.2) having a work function value ranging from about 4.2 to about 4.3 eV on a gate insulating film in a nMOS region, a (TixAly)1-zNz film (where z ranges from about 0.3 to about 0.6) having a work function value ranging from about 4.8 to about 5.0 eV on the gate insulating film in a pMOS region, thus implementing a surface channel CMOS device both in the nMOS region and the pMOS region. Therefore, the threshold voltage is reduced.
摘要翻译：制造半导体器件的方法在制造金属栅极的过程中形成表面沟道CMOSFET。该方法在nMOS区域的栅极绝缘膜上形成具有约4.2至约4.3eV的功函数值的（TixAly）1-zNz膜（其中z范围为约0.0至约0.2），（TixAly）1 -zNz膜（其中z范围为约0.3至约0.6），在pMOS区域中的栅极绝缘膜上具有约4.8至约5.0eV的功函数值，从而在nMOS区域和 pMOS区域。因此，阈值电压降低。

2. 发明授权

US06828185B2 CMOS of semiconductor device and method for manufacturing the same 有权
标题翻译：半导体器件的CMOS及其制造方法
公开(公告)号：US06828185B2
公开(公告)日：2004-12-07
申请号：US10230345
申请日：2002-08-29
申请人： Kwan Yong Lim , Heung Jae Cho , Dae Gyu Park , In Seok Yeo
发明人： Kwan Yong Lim , Heung Jae Cho , Dae Gyu Park , In Seok Yeo
IPC分类号： H01L218238
CPC分类号： H01L21/823857
摘要： The present invention discloses the single gate CMOS with the surface channel manufactured according to the manufacturing method of the present invention is very advantageous for improving the characteristics, yield and reliability of the device, by performing decoupled plasma nitridation (DPN) process on the gate oxide film of the cell NMOS and the peripheral PMOS, respectively, thereby forming a silicon nitride on the surface of the gate oxide film. Further, the single gate CMOS with the surface channel can be formed more easily through the simplified process in overall, without requiring a separate transient ion implantation process, even when the gate electrode of the n+ polysilicon layer is used, by having the threshold voltage of the cell NMOS be approximately +0.9V, the threshold voltage of the peripheral PMOS be approximately −0.5V and above, and the threshold voltage of the peripheral NMOS be approximately +0.5V and below. In addition, since the cell NMOS already has +0.9V of threshold voltage, back bias does not have to be applied separately to achieve the +0.9V threshold voltage, and the device with low power consumption is formed successfully.
摘要翻译：本发明公开了根据本发明的制造方法制造的具有表面通道的单栅极CMOS通过在栅极氧化物上进行去耦等离子体氮化（DPN）工艺来改善器件的特性，产量和可靠性是非常有利的电池NMOS和外围PMOS的膜，从而在栅极氧化膜的表面上形成氮化硅。此外，即使当使用n +多晶硅层的栅电极时，也可以通过整体的简化处理更容易地形成具有表面通道的单栅极CMOS，而不需要单独的瞬态离子注入工艺，单元NMOS的阈值电压约为+ 0.9V，外围PMOS的阈值电压约为-0.5V及以上，并且外围NMOS的阈值电压约为+ 0.5V及以下。另外，由于单元NMOS已经具有阈值电压的+ 0.9V，所以不必单独施加反向偏置以实现+ 0.9V阈值电压，并且成功地形成具有低功耗的器件。

3. 发明授权

US07157359B2 Method of forming a metal gate in a semiconductor device using atomic layer deposition process 有权
标题翻译：使用原子层沉积工艺在半导体器件中形成金属栅极的方法
公开(公告)号：US07157359B2
公开(公告)日：2007-01-02
申请号：US10036156
申请日：2001-12-26
申请人： Dae Gyu Park , Heung Jae Cho , Kwan Yong Lim
发明人： Dae Gyu Park , Heung Jae Cho , Kwan Yong Lim
IPC分类号： H01L21/3205
CPC分类号： H01L29/4966 , H01L21/28088
摘要： A method for forming a metal gate capable of preventing degradation in a characteristic of a gate insulating film upon formation of the metal gate. The method of forming the metal gate comprises the steps of providing a silicon substrate having device isolation films of a trench shape for defining an active region; forming a gate insulating film on the surface of the silicon substrate by means of a thermal oxidization process; sequentially forming a barrier metal film and a metal film for the gate on the gate insulating film; and patterning the metal film for the gate, the barrier metal film and the gate insulating film, wherein deposition of the barrier metal film and the metal film for the gate is performed by means of an atomic layer deposition (ALD) process or remote plasma chemical vapor deposition (CVD) process.
摘要翻译：一种用于形成金属栅极的方法，其能够防止在形成金属栅极时栅极绝缘膜的特性劣化。形成金属栅极的方法包括以下步骤：提供具有用于限定有源区的沟槽形状的器件隔离膜的硅衬底; 通过热氧化工艺在硅衬底的表面上形成栅极绝缘膜; 在栅极绝缘膜上依次形成阻挡金属膜和栅极用金属膜; 并且对栅极金属膜，阻挡金属膜和栅极绝缘膜进行图案化，其中通过原子层沉积（ALD）工艺或远程等离子体化学技术进行用于栅极的阻挡金属膜和金属膜的沉积气相沉积（CVD）工艺。

4. 发明授权

US06768179B2 CMOS of semiconductor device and method for manufacturing the same 失效
公开(公告)号：US06768179B2
公开(公告)日：2004-07-27
申请号：US10663910
申请日：2003-09-17
申请人： Heung Jae Cho , Dae Gyu Park , Kwan Yong Lim
发明人： Heung Jae Cho , Dae Gyu Park , Kwan Yong Lim
IPC分类号： H01L2994
CPC分类号： H01L21/823842
摘要： CMOS device arrangements have a surface channel, and a method for manufacturing the same by forming a multi-layer that includes a first metal layer, a polysilicon layer and a second metal layer having a work function from 4.8 through 5.0 eV on a cell region NMOS and a gate electrode of a peripheral circuit region PMOS, and by forming a multi-layer that includes a polysilicon layer and a second metal layer on a gate electrode of a peripheral circuit region NMOS. Because of the multi-layered gate electrode, a separate transient ion implantation process is not necessary, which consequently simplified the CMOS manufacturing process, while maintaining the threshold voltage of each peripheral circuit region −0.5V and below, and the threshold voltage of the peripheral circuit region NMOS +0.5V and below. Meantime, since the cell NMOS has the threshold voltage of +1V thanks to the first metal layer, no separate back bias is necessary, thereby forming a device with low power consumption, which consequently improves characteristics, yield and reliability of the device.

5. 发明授权

US06642132B2 Cmos of semiconductor device and method for manufacturing the same 有权
标题翻译：半导体器件的Cmos及其制造方法
公开(公告)号：US06642132B2
公开(公告)日：2003-11-04
申请号：US10253779
申请日：2002-09-25
申请人： Heung Jae Cho , Dae Gyu Park , Kwan Yong Lim
发明人： Heung Jae Cho , Dae Gyu Park , Kwan Yong Lim
IPC分类号： H01L213205
CPC分类号： H01L21/823842
摘要： CMOS device arrangements have a surface channel, and a method for manufacturing the same by forming a multi-layer that includes a first metal layer, a polysilicon layer and a second metal layer having a work function from 4.8 through 5.0 eV on a cell region NMOS and a gate electrode of a peripheral circuit region PMOS, and by forming a multi-layer that includes a polysilicon layer and a second metal layer on a gate electrode of a peripheral circuit region NMOS. Because of the multi-layered gate electrode, a separate transient ion implantation process is not necessary, which consequently simplified the CMOS manufacturing process, while maintaining the threshold voltage of each peripheral circuit region −0.5V and below, and the threshold voltage of the peripheral circuit region NMOS +0.5V and below. Meantime, since the cell NMOS has the threshold voltage of +1V thanks to the first metal layer, no separate back bias is necessary, thereby forming a device with low power consumption, which consequently improves characteristics, yield and reliability of the device.
摘要翻译： CMOS器件布置具有表面沟道，以及通过在单元区域NMOS上形成具有4.8至5.0eV的功函数的第一金属层，多晶硅层和第二金属层的多层形成其制造方法以及外围电路区域PMOS的栅电极，并且通过在外围电路区域NMOS的栅电极上形成包括多晶硅层和第二金属层的多层。由于多层栅电极，不需要单独的瞬态离子注入工艺，从而简化了CMOS制造工艺，同时保持了每个外围电路区域的阈值电压为-0.5V及以下，外围电路的阈值电压电路区域NMOS + 0.5V及以下。同时，由于单元NMOS由于第一金属层而具有+ 1V的阈值电压，因此不需要单独的背偏置，从而形成具有低功耗的器件，从而提高器件的特性，产量和可靠性。

6. 发明授权

US06448166B2 Method for forming a gate for semiconductor devices 失效
标题翻译：半导体器件栅极形成方法
公开(公告)号：US06448166B2
公开(公告)日：2002-09-10
申请号：US09895268
申请日：2001-07-02
申请人： Heung Jae Cho , Dae Gyu Park , Kwan Yong Lim
发明人： Heung Jae Cho , Dae Gyu Park , Kwan Yong Lim
IPC分类号： H01L213205
CPC分类号： H01L21/02356 , H01L21/0214 , H01L21/02164 , H01L21/02183 , H01L21/02255 , H01L21/02271 , H01L21/02337 , H01L21/02348 , H01L21/28185 , H01L21/28194 , H01L21/28202 , H01L21/3143 , H01L21/3185 , H01L29/513 , H01L29/518
摘要： The present invention discloses a method for forming a gate for semiconductor devices by depositing a TaOxNy film as a gate oxide film. The method includes the steps of providing a semiconductor substrate where a device isolation film has been formed, growing an SiO2 or SiON film on the semiconductor substrate, depositing an amorphous TaOxNy film on the SiO2 or SiON film, performing a low temperature annealing process to improve quality of the amorphous TaOxNy film, performing a high temperature annealing process ex-situ to remove organic substances and nitrogen in the amorphous TaOxNy film, and crystallize the amorphous TaOxNy film, and depositing a metal barrier film on the crystallized TaOxNy film, and depositing a polysilicon film or metal film for a gate electrode on the metal barrier film.
摘要翻译：本发明公开了一种通过沉积TaOxNy膜作为栅氧化膜形成半导体器件的栅极的方法。该方法包括以下步骤：提供半导体衬底，其中已经形成器件隔离膜，在半导体衬底上生长SiO 2或SiON膜，在SiO 2或SiON膜上沉积无定形TaO x N y膜，进行低温退火工艺以改善无定形TaOxNy膜的质量，非晶态TaO x N y膜中的有机物质和氮气的去除，进行高温退火处理，使无定形TaO x N y膜结晶化，在结晶化的TaO x N y膜上沉积金属阻挡膜，多晶硅膜或用于金属阻挡膜上的栅电极的金属膜。

7. 发明授权

US06514826B1 Method of forming a gate electrode in a semiconductor device 有权
标题翻译：在半导体器件中形成栅电极的方法
公开(公告)号：US06514826B1
公开(公告)日：2003-02-04
申请号：US09721636
申请日：2000-11-27
申请人： Dae Gyu Park , Tae Ho Cha
发明人： Dae Gyu Park , Tae Ho Cha
IPC分类号： H01L21336
CPC分类号： H01L21/28185 , C23C14/08 , H01L21/28194 , H01L21/31604 , H01L21/31683 , H01L29/517
摘要： There is disclosed a method of forming a gate electrode in a semiconductor device. The present invention forms a gate insulating film using (TiO2)x(Al2O3)x-1 in which a titanium oxide film (TiO2) having a high dielectric constant and an aluminum oxide film having leakage and interfacial property are mixed. Therefore, the present invention could not only improve the leakage current characteristic of a semiconductor device but also early develop a high-speed device having a high density in the future.
摘要翻译：公开了一种在半导体器件中形成栅电极的方法。本发明使用（TiO 2）x（Al 2 O 3）x-1形成具有高介电常数的氧化钛膜（TiO 2）和具有渗漏和界面特性的氧化铝膜的栅绝缘膜。因此，本发明不仅可以改善半导体器件的漏电流特性，而且可以早日开发高密度的高速器件。

8. 发明授权

US06391727B1 Method of manufacturing a semiconductor device utilizing a(Al2O3)X-(TiO2)1-X gate dielectric film 失效
标题翻译：制造使用（Al 2 O 3）X-（TiO 2）1-X栅极电介质膜的半导体器件的方法
公开(公告)号：US06391727B1
公开(公告)日：2002-05-21
申请号：US09722351
申请日：2000-11-28
申请人： Dae Gyu Park
发明人： Dae Gyu Park
IPC分类号： H01L214763
CPC分类号： C23C14/0641 , C23C14/5853 , H01L21/28185 , H01L21/28202 , H01L21/28211 , H01L21/3144 , H01L21/3145 , H01L21/318 , H01L27/10873 , H01L29/517 , H01L29/518
摘要： There is disclosed a method of manufacturing a semiconductor device utilizing a gate dielectric film. The present invention can obtain a (Al2O3)X—(TiO2)1−X gate dielectric film where its the dielectric constant is higher than that of Al2O3 and its leakage current characteristic is improved compared to TiO2, by depositing a Ti1−XAlXN film on a semiconductor substrate and then forming the (Al2O3)X—(TiO2)1−X gate dielectric film by oxidization process. Therefore, the present invention can implement a high-speed high-density logic device and an ultra high integration device of more than 1G DRAM class, which utilize a high dielectric material as the gate dielectric film.
摘要翻译：公开了利用栅极电介质膜制造半导体器件的方法。本发明可以获得其中介电常数高于Al 2 O 3的（Al 2 O 3）X-（TiO 2）1-X栅极电介质膜，并且通过将Ti1-XAlXN膜沉积在TiO 2上，其漏电流特性得到改善半导体衬底，然后通过氧化工艺形成（Al 2 O 3）X-（TiO 2）1-X栅极电介质膜。因此，本发明可以实现利用高介电材料作为栅极电介质膜的高于1G DRAM类的高速高密度逻辑器件和超高集成器件。

9. 发明授权

US5919281A 2-stage fluidized bed furnace for pre-reducing fine iron ore and method for pre-reducing fine iron ore using the furnace 失效
标题翻译：用于预还原精炼铁矿石的2级流化床炉和使用该炉预还原精细铁矿石的方法
公开(公告)号：US5919281A
公开(公告)日：1999-07-06
申请号：US894670
申请日：1997-08-25
申请人： Dae Gyu Park , Suk In Park , Il Ock Lee
发明人： Dae Gyu Park , Suk In Park , Il Ock Lee
IPC分类号： C21B11/00 , C21B13/00 , C21B13/14 , F27B15/00
CPC分类号： C21B13/0033 , Y02P10/136 , Y02P10/216
摘要： The 2-stage fluidized bed furnace for pre-reducing a fine iron ore comprises a first stage fluidized bed furnace for receiving the fine iron ore from a storage hopper, discharging medium/small particle size iron ore to the upper part thereof, and reducing a coarse particle size iron ore while forming a bubbling fluidized bed; a second stage fluidized bed furnace for receiving the medium/small particle size iron ore discharged from the upper part of the first stage and reducing it while forming a turbulent fluidized bed; and a first hot cyclone for collecting the small particle size iron ore contained in the discharged gas from the second stage fluidized bed furnace, the first stage furnace being formed in an upper-narrowed, lower-expanded shape and comprising a narrow, upper portion, a transitional, slanted portion and a wide, lower portion, the second stage furnace being in an upper-expanded, lower-narrowed shape and comprising a wide, upper portion, a transitional, slanted portion and a narrow, lower portion.
摘要翻译： PCT No.PCT / KR96 / 00249 Sec。 371日期1997年8月25日第 102（e）日期1997年8月25日PCT 1996年12月26日PCT公布。公开号WO97 / 23655 日期1997年7月3日用于预还原精细铁矿石的2级流化床炉包括用于从储料斗接收细铁矿石的第一级流化床炉，将中等/小粒径铁矿石排放到上部并且在形成鼓泡流化床的同时还原粗颗粒铁矿石; 第二级流化床炉，用于接收从第一阶段上部排出的中/小粒度铁矿石，并在形成湍流流化床的同时还原; 以及第一热旋风分离器，用于收集来自第二级流化床炉的排放气体中所含的小粒度铁矿石，第一级炉形成为上部变窄的较低膨胀形状，并且包括窄的上部，过渡的倾斜部分和宽的下部，第二级炉处于上部膨胀的下部变窄的形状，并且包括宽的上部，过渡的倾斜部分和较窄的下部。

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