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    • 9. 发明授权
    • SOI MuGFETs having single gate electrode level
    • 具有单栅电极层的SOI MuGFET
    • US08581317B2
    • 2013-11-12
    • US12199041
    • 2008-08-27
    • Howard TigelaarCloves Rinn CleavelinAndrew MarshallWeize Xiong
    • Howard TigelaarCloves Rinn CleavelinAndrew MarshallWeize Xiong
    • H01L27/115
    • H01L27/1203H01L21/84H01L27/11519H01L27/11521H01L27/11558
    • A silicon on insulator (SOI) multi-gate field effect transistor electrically Programmable Read-Only Memory (MuFET EPROM) includes a substrate having a dielectric surface. A first semiconducting region is in or on the dielectric surface. A source region, a drain region and a channel region interposed between the source and drain are formed in first semiconducting region. A gate dielectric layer is on the channel region. At least a second semiconducting region in or on the dielectric surface is spaced apart from the first semiconducting region. A first electrode layer comprises a first electrode portion including a transistor gate electrode and a control gate electrode electrically isolated from one another. The transistor gate overlies the channel region to form a transistor. The control gate extends to overlay a portion of the second semiconducting region. The transistor gate and thus the transistor and the control gate are capacitively coupled to one another by at least one MOS coupling capacitor, with one plate of the MOS coupling capacitor ohmically coupled to or including the second semiconducting region.
    • 绝缘体上硅(SOI)多栅极场效应晶体管电可编程只读存储器(MuFET EPROM)包括具有电介质表面的衬底。 第一半导电区域位于电介质表面中或其上。 源极区域,漏极区域和介于源极和漏极之间的沟道区域形成在第一半导体区域中。 栅介质层位于沟道区上。 电介质表面中或电介质表面上的至少第二半导体区域与第一半导体区域间隔开。 第一电极层包括第一电极部分,其包括晶体管栅电极和彼此电隔离的控制栅电极。 晶体管栅极覆盖沟道区以形成晶体管。 控制门延伸以覆盖第二半导体区域的一部分。 晶体管栅极,因此晶体管和控制栅极通过至少一个MOS耦合电容器彼此电容耦合,MOS耦合电容的一个板欧姆耦合到或包括第二半导体区域。