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1. 发明申请

US20090253253A1 METHOD OF ADJUSTING FDSOI THRESHOLD VOLTAGE THROUGH OXIDE CHARGES GENERATION IN THE BURIED OXIDE 有权
标题翻译：通过氧化硅氧化物生成的氧化物电压调节方法
公开(公告)号：US20090253253A1
公开(公告)日：2009-10-08
申请号：US12062968
申请日：2008-04-04
申请人： Weize XIONG , Cloves Rinn Cleavelin
发明人： Weize XIONG , Cloves Rinn Cleavelin
IPC分类号： H01L21/425
CPC分类号： H01L21/31155 , H01L21/26506 , H01L21/28211 , H01L21/823842 , H01L21/823878 , H01L21/84
摘要： Different performance MOSFET Fully Depleted devices can be achieved on a single chip by varying the Vt through ion implantation. The integration of multiple Vt can be achieved through the selection of a metal gate stack with suitable effective WF for one semiconductor device to be included on a chip. Then, an ion implantation, with a dopant such as F, can be selectively performed to achieve proper Vt for other semiconductor devices on the chip.
摘要翻译：通过改变Vt通过离子注入，可以在单个芯片上实现不同性能的MOSFET完全耗尽的器件。可以通过选择具有合适的有效WF的金属栅极堆叠来实现多个Vt的集成，一个半导体器件将被包括在芯片上。然后，可以选择性地执行具有诸如F的掺杂剂的离子注入，以为芯片上的其它半导体器件实现适当的Vt。

2. 发明申请

US20080308847A1 METHOD OF MAKING (100) NMOS AND (110) PMOS SIDEWALL SURFACE ON THE SAME FIN ORIENTATION FOR MULTIPLE GATE MOSFET WITH DSB SUBSTRATE 有权
标题翻译：在具有DSB基板的多个栅极MOSFET的同一熔接方向上制造（100）NMOS和（110）PMOS面板表面的方法
公开(公告)号：US20080308847A1
公开(公告)日：2008-12-18
申请号：US11764442
申请日：2007-06-18
申请人： Weize XIONG , Cloves Rinn Cleavelin , Angelo Pinto , Rick L. Wise
发明人： Weize XIONG , Cloves Rinn Cleavelin , Angelo Pinto , Rick L. Wise
IPC分类号： H01L27/11 , H01L21/8244
CPC分类号： H01L27/0886 , G11C11/412 , H01L21/823807 , H01L21/823821 , H01L27/0207 , H01L27/092 , H01L27/11 , H01L27/1104 , H01L27/1116 , H01L29/045 , Y10S257/90 , Y10S438/973 , Y10S438/982
摘要： A method of forming an integrated circuit device that includes a plurality of MuGFETs is disclosed. A PMOS fin of a MuGFET is formed on a substrate. The PMOS fin includes a channel of a first surface of a first crystal orientation. A NMOS fin of another MuGFET is formed on the substrate. The NMOS fin includes a channel on the substrate at one of 0° and 90° to the PMOS fin and includes a second surface of a second crystal orientation.
摘要翻译：公开了一种形成包括多个MuGFET的集成电路器件的方法。在基板上形成MuGFET的PMOS鳍。 PMOS鳍包括第一晶体取向的第一表面的沟道。在基板上形成另一个MuGFET的NMOS鳍。所述NMOS鳍片包括在所述衬底上与所述PMOS鳍片0°和90°之一处的通道，并且包括第二晶体取向的第二表面。

3. 发明申请

US20120045874A1 CMOS INTEGRATION METHOD FOR OPTIMAL IO TRANSISTOR VT 有权
标题翻译：用于最佳IO晶体管VT的CMOS集成方法
公开(公告)号：US20120045874A1
公开(公告)日：2012-02-23
申请号：US12857954
申请日：2010-08-17
申请人： Weize XIONG , Greg Charles Baldwin
发明人： Weize XIONG , Greg Charles Baldwin
IPC分类号： H01L21/8238
CPC分类号： H01L21/823892 , H01L21/823857
摘要： Various embodiments provide methods for fabricating dual supply voltage CMOS devices with a desired I/O transistor threshold voltage. The dual supply voltage CMOS devices can be fabricated in a semiconductor substrate that includes isolated regions for a logic NMOS transistor, a logic PMOS transistor, an I/O NMOS transistor, and an I/O PMOS transistor. Specifically, the fabrication can first set and/or adjust the threshold voltage (VT) of each of the I/O NMOS transistor and the I/O PMOS transistor to a desired level. Logic NMOS and logic PMOS transistors can then be formed with I/O NMOS and I/O PMOS transistors masked without affecting the set/adjusted VT of the I/O transistors.
摘要翻译：各种实施例提供用于制造具有期望的I / O晶体管阈值电压的双电源电压CMOS器件的方法。双电源电压CMOS器件可以制造在包括用于逻辑NMOS晶体管，逻辑PMOS晶体管，I / O NMOS晶体管和I / O PMOS晶体管的隔离区域的半导体衬底中。具体地，制造可以首先将I / O NMOS晶体管和I / O PMOS晶体管中的每一个的阈值电压（VT）设置和/或调整到期望的水平。逻辑NMOS和逻辑PMOS晶体管然后可以形成I / O NMOS和I / O PMOS晶体管，而不影响I / O晶体管的置位/调节VT。

4. 发明申请

US20110306170A1 Novel Method to Improve Performance by Enhancing Poly Gate Doping Concentration in an Embedded SiGe PMOS Process 审中-公开
标题翻译：通过在嵌入式SiGe PMOS工艺中增强多栅极掺杂浓度来提高性能的新方法
公开(公告)号：US20110306170A1
公开(公告)日：2011-12-15
申请号：US12549908
申请日：2009-08-28
申请人： Xin WANG , Zhiqiang WU , Weize XIONG , Song Zhao
发明人： Xin WANG , Zhiqiang WU , Weize XIONG , Song Zhao
IPC分类号： H01L21/336
CPC分类号： H01L29/7848 , H01L21/32155 , H01L21/823807 , H01L21/823814 , H01L21/823828 , H01L29/66636
摘要： A method for forming an embedded SiGe (eSiGe) PMOS transistor (102) with improved PMOS poly gate (108) doping concentration without increasing mask count and causing S/D overrun issue. After gate sidewall spacer (112) formation, the gate electrode (108) and source/drain regions (122) are implanted. After the implant, a recess (124) is formed and SiGe is deposited in the recess. By implanting and removing the implanted material (122) from the source/drain regions prior to SiGe (106) deposition, high PMOS gate doping can be achieved without causing a S/D overrun issue.
摘要翻译：一种用于在不增加掩模计数并引起S / D超限问题的情况下形成具有改进的PMOS多晶硅（108）掺杂浓度的嵌入式SiGe（eSiGe）PMOS晶体管（102）的方法。在栅极侧壁间隔物（112）形成之后，植入栅电极（108）和源/漏区（122）。在植入之后，形成凹部（124）并且SiGe沉积在凹部中。通过在SiGe（106）沉积之前从源极/漏极区注入和去除植入材料（122），可以实现高PMOS栅极掺杂而不引起S / D超限问题。

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