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    • 6. 发明授权
      US06838325B2 Method of forming a self-aligned, selectively etched, double recess high electron mobility transistor 有权
    • Method of forming a self-aligned, selectively etched, double recess high electron mobility transistor
    • 形成自对准，选择性蚀刻的双凹槽高电子迁移率晶体管的方法
    • US06838325B2
    • 2005-01-04
    • US10279358
    • 2002-10-24
    • Colin S. Whelan , Elsa K. Tong
    • Colin S. Whelan , Elsa K. Tong
    • H01L21/285 , H01L21/335 , H01L29/778 , H01L21/8252
    • H01L29/66462 , H01L21/28587 , H01L29/7785
    • A method is provided for forming a self-aligned, selectively etched, double recess high electron mobility transistor. The method includes providing a semiconductor structure having a III-V substrate; a first relatively wide band gap layer, a channel layer, a second relatively wide band gap Schottky layer, an etch stop layer; a III-V third wide band gap layer on etch stop layer; and an ohmic contact layer on the third relatively wide band gap layer. A mask is provided having a gate contact aperture to expose a gate region of the ohmic contact layer. A first wet chemical etch is brought into contact with portions of the ohmic contact layer exposed by the gate contact aperture. The first wet chemical selectively removes exposed portions of the ohmic contact layer and underlying portions of the third relatively wide band gap layer. The etch stop layer inhibits the first wet chemical etch from removing portions of such etch stop layer. Next, a second wet chemical etch is brought into contact with structure etched by the first wet chemical etch. The second wet chemical etch selectively removes exposed portions of the ohmic contact layer while leaving substantially un-etched exposed portions of the third relatively wide band gap layer, the Schottky contact layer and the etch stop layer. The etch stop layer is removed. A metal layer is deposited over the mask and through gate aperture therein onto, and in Schottky contact with, the Schottky contact layer.
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Espacenet 法律信息 同族专利 专利引用
    • 7. 发明授权
      US06835969B1 Split-channel high electron mobility transistor (HEMT) device 有权
    • Split-channel high electron mobility transistor (HEMT) device
    • 分流通道高电子迁移率晶体管（HEMT）器件
    • US06835969B1
    • 2004-12-28
    • US10606820
    • 2003-06-26
    • Philbert F. Marsh , Colin S. Whelan , William E. Hoke
    • Philbert F. Marsh , Colin S. Whelan , William E. Hoke
    • H01L29/778
    • H01L29/7784
    • A transistor structure having an gallium arsenide (GaAs) semiconductor substrate; a lattice match layer; an indium aluminum arsenide (InAlAs) barrier layer disposed over the lattice match layer; an InyGa1-yAs lower channel layer disposed on the barrier layer, where y is the mole fraction of In content in the lower channel layer; an InxGa1-xAs upper channel layer disposed on the lower channel layer, where x is the mole fraction of In content in the upper channel layer and where x is different from y; and an InAlAs Schottky layer on the InxGa1-xAs upper channel layer. The lower channel layer has a bandgap greater that the bandgap of the upper channel layer. The lower channel layer has a bulk electron mobility lower than the bulk electron mobility of the upper channel layer where.
    • 具有砷化镓（GaAs）半导体衬底的晶体管结构; 一个格子匹配层; 设置在晶格匹配层上的铟铝砷化物（InAlAs）阻挡层; 设置在阻挡层上的InyGa1-yAs下通道层，其中y是下通道层中In含量的摩尔分数; 设置在下沟道层上的In x Ga 1-x As上沟道层，其中x是上沟道层中In含量的摩尔分数，其中x不同于y; 以及In x Ga 1-x As上沟道层上的InAlAs肖特基层。 下通道层的带隙大于上通道层的带隙。 下沟道层的体电子迁移率低于上沟道层的体电子迁移率。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Espacenet 法律信息 同族专利 专利引用
    • 9. 发明授权
      US06924218B2 Sulfide encapsulation passivation technique 有权
    • Sulfide encapsulation passivation technique
    • 硫化物封装钝化技术
    • US06924218B2
    • 2005-08-02
    • US10321310
    • 2002-12-17
    • Philbert Francis Marsh , Colin S. Whelan
    • Philbert Francis Marsh , Colin S. Whelan
    • H01L21/00 , H01L21/02 , H01L21/28 , H01L21/314 , H01L21/3213 , H01L21/335 , H01L21/44
    • H01L21/32134 , H01L21/02057 , H01L21/02071 , H01L29/66462
    • A method for passivating a III-V material Schottky layer of a field effect transistor. The transistor has a gate electrode in Schottky contact with a gate electrode contact region of the Schottky layer. The gate electrode is adapted to control a flow of carriers between a source electrode of the transistor and a drain electrode of such tarnsistor. The transistor has exposed surface portions of the Schottky layer beween the source electrode and the drain electrode adjacent to the gate electrode contact region of the Schottky layer. The method includes removing organic contamination from the exposed surface portions of the Schottky layer using a oxygen plasma. The contamination removed surface portions of the Schottky layer are exposed to a solution of ammonium sulfide and NH4OH. After removal of the solution, the exposed regions are dried in a nitrogen enviroment. A layer of passivating material is deposited over the dried surface portions.
    • 一种用于钝化场效应晶体管的III-V材料肖特基层的方法。 晶体管具有与肖特基层的栅电极接触区域肖特基接触的栅电极。 栅电极适于控制晶体管的源电极和这种电阻器的漏电极之间的载流子流。 晶体管具有暴露在肖特基层的与源极电极和漏电极相邻的肖特基层的表面部分，与肖特基层的栅电极接触区域相邻。 该方法包括使用氧等离子体从肖特基层的暴露表面部分去除有机污染物。 将去除的肖特基层表面部分的污染物暴露于硫化铵和NH 4 OH的溶液中。 除去溶液后，暴露的区域在氮环境中干燥。 一层钝化材料沉积在干燥的表面部分上。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Espacenet 法律信息 同族专利 专利引用
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