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1. 发明授权

US07016041B2 Reticle overlay correction 有权
标题翻译：标线重叠校正
公开(公告)号：US07016041B2
公开(公告)日：2006-03-21
申请号：US10236226
申请日：2002-09-06
申请人： Colin D. Yates , James R. B. Elmer
发明人： Colin D. Yates , James R. B. Elmer
IPC分类号： G01B11/00
CPC分类号： G03F7/70633
摘要： A method for characterizing overlay errors between at least a first and a second mask layer for an integrated circuit. A first primary alignment structure is formed in a first position of the inter-layer region around the first mask layer, and a first secondary alignment structure is formed in a second position of the inter-layer region around the first mask layer. Similarly, a second primary alignment structure is formed in a first position of an inter-layer region around the second mask layer, and a second secondary alignment structure is formed in a second position of the inter-layer region around the second mask layer. The first mask layer and the second mask layer are exposed onto a photoresist coated substrate with a first exposure and a second exposure, where the first position of the first primary alignment structure during the first exposure generally aligns with the second position of the second secondary alignment structure, and the second position of the first secondary alignment structure during the second exposure generally aligns with the first position of the second primary alignment structure. The photoresist on the substrate is developed, and offsets between the first primary alignment structure and the second secondary alignment structure are measured, and offsets between the second primary alignment structure and the first secondary alignment structure are also measured, to determine the overlay errors.
摘要翻译：一种用于表征用于集成电路的至少第一和第二掩模层之间的覆盖误差的方法。第一主对准结构形成在第一掩模层周围的层间区域的第一位置，第一次取向结构形成在第一掩模层周围的层间区域的第二位置。类似地，第二主对准结构形成在第二掩模层周围的层间区域的第一位置，并且第二次取向结构形成在第二掩模层周围的层间区域的第二位置。第一掩模层和第二掩模层在第一曝光和第二曝光下暴露在光致抗蚀剂涂覆的基板上，其中在第一曝光期间第一主对准结构的第一位置通常与第二次对准的第二位置对齐并且在第二曝光期间第一次对准结构的第二位置通常与第二主对准结构的第一位置对准。显影衬底上的光致抗蚀剂，并且测量第一主对准结构和第二次对准结构之间的偏移，并且还测量第二主对准结构和第一次对准结构之间的偏移，以确定重叠误差。

2. 发明授权

US07115425B2 Integrated circuit process monitoring and metrology system 有权
标题翻译：集成电路过程监控与计量系统
公开(公告)号：US07115425B2
公开(公告)日：2006-10-03
申请号：US11072127
申请日：2005-03-04
申请人： Peter A. Burke , Eric J. Kirchner , James R. B. Elmer
发明人： Peter A. Burke , Eric J. Kirchner , James R. B. Elmer
IPC分类号： H01L21/66
CPC分类号： H01L22/34 , H01L21/31053
摘要： A method for monitoring polishing process parameters for an integrated circuit structure on a substrate. A first metrology site is constructed on the substrate. The first metrology site represents a design extreme of a high density integrated circuit structure. The first metrology site is formed by placing a relatively small horizontal surface area trench within a relatively large surface area field of a polish stop material. A second metrology site is also constructed on the substrate. The second metrology site represents a design extreme of a low density integrated circuit structure. The second metrology site is formed by placing a relatively large horizontal surface area trench within a relatively small surface area field of a polish stop material. The substrate is covered with a layer of an insulating material, thereby at least filling the trenches. A target thickness of the insulating material necessary to leave the trenches substantially filled to a top surface of the field of polish stop material is calculated. The substrate is polished until a first thickness of the insulating material in the trench of the first metrology site is no more than the target thickness. A second thickness of the insulating material in the trench of the second metrology site is measured, and values based on the first thickness and the second thickness are monitored as the polishing process parameters for the integrated circuit structure.
摘要翻译：一种用于监测基板上的集成电路结构的抛光工艺参数的方法。第一个计量站点被构建在基板上。第一个测量站点代表了高密度集成电路结构的设计极限。第一计量站点是通过在抛光停止材料的相对大的表面区域内放置相对较小的水平表面区域沟槽而形成的。第二个计量站点也在基板上构建。第二个测量站点是低密度集成电路结构的设计极限。第二计量站点通过在抛光停止材料的相对小的表面区域内放置相对较大的水平表面区域沟槽而形成。衬底被绝缘材料层覆盖，从而至少填充沟槽。计算出将沟槽基本上填充到抛光停止材料领域的顶表面所需的绝缘材料的目标厚度。抛光衬底直到第一测量点的沟槽中的绝缘材料的第一厚度不超过目标厚度。测量第二测量位置的沟槽中的绝缘材料的第二厚度，并且监测基于第一厚度和第二厚度的值作为用于集成电路结构的抛光工艺参数。

3. 发明授权

US06472316B1 Photolithography overlay control 有权
标题翻译：光刻覆盖控制
公开(公告)号：US06472316B1
公开(公告)日：2002-10-29
申请号：US09971329
申请日：2001-10-04
申请人： James R. B. Elmer , Eric J. Kirchner
发明人： James R. B. Elmer , Eric J. Kirchner
IPC分类号： H01L214763
CPC分类号： H01L23/544 , H01L21/76838 , H01L2223/54453 , H01L2924/0002 , H01L2924/00
摘要： A method for forming an alignment feature on a substrate. The alignment feature is of the type concurrently formed with an electrically conductive layer overlying an electrically nonconductive layer having vias. The vias are filled with an electrically conductive material, and the alignment feature has a smaller aspect ratio than the vias. The alignment feature is not filled with the electrically conductive material when a first amount of the electrically conductive material, sufficient to just fill the vias, is deposited on the substrate. The first amount of the electrically conductive material within the alignment feature is not sufficient to prevent the alignment feature in the electrically conductive layer from distorting, and thereby reducing the effectiveness of the alignment feature. The improvement is in depositing an additional amount of the electrically conductive material on the substrate. The additional amount is more than the first amount that is just sufficient to fill the vias, and fills the alignment feature to a level sufficient to prevent the alignment feature in the electrically conductive layer from distorting and reducing the effectiveness of the alignment feature.
摘要翻译：一种在衬底上形成取向特征的方法。对准特征是同时形成有覆盖在具有通孔的非导电层上的导电层的类型。通孔填充有导电材料，并且对准特征具有比通孔更小的纵横比。当第一量的导电材料（足以仅填充通孔）沉积在基底上时，对准特征未填充导电材料。对准特征中的第一量的导电材料不足以防止导电层中的对准特征变形，从而降低对准特征的有效性。改进在于在衬底上沉积额外量的导电材料。附加量大于刚好足以填充通孔的第一量，并且将对准特征填充到足以防止导电层中的对准特征变形并降低对准特征的有效性的水平。

4. 发明授权

US06818516B1 Selective high k dielectrics removal 失效
标题翻译：选择性高k电介质去除
公开(公告)号：US06818516B1
公开(公告)日：2004-11-16
申请号：US10629496
申请日：2003-07-29
申请人： Wai Lo , Hong Lin , Shiqun Gu , James R. B. Elmer
发明人： Wai Lo , Hong Lin , Shiqun Gu , James R. B. Elmer
IPC分类号： H01L21336
CPC分类号： H01L29/6659 , H01L21/31111
摘要： A method of forming a gate structure in an integrated circuit on a substrate. A high k layer is formed on the substrate, and a gate electrode layer is formed on the high k layer. The gate electrode layer is the patterned. LDD regions are formed using an ion implantation process, thereby creating damaged portions of the high k layer. A first portion of the damaged portions of the high k layer are removed, thereby defining a gate structure, and leaving remaining portions of the damaged portions of the high k layer. Sidewall spacers are formed adjacent the gate structure. Source/drain regions are formed using an ion implantation process, thereby further damaging the remaining portions of the damaged portions of the high k layer. The remaining portions of the damaged portions of the high k layer are then removed.
摘要翻译：在基板上的集成电路中形成栅极结构的方法。在基板上形成高k层，在高k层上形成栅电极层。栅极电极层是图案化的。使用离子注入工艺形成LDD区域，从而产生高k层的损坏部分。去除高k层的损坏部分的第一部分，从而限定栅极结构，并留下高k层的损坏部分的剩余部分。侧壁间隔件形成在栅极结构附近。使用离子注入工艺形成源极/漏极区，从而进一步损坏高k层的损伤部分的剩余部分。然后去除高k层的损坏部分的剩余部分。

5. 发明授权

US07095483B2 Process independent alignment marks 有权
标题翻译：过程独立对齐标记
公开(公告)号：US07095483B2
公开(公告)日：2006-08-22
申请号：US11000772
申请日：2004-12-01
申请人： David W. Daniel , James R. B. Elmer
发明人： David W. Daniel , James R. B. Elmer
IPC分类号： G03B27/42 , G03B27/58 , G03B27/62 , G01B11/00 , G03B27/54
CPC分类号： H01L23/544 , H01L2223/5442 , H01L2223/54426 , H01L2223/54453 , H01L2223/54466 , H01L2223/54493 , H01L2924/0002 , H01L2924/09701 , Y10S438/975 , H01L2924/00
摘要： An apparatus for aligning a mask having an image and at least one complimentary alignment mark to a substrate having a first surface and a substantially opposing second surface. The substrate further has at least one alignment mark on the second surface. A mask support supports the mask in proximity to the first surface of the substrate. A substrate support supports the substrate with the first surface in proximity to the mask. An alignment means aligns the at least one alignment mark on the second surface of the substrate to the at least one complimentary alignment mark on the mask. An exposure source projects the image of the mask onto the first surface of the substrate, and a controller controls the mask support, substrate support, alignment means, and exposure source.
摘要翻译：一种用于将具有图像和至少一个互补对准标记的掩模对准到具有第一表面和基本上相对的第二表面的基板的设备。基板还在第二表面上具有至少一个对准标记。掩模支撑件支撑靠近基板的第一表面的掩模。衬底支撑件支撑具有靠近掩模的第一表面的衬底。对准装置将衬底的第二表面上的至少一个对准标记对准掩模上的至少一个互补对准标记。曝光源将掩模的图像投影到基板的第一表面上，并且控制器控制掩模支撑件，基板支撑件，对准装置和曝光源。

6. 发明授权

US06964924B1 Integrated circuit process monitoring and metrology system 失效
标题翻译：集成电路过程监控与计量系统
公开(公告)号：US06964924B1
公开(公告)日：2005-11-15
申请号：US09952790
申请日：2001-09-11
申请人： Peter A. Burke , Eric J. Kirchner , James R. B. Elmer
发明人： Peter A. Burke , Eric J. Kirchner , James R. B. Elmer
IPC分类号： H01L21/302 , H01L21/3105 , H01L21/66 , H01L21/76 , H01L23/544
CPC分类号： H01L22/34 , H01L21/31053
摘要： A method for monitoring polishing process parameters for an integrated circuit structure on a substrate. A first metrology site is constructed on the substrate. The first metrology site represents a design extreme of a high density integrated circuit structure. The first metrology site is formed by placing a relatively small horizontal surface area trench within a relatively large surface area field of a polish stop material. A second metrology site is also constructed on the substrate. The second metrology site represents a design extreme of a low density integrated circuit structure. The second metrology site is formed by placing a relatively large horizontal surface area trench within a relatively small surface area field of a polish stop material. The substrate is covered with a layer of an insulating material, thereby at least filling the trenches. A target thickness of the insulating material necessary to leave the trenches substantially filled to a top surface of the field of polish stop material is calculated. The substrate is polished until a first thickness of the insulating material in the trench of the first metrology site is no more than the target thickness. A second thickness of the insulating material in the trench of the second metrology site is measured, and values based on the first thickness and the second thickness are monitored as the polishing process parameters for the integrated circuit structure.
摘要翻译：一种用于监测基板上的集成电路结构的抛光工艺参数的方法。第一个计量站点被构建在基板上。第一个测量站点代表了高密度集成电路结构的设计极限。第一计量站点是通过在抛光停止材料的相对大的表面区域内放置相对较小的水平表面区域沟槽而形成的。第二个计量站点也在基板上构建。第二个测量站点是低密度集成电路结构的设计极限。第二计量站点通过在抛光停止材料的相对小的表面区域内放置相对较大的水平表面区域沟槽而形成。衬底被绝缘材料层覆盖，从而至少填充沟槽。计算出将沟槽基本上填充到抛光停止材料领域的顶表面所需的绝缘材料的目标厚度。抛光衬底直到第一测量点的沟槽中的绝缘材料的第一厚度不超过目标厚度。测量第二测量位置的沟槽中的绝缘材料的第二厚度，并且监测基于第一厚度和第二厚度的值作为用于集成电路结构的抛光工艺参数。

7. 发明授权

US07915122B2 Self-aligned cell integration scheme 失效
标题翻译：自对准单元集成方案
公开(公告)号：US07915122B2
公开(公告)日：2011-03-29
申请号：US11312849
申请日：2005-12-20
申请人： Richard J. Carter , Hemanshu D. Bhatt , Shiqun Gu , Peter A. Burke , James R. B. Elmer , Sey-Shing Sun , Byung-Sung Kwak , Verne Hornback
发明人： Richard J. Carter , Hemanshu D. Bhatt , Shiqun Gu , Peter A. Burke , James R. B. Elmer , Sey-Shing Sun , Byung-Sung Kwak , Verne Hornback
IPC分类号： H01L21/336
CPC分类号： H01L51/0018 , B82Y10/00 , H01L27/283 , H01L51/0048 , H01L51/0545 , Y10S977/742
摘要： A method of forming a self-aligned logic cell. A nanotube layer is formed over the bottom electrode. A clamp layer is formed over the nanotube layer. The clamp layer covers the nanotube layer, thereby protecting the nanotube layer. A dielectric layer is formed over the clamp layer. The dielectric layer is etched. The clamp layer provides an etch stop and protects the nanotube layer. The clamp layer is etched with an isotropic etchant that etches the clamp layer underneath the dielectric layer, creating an overlap of the dielectric layer, and causing a self-alignment between the clamp layer and the dielectric layer. A spacer layer is formed over the nanotube layer. The spacer layer is etched except for a ring portion around the edge of the dielectric layer. The nanotube layer is etched except for portions that are underlying at least one of the clamp layer, the dielectric layer, and the spacer layer, thereby causing a self-alignment between the clamp layer, the overlap to the dielectric layer, the spacer layer, and the nanotube layer.
摘要翻译：一种形成自对准逻辑单元的方法。在底部电极上形成纳米管层。在纳米管层上形成夹层。夹层覆盖纳米管层，从而保护纳米管层。在钳位层上形成电介质层。蚀刻介电层。钳位层提供蚀刻停止并保护纳米管层。用各向同性蚀刻剂蚀刻钳夹层，蚀刻介质层下方的夹层，产生电介质层的重叠，并引起钳位层和电介质层之间的自对准。在纳米管层上形成间隔层。除了围绕电介质层的边缘的环形部分之外，蚀刻间隔层。除了夹持层，电介质层和间隔层中的至少一个的部分以外，蚀刻纳米管层，从而导致夹紧层之间的自对准，与电介质层的重叠，间隔层，和纳米管层。

8. 发明授权

US06856029B1 Process independent alignment marks 有权
标题翻译：过程独立对齐标记
公开(公告)号：US06856029B1
公开(公告)日：2005-02-15
申请号：US09887131
申请日：2001-06-22
申请人： David W. Daniel , James R. B. Elmer
发明人： David W. Daniel , James R. B. Elmer
IPC分类号： H01L23/544
CPC分类号： H01L23/544 , H01L2223/5442 , H01L2223/54426 , H01L2223/54453 , H01L2223/54466 , H01L2223/54493 , H01L2924/0002 , H01L2924/09701 , Y10S438/975 , H01L2924/00
摘要： An integrated circuit substrate having a first surface for receiving a series of aligned layers during the creation of the integrated circuit, and a second surface disposed substantially opposite the first surface, where the second surface has at least one alignment mark for aligning the series of aligned layers one to another during creation of the integrated circuit. An apparatus for aligning a mask having an image and at least one complimentary alignment mark to a substrate having a first surface and a substantially opposing second surface, where the substrate has at least one alignment mark on the second surface.
摘要翻译：一种集成电路基板，其具有用于在所述集成电路的创建期间接收一系列对准层的第一表面和与所述第一表面基本相对设置的第二表面，其中所述第二表面具有至少一个对准标记，在集成电路的创建期间彼此层叠。一种用于将具有图像和至少一个互补对准标记的掩模对准到具有第一表面和基本上相对的第二表面的基底的装置，其中所述基底在所述第二表面上具有至少一个对准标记。

9. 发明授权

US06710851B1 Multi pattern reticle 有权
标题翻译：多图案掩模版
公开(公告)号：US06710851B1
公开(公告)日：2004-03-23
申请号：US10060002
申请日：2002-01-29
申请人： James R. B. Elmer , Ann I. Kang
发明人： James R. B. Elmer , Ann I. Kang
IPC分类号： G03B2742
CPC分类号： G03F7/70433 , G03B27/42 , G03F1/50
摘要： A reticle includes multiple different layer patterns selected from a group comprising same circuit layer patterns and different circuit layer patterns. The layer patterns are positioned on the reticle within borders and within a portion of a defined x by y array on the reticle. The reticle is used to produce an integrated circuit of a single design or integrated circuits of multiple designs.
摘要翻译：掩模版包括从包括相同电路层图案和不同电路层图案的组中选择的多个不同层图案。层图案位于掩模版的边界内并且位于掩模版上定义的x×y阵列的一部分内。光罩用于制造单一设计的集成电路或多个设计的集成电路。

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