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1. 发明申请

US20110010501A1 EFFICIENT DATA PREFETCHING IN THE PRESENCE OF LOAD HITS 有权
标题翻译：有效的数据预处理在负载的存在
公开(公告)号：US20110010501A1
公开(公告)日：2011-01-13
申请号：US12763938
申请日：2010-04-20
申请人： Clinton Thomas Glover , Colin Eddy , Rodney E. Hooker , Albert J. Loper
发明人： Clinton Thomas Glover , Colin Eddy , Rodney E. Hooker , Albert J. Loper
IPC分类号： G06F12/08 , G06F12/00
CPC分类号： G06F12/0862 , G06F12/0859 , G06F12/0897 , G06F2212/6022
摘要： A BIU prioritizes L1 requests above L2 requests. The L2 generates a first request to the BIU and detects the generation of a snoop request and L1 request to the same cache line. The L2 determines whether a bus transaction to fulfill the first request may be retried and, if so, generates a miss, and otherwise generates a hit. Alternatively, the L2 detects the L1 generated a request to the L2 for the same line and responsively requests the BIU to refrain from performing a transaction on the bus to fulfill the first request if the BIU has not yet been granted the bus. Alternatively, a prefetch cache and the L2 allow the same line to be simultaneously present. If an L1 request hits in both the L2 and in the prefetch cache, the prefetch cache invalidates its copy of the line and the L2 provides the line to the L1.
摘要翻译： BIU将L1请求优先于L2请求。 L2产生对BIU的第一个请求，并检测到窥探请求和L1请求到同一个高速缓存行的生成。 L2确定是否可以重试履行第一请求的总线事务，如果是，则产生未命中，否则生成命中。或者，L2检测到L1产生对同一行的L2的请求，并且如果BIU尚未被授予总线，则响应地请求BIU在总线上不执行交易以执行第一请求。或者，预取高速缓存和L2允许同时存在同一行。如果L1请求都在L2和预取缓存中同时进行，则预取缓存使其副本无效，并且L2向L1提供该行。

2. 发明申请

US20120272003A1 EFFICIENT DATA PREFETCHING IN THE PRESENCE OF LOAD HITS 有权
标题翻译：有效的数据预处理在负载的存在
公开(公告)号：US20120272003A1
公开(公告)日：2012-10-25
申请号：US13535152
申请日：2012-06-27
申请人： Clinton Thomas Glover , Colin Eddy , Rodney E. Hooker , Albert J. Loper
发明人： Clinton Thomas Glover , Colin Eddy , Rodney E. Hooker , Albert J. Loper
IPC分类号： G06F12/08
CPC分类号： G06F12/0862 , G06F12/0859 , G06F12/0897 , G06F2212/6022
摘要： A microprocessor configured to access an external memory includes a first-level cache, a second-level cache, and a bus interface unit (BIU) configured to interface the first-level and second-level caches to a bus used to access the external memory. The BIU is configured to prioritize requests from the first-level cache above requests from the second-level cache. The second-level cache is configured to generate a first request to the BIU to fetch a cache line from the external memory. The second-level cache is also configured to detect that the first-level cache has subsequently generated a second request to the second-level cache for the same cache line. The second-level cache is also configured to request the BIU to refrain from performing a transaction on the bus to fulfill the first request if the BIU has not yet been granted ownership of the bus to fulfill the first request.
摘要翻译：被配置为访问外部存储器的微处理器包括：第一级高速缓存，第二级高速缓存和总线接口单元（BIU），其被配置为将第一级和第二级高速缓存连接到用于访问外部存储器的总线。 BIU被配置为优先考虑来自第二级缓存的来自第二级缓存的请求的请求。第二级缓存被配置为生成对BIU的第一请求以从外部存储器获取高速缓存行。第二级缓存还被配置为检测第一级高速缓存随后已经为同一高速缓存行生成了第二级缓存的第二请求。第二级缓存还被配置为如果BIU尚未被授予总线的所有权以满足第一请求，则要求BIU避免在总线上执行事务以满足第一请求。

3. 发明授权

US08543765B2 Efficient data prefetching in the presence of load hits 有权
标题翻译：有效的数据预取在有负载点击
公开(公告)号：US08543765B2
公开(公告)日：2013-09-24
申请号：US13535188
申请日：2012-06-27
申请人： Clinton Thomas Glover , Colin Eddy , Rodney E. Hooker , Albert J. Loper
发明人： Clinton Thomas Glover , Colin Eddy , Rodney E. Hooker , Albert J. Loper
IPC分类号： G06F12/08
CPC分类号： G06F12/0862 , G06F12/0859 , G06F12/0897 , G06F2212/6022
摘要： A memory subsystem in a microprocessor includes a first-level cache, a second-level cache, and a prefetch cache configured to speculatively prefetch cache lines from a memory external to the microprocessor. The second-level cache and the prefetch cache are configured to allow the same cache line to be simultaneously present in both. If a request by the first-level cache for a cache line hits in both the second-level cache and in the prefetch cache, the prefetch cache invalidates its copy of the cache line and the second-level cache provides the cache line to the first-level cache.
摘要翻译：微处理器中的存储器子系统包括第一级高速缓存，第二级高速缓存和预取高速缓存，其被配置为从微处理器外部的存储器推测性地预取高速缓存行。二级缓存和预取缓存被配置为允许同一个高速缓存行同时存在于两者中。如果缓存行的第一级缓存的请求在二级缓存和预取高速缓存中都击中，则预取缓存使其高速缓存行的副本无效，并且第二级缓存将高速缓存行提供给第一级高速缓存级缓存。

4. 发明授权

US08489823B2 Efficient data prefetching in the presence of load hits 有权
标题翻译：有效的数据预取在有负载点击
公开(公告)号：US08489823B2
公开(公告)日：2013-07-16
申请号：US13535152
申请日：2012-06-27
申请人： Clinton Thomas Glover , Colin Eddy , Rodney E. Hooker , Albert J. Loper
发明人： Clinton Thomas Glover , Colin Eddy , Rodney E. Hooker , Albert J. Loper
IPC分类号： G06F12/08
CPC分类号： G06F12/0862 , G06F12/0859 , G06F12/0897 , G06F2212/6022
摘要： A microprocessor configured to access an external memory includes a first-level cache, a second-level cache, and a bus interface unit (BIU) configured to interface the first-level and second-level caches to a bus used to access the external memory. The BIU is configured to prioritize requests from the first-level cache above requests from the second-level cache. The second-level cache is configured to generate a first request to the BIU to fetch a cache line from the external memory. The second-level cache is also configured to detect that the first-level cache has subsequently generated a second request to the second-level cache for the same cache line. The second-level cache is also configured to request the BIU to refrain from performing a transaction on the bus to fulfill the first request if the BIU has not yet been granted ownership of the bus to fulfill the first request.
摘要翻译：被配置为访问外部存储器的微处理器包括：第一级高速缓存，第二级高速缓存和总线接口单元（BIU），其被配置为将第一级和第二级高速缓存连接到用于访问外部存储器的总线。 BIU被配置为优先考虑来自第二级缓存的来自第二级缓存的请求的请求。第二级缓存被配置为生成对BIU的第一请求以从外部存储器获取高速缓存行。第二级缓存还被配置为检测第一级高速缓存随后已经为同一高速缓存行生成了第二级缓存的第二请求。第二级缓存还被配置为如果BIU尚未被授予总线的所有权以满足第一请求，则要求BIU避免在总线上执行事务以满足第一请求。

5. 发明申请

US20120272004A1 EFFICIENT DATA PREFETCHING IN THE PRESENCE OF LOAD HITS 有权
标题翻译：有效的数据预处理在负载的存在
公开(公告)号：US20120272004A1
公开(公告)日：2012-10-25
申请号：US13535188
申请日：2012-06-27
申请人： Clinton Thomas Glover , Colin Eddy , Rodney E. Hooker , Albert J. Loper
发明人： Clinton Thomas Glover , Colin Eddy , Rodney E. Hooker , Albert J. Loper
IPC分类号： G06F12/08
CPC分类号： G06F12/0862 , G06F12/0859 , G06F12/0897 , G06F2212/6022
摘要： A memory subsystem in a microprocessor includes a first-level cache, a second-level cache, and a prefetch cache configured to speculatively prefetch cache lines from a memory external to the microprocessor. The second-level cache and the prefetch cache are configured to allow the same cache line to be simultaneously present in both. If a request by the first-level cache for a cache line hits in both the second-level cache and in the prefetch cache, the prefetch cache invalidates its copy of the cache line and the second-level cache provides the cache line to the first-level cache.
摘要翻译：微处理器中的存储器子系统包括第一级高速缓存，第二级高速缓存和预取高速缓存，其被配置为从微处理器外部的存储器推测性地预取高速缓存行。二级缓存和预取缓存被配置为允许同一个高速缓存行同时存在于两者中。如果缓存行的第一级缓存的请求在二级缓存和预取高速缓存中都击中，则预取缓存使其高速缓存行的副本无效，并且第二级缓存将高速缓存行提供给第一级高速缓存级缓存。

6. 发明授权

US08234450B2 Efficient data prefetching in the presence of load hits 有权
标题翻译：有效的数据预取在有负载点击
公开(公告)号：US08234450B2
公开(公告)日：2012-07-31
申请号：US12763938
申请日：2010-04-20
申请人： Clinton Thomas Glover , Colin Eddy , Rodney E. Hooker , Albert J. Loper
发明人： Clinton Thomas Glover , Colin Eddy , Rodney E. Hooker , Albert J. Loper
IPC分类号： G06F12/08
CPC分类号： G06F12/0862 , G06F12/0859 , G06F12/0897 , G06F2212/6022
摘要： A BIU prioritizes L1 requests above L2 requests. The L2 generates a first request to the BIU and detects the generation of a snoop request and L1 request to the same cache line. The L2 determines whether a bus transaction to fulfill the first request may be retried and, if so, generates a miss, and otherwise generates a hit. Alternatively, the L2 detects the L1 generated a request to the L2 for the same line and responsively requests the BIU to refrain from performing a transaction on the bus to fulfill the first request if the BIU has not yet been granted the bus. Alternatively, a prefetch cache and the L2 allow the same line to be simultaneously present. If an L1 request hits in both the L2 and in the prefetch cache, the prefetch cache invalidates its copy of the line and the L2 provides the line to the L1.
摘要翻译： BIU将L1请求优先于L2请求。 L2产生对BIU的第一个请求，并检测到窥探请求和L1请求到同一个高速缓存行的生成。 L2确定是否可以重试履行第一请求的总线事务，如果是，则产生未命中，否则生成命中。或者，L2检测到L1产生对同一行的L2的请求，并且如果BIU尚未被授予总线，则响应地请求BIU在总线上不执行交易以执行第一请求。或者，预取高速缓存和L2允许同时存在同一行。如果L1请求都在L2和预取缓存中同时进行，则预取缓存使其副本无效，并且L2向L1提供该行。

7. 发明申请

US20110113196A1 AVOIDING MEMORY ACCESS LATENCY BY RETURNING HIT-MODIFIED WHEN HOLDING NON-MODIFIED DATA 有权
标题翻译：保存未经修改的数据时，通过恢复进行修改而避免内存访问延迟
公开(公告)号：US20110113196A1
公开(公告)日：2011-05-12
申请号：US12880958
申请日：2010-09-13
申请人： Rodney E. Hooker , Colin Eddy , Darius D. Gaskins , Albert J. Loper, JR.
发明人： Rodney E. Hooker , Colin Eddy , Darius D. Gaskins , Albert J. Loper, JR.
IPC分类号： G06F12/08
CPC分类号： G06F12/0831
摘要： A microprocessor is configured to communicate with other agents on a system bus and includes a cache memory and a bus interface unit coupled to the cache memory and to the system bus. The bus interface unit receives from another agent coupled to the system bus a transaction to read data from a memory address, determines whether the cache memory is holding the data at the memory address in an exclusive state (or a shared state in certain configurations), and asserts a hit-modified signal on the system bus and provides the data on the system bus to the other agent when the cache memory is holding the data at the memory address in an exclusive state. Thus, the delay of an access to the system memory by the other agent is avoided.
摘要翻译：微处理器被配置为与系统总线上的其他代理通信，并且包括高速缓存存储器和耦合到高速缓冲存储器和系统总线的总线接口单元。总线接口单元从耦合到系统总线的另一个代理接收从存储器地址读取数据的事务，确定高速缓冲存储器是否处于处于独占状态（或某些配置中的共享状态）的存储器地址处的数据，并且当高速缓冲存储器将数据保存在处于独占状态的存储器地址时，在系统总线上断言命中修正信号并将系统总线上的数据提供给另一个代理。因此，避免了其他代理对系统存储器的访问的延迟。

8. 发明授权

US08364906B2 Avoiding memory access latency by returning hit-modified when holding non-modified data 有权
标题翻译：在保存未修改的数据时，通过返回命中修改来避免内存访问延迟
公开(公告)号：US08364906B2
公开(公告)日：2013-01-29
申请号：US12880958
申请日：2010-09-13
申请人： Rodney E. Hooker , Colin Eddy , Darius D. Gaskins , Albert J. Loper, Jr.
发明人： Rodney E. Hooker , Colin Eddy , Darius D. Gaskins , Albert J. Loper, Jr.
IPC分类号： G06F12/00
CPC分类号： G06F12/0831
摘要： A microprocessor is configured to communicate with other agents on a system bus and includes a cache memory and a bus interface unit coupled to the cache memory and to the system bus. The bus interface unit receives from another agent coupled to the system bus a transaction to read data from a memory address, determines whether the cache memory is holding the data at the memory address in an exclusive state (or a shared state in certain configurations), and asserts a hit-modified signal on the system bus and provides the data on the system bus to the other agent when the cache memory is holding the data at the memory address in an exclusive state. Thus, the delay of an access to the system memory by the other agent is avoided.
摘要翻译：微处理器被配置为与系统总线上的其他代理通信，并且包括高速缓存存储器和耦合到高速缓冲存储器和系统总线的总线接口单元。总线接口单元从耦合到系统总线的另一个代理接收从存储器地址读取数据的事务，确定高速缓冲存储器是否处于处于独占状态（或某些配置中的共享状态）的存储器地址处的数据，并且当高速缓冲存储器将数据保存在处于独占状态的存储器地址时，在系统总线上断言命中修正信号并将系统总线上的数据提供给另一个代理。因此，避免了其他代理对系统存储器的访问的延迟。

9. 发明授权

US09952875B2 Microprocessor with ALU integrated into store unit 有权
公开(公告)号：US09952875B2
公开(公告)日：2018-04-24
申请号：US12609193
申请日：2009-10-30
申请人： Gerard M. Col , Colin Eddy , Rodney E. Hooker
发明人： Gerard M. Col , Colin Eddy , Rodney E. Hooker
IPC分类号： G06F9/312 , G06F9/38 , G06F9/30 , G06F12/0875
CPC分类号： G06F9/3875 , G06F9/3001 , G06F9/3004 , G06F9/30043 , G06F9/30145 , G06F9/3017 , G06F9/3893 , G06F12/0875
摘要： A superscalar pipelined microprocessor includes a register set defined by an instruction set architecture of the microprocessor, execution units, and a store unit, coupled to the cache memory and distinct from the other execution units of the microprocessor. The store unit comprises an ALU. The store unit receives an instruction that specifies a source register of the register set and an operation to be performed on a source operand to generate a result. The store unit reads the source operand from the source register. The ALU performs the operation on the source operand to generate the result, rather than forwarding the source operand to any of the other execution units of the microprocessor to perform the operation on the source operand to generate the result. The store unit operatively writes the result to the cache memory.

10. 发明申请

US20140122847A1 MICROPROCESSOR THAT TRANSLATES CONDITIONAL LOAD/STORE INSTRUCTIONS INTO VARIABLE NUMBER OF MICROINSTRUCTIONS 有权
标题翻译：将条件负载/存储指令转换成可变数量的微处理器的微处理器
公开(公告)号：US20140122847A1
公开(公告)日：2014-05-01
申请号：US14007116
申请日：2012-04-06
申请人： G. Glenn Henry , Terry Parks , Rodney E. Hooker , Gerard M. Col , Colin Eddy
发明人： G. Glenn Henry , Terry Parks , Rodney E. Hooker , Gerard M. Col , Colin Eddy
IPC分类号： G06F9/26
CPC分类号： G06F9/441 , G06F9/265 , G06F9/30043 , G06F9/30072 , G06F9/30076 , G06F9/30105 , G06F9/30123 , G06F9/30145 , G06F9/3017 , G06F9/30174 , G06F9/30189 , G06F9/30196 , G06F9/3802 , G06F9/4401 , G06F9/4403 , G06F15/82
摘要： An instruction translator receives a conditional load/store instruction that specifies a condition, destination/data register, base register, offset source, and memory addressing mode. The instruction instructs the microprocessor to load data from a memory location into the destination register (conditional load) or store data to the memory location from the data register (conditional store) only if the condition flags satisfy the condition. The offset source specifies whether the offset is an immediate value or a value in an offset register. The addressing mode specifies whether the base register is updated when the condition flags satisfy the condition. The instruction translator translates the conditional load instruction into a number of microinstructions, which varies as a function of the offset source, addressing mode, and whether the conditional instruction is a conditional load or store instruction. An out-of-order execution pipeline executes the microinstructions to generate results specified by the instruction.
摘要翻译：指令转换器接收指定条件，目标/数据寄存器，基址寄存器，偏移源和存储器寻址模式的条件加载/存储指令。只有当条件标志满足条件时，指令才指示微处理器将数据从存储单元加载到目标寄存器（条件加载）中，或者将数据从数据寄存器（条件存储）存储到存储单元。偏移源指定偏移量是立即值还是偏移量寄存器中的值。寻址模式指定条件标志满足条件时是否更新基址寄存器。指令翻译器将条件加载指令转换为多个微指令，其作为偏移源，寻址模式以及条件指令是条件加载还是存储指令的函数而变化。无序执行流水线执行微指令以生成指令指定的结果。

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