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1. 发明授权

US5296733A Hetero junction bipolar transistor with improved electrode wiring contact region 失效
标题翻译：具有改进的电极接线区域的异质结双极晶体管
公开(公告)号：US5296733A
公开(公告)日：1994-03-22
申请号：US615381
申请日：1990-11-19
申请人： Chushiroh Kusano , Hiroshi Masuda , Katsuhiko Mitani , Kazuhiro Mochizuki , Masaru Miyazaki , Masahiko Kawata , Susumu Takahashi
发明人： Chushiroh Kusano , Hiroshi Masuda , Katsuhiko Mitani , Kazuhiro Mochizuki , Masaru Miyazaki , Masahiko Kawata , Susumu Takahashi
IPC分类号： H01L29/73 , H01L21/331 , H01L29/205 , H01L29/737 , H01L29/72 , H01L29/06
CPC分类号： H01L29/7371
摘要： A hetero junction bipolar transistor provides a contact area an area between an emitter (or collector) electrode and a wiring formed on the electrode that is larger than that of the emitter (or collector). A variation in voltage applied to an emitter (or collector)-base junctions is prevented and a stable operation of the transistor is attained. In addition, when an etching operation is carried out, an insulation film is formed on a side part of a mask. A patterning of the emitter (or collector) is then carried out and thus an emitter (or collector) having a size approximate to that of the mask is formed.
摘要翻译：异质结双极晶体管提供接触区域，其在发射极（或集电极）电极和形成在电极上的布线之间的面积大于发射极（或集电极）的面积。防止施加到发射极（或集电极） - 基极结的电压变化，并且获得晶体管的稳定操作。另外，当进行蚀刻操作时，在掩模的侧面上形成绝缘膜。然后执行发射极（或集电极）的图案化，因此形成具有接近于掩模的尺寸的发射极（或集电极）。

2. 发明授权

US5668402A Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：US5668402A
公开(公告)日：1997-09-16
申请号：US66635
申请日：1993-05-24
申请人： Kazuhiro Mochizuki , Shigeo Goto , Chushirou Kusano , Masahiko Kawata , Hiroshi Masuda , Katsuhiko Mitani , Susumu Takahashi
发明人： Kazuhiro Mochizuki , Shigeo Goto , Chushirou Kusano , Masahiko Kawata , Hiroshi Masuda , Katsuhiko Mitani , Susumu Takahashi
IPC分类号： H01L29/73 , A61F7/02 , H01L21/20 , H01L21/331 , H01L21/338 , H01L29/04 , H01L29/205 , H01L29/737 , H01L29/812
CPC分类号： H01L29/045 , H01L21/02395 , H01L21/02433 , H01L21/02463 , H01L21/02505 , H01L21/02532 , H01L21/02546 , H01L21/02609 , A61F2007/0265
摘要： A semiconductor device comprises a semiconductor substrate formed by a first single crystalline semiconductor material and semiconductor layers formed on the semiconductor substrate by a second single crystalline semiconductor material doped with an element which can easily surface segregate. The surface of the semiconductor substrate is formed of a crystalline plane substantially equivalent to a facet plane which is formed on the surface of the second single crystalline semiconductor material if the second single crystalline semiconductor material is epitaxially grown with being doped with the element on a (100) plane of the first single crystalline semiconductor material.
摘要翻译：半导体器件包括由第一单晶半导体材料形成的半导体衬底和通过掺杂有易于表面分离的元件的第二单晶半导体材料形成在半导体衬底上的半导体层。半导体衬底的表面由与第二单晶半导体材料的表面上形成的小平面基本相同的晶面形成，如果第二单晶半导体材料被外延生长，在第 100）平面的第一单晶半导体材料。

3. 发明授权

US5017517A Method of fabricating semiconductor device using an Sb protection layer 失效
标题翻译：使用Sb保护层制造半导体器件的方法
公开(公告)号：US5017517A
公开(公告)日：1991-05-21
申请号：US518035
申请日：1990-05-02
申请人： Kazuhiro Mochizuki , Tomonori Tanoue , Chushirou Kusano , Hiroshi Masuda , Katsuhiko Mitani
发明人： Kazuhiro Mochizuki , Tomonori Tanoue , Chushirou Kusano , Hiroshi Masuda , Katsuhiko Mitani
IPC分类号： H01L29/73 , H01L21/20 , H01L21/28 , H01L21/331 , H01L29/205 , H01L29/737 , H01L29/80
CPC分类号： H01L29/66318 , H01L21/02395 , H01L21/02463 , H01L21/02491 , H01L21/02546 , H01L21/02639 , H01L21/28 , Y10S148/005 , Y10S148/011 , Y10S148/026 , Y10S438/976
摘要： A method for fabricating a semiconductor device comprises the steps of forming the first semiconductor layer on a semiconductor substrate, forming a surface protection layer of antimony (Sb) or the material having Sb as its main component, executing the other steps necessary for the fabrication of the semiconductor device, removing the surface protection layer, and forming, on the first semiconductor layer thus exposed, the second semiconductor layer.
摘要翻译：一种制造半导体器件的方法包括以下步骤：在半导体衬底上形成第一半导体层，形成锑（Sb）的表面保护层或具有Sb的材料作为其主要成分，执行制造所需的其它步骤半导体器件，去除表面保护层，并且在由此暴露的第一半导体层上形成第二半导体层。

4. 发明授权

US5949097A Semiconductor device, method for manufacturing same, communication system and electric circuit system 失效
标题翻译：半导体装置及其制造方法，通信系统及电路系统
公开(公告)号：US5949097A
公开(公告)日：1999-09-07
申请号：US932939
申请日：1997-09-17
申请人： Koji Hirata , Tomonori Tanoue , Hiroshi Masuda , Hiroyuki Uchiyama , Kazuhiro Mochizuki
发明人： Koji Hirata , Tomonori Tanoue , Hiroshi Masuda , Hiroyuki Uchiyama , Kazuhiro Mochizuki
IPC分类号： H01L21/331 , H01L21/768 , H01L27/06 , H01L29/737 , H01L29/04
CPC分类号： H01L29/66318 , H01L27/0605 , H01L29/7371
摘要： The present invention relates to a contact structure not only for a semiconductor device having a hetero-junction bipolar transistor or a hetero-insulated gate field effect transistor but also for semiconductor devices at large. In a semiconductor layer of a polycrystalline or amorphous undoped III-V compound semiconductor or an alloy thereof, a through hole is formed for contact. The size of the through hole is set to permit exposure of at least part of a first conductor layer and a dielectric layer, such as an Si compound, present around the first conductor layer, and a second conductor layer is formed within the through hole so as to contact the first conductor layer. Since the semiconductor layer can be subjected to a selective dry etching for the dielectric layer, the dielectric layer is not etched at the time of forming the above through hole in the semiconductor layer. As a result an electric short-circuit of the second conductor layer with a single crystal semiconductor layer which underlies the dielectric layer can be prevented.
摘要翻译：本发明涉及不仅具有异质结双极晶体管或异质绝缘栅场效应晶体管的半导体器件的接触结构，而且还涉及用于半导体器件的半导体器件。在多晶或非晶未掺杂的III-V族化合物半导体的半导体层或其合金中，形成用于接触的通孔。通孔的尺寸被设定为允许暴露在第一导体层周围的第一导体层和诸如Si化合物的电介质层的至少一部分，并且在通孔内形成第二导体层，因此以接触第一导体层。由于可以对半导体层进行电介质层的选择性干蚀刻，所以在形成半导体层中的上述通孔时不会蚀刻电介质层。结果，可以防止具有位于电介质层下面的单晶半导体层的第二导体层的电短路。

5. 发明授权

US5481120A Semiconductor device and its fabrication method 失效
标题翻译：半导体器件及其制造方法
公开(公告)号：US5481120A
公开(公告)日：1996-01-02
申请号：US164801
申请日：1993-12-10
申请人： Kazuhiro Mochizuki , Tomoyoshi Mishima , Tohru Nakamura , Hiroshi Masuda , Tomonori Tanoue , Tooru Haga , Yoshihisa Fujisaki
发明人： Kazuhiro Mochizuki , Tomoyoshi Mishima , Tohru Nakamura , Hiroshi Masuda , Tomonori Tanoue , Tooru Haga , Yoshihisa Fujisaki
IPC分类号： H01L21/331 , H01L29/08 , H01L29/20 , H01L29/45 , H01L29/737 , H01L29/80 , H01S5/042 , H01S5/183 , H01S5/22 , H01S5/323 , H01L27/02
CPC分类号： H01S5/18347 , H01L29/0891 , H01L29/20 , H01L29/452 , H01L29/66318 , H01L29/7371 , H01S5/0424 , H01L29/802 , H01S2304/02 , H01S5/18341 , H01S5/18369 , H01S5/32316
摘要： Disclosed is a semiconductor device using a polycrystalline compound semiconductor with a low resistance as a low resistance layer, and its fabrication method. The above polycrystalline compound semiconductor layer is doped with C or Be as impurities in a large amount, and is extremely low in resistance. The polycrystalline compound semiconductor layer is formed by either of a molecular beam epitaxy method, an organometallic vapor phase epitaxy method and an organometallic molecular beam epitaxy method under the condition that a substrate temperature is 450.degree. C. or less and the ratio of partial pressure of a V-group element to a III-group element is 50 or more. In the case that the above polycrystaline compound semiconductor layer with a low resistance is used as an extrinsic base region of an heterojunction bipolar transistor, since the extrinsic base region can be formed on a dielectric film formed on a collector, it is possible to reduce the base-collector capacitance, and hence to enhance the operational speed of the heterojunction bipolar transistor.
摘要翻译：公开了使用具有低电阻的多晶化合物半导体作为低电阻层的半导体器件及其制造方法。上述多晶化合物半导体层以C或Be作为杂质被大量掺杂，并且电阻极低。多晶化合物半导体层通过分子束外延法，有机金属气相外延法和有机金属分子束外延法中的任一种形成，在基板温度为450℃以下的条件下，对于III族元素的V族元素为50以上。在上述具有低电阻的多晶化合物半导体层用作异质结双极晶体管的外在基极区域的情况下，由于可以在形成在集电体上的电介质膜上形成非本征基区，因此可以减少基极集电极电容，从而提高异质结双极晶体管的工作速度。

6. 发明申请

US20070073448A1 Semiconductor device having a hole or a step of normal mesa shape as viewed from any cross-section and manufacturing method of the same 审中-公开
标题翻译：具有从任何横截面观察的具有孔或台阶正常台面形状的半导体器件及其制造方法
公开(公告)号：US20070073448A1
公开(公告)日：2007-03-29
申请号：US11583885
申请日：2006-10-20
申请人： Chisaki Takubo , Hiroji Yamada , Kazuhiro Mochizuki , Kenichi Tanaka , Tomonori Tanoue , Hiroyuki Uchiyama
发明人： Chisaki Takubo , Hiroji Yamada , Kazuhiro Mochizuki , Kenichi Tanaka , Tomonori Tanoue , Hiroyuki Uchiyama
IPC分类号： G05D1/10
CPC分类号： H01L21/30617 , H01L29/045 , H01L29/0657 , H01L29/66318 , H01L29/7371
摘要： A semiconductor device capable of overcoming a drawback due to the shape of a concave portion present in the zinc blende type compound semiconductor substrate in which the area of the bottom is larger than the surface in the cross sectional shape, as well as a manufacturing method thereof. A hole or step present in the semiconductor substrate constituting the semiconductor device is formed into a normal mesa shape irrespective of the orientation of the crystals on the surface of the semiconductor substrate. A wet etching solution having an etching rate for a portion below the etching mask higher than that in the direction of the depth of the semiconductor substrate is used.
摘要翻译：一种半导体器件及其制造方法，其能够克服存在于闪锌矿型化合物半导体衬底中的凹部的形状的缺陷，其中底部的面积大于截面形状的表面，以及其制造方法。存在于构成半导体器件的半导体衬底中的孔或台阶形成为正常台面形状，而与半导体衬底的表面上的晶体取向无关。使用对蚀刻掩模下方的蚀刻速率比半导体衬底的深度方向的蚀刻速度更高的湿蚀刻溶液。

7. 发明申请

US20060163696A1 Metal base transistor and oscillator using the same 审中-公开
标题翻译：金属基极晶体管和振荡器使用相同
公开(公告)号：US20060163696A1
公开(公告)日：2006-07-27
申请号：US11208561
申请日：2005-08-23
申请人： Kazuhiro Mochizuki , Shigehisa Tanaka , Tomonori Tanoue
发明人： Kazuhiro Mochizuki , Shigehisa Tanaka , Tomonori Tanoue
IPC分类号： H01L27/082
CPC分类号： H01L29/7606 , H01L29/2003
摘要： The most important task in realizing a downsized and low cost THz band spectroscopic and fluoroscopic instrument is to achieve downsizing and cost reduction of oscillators used in the instrument. A metal base transistor is used for an active element of the oscillator. In order to improve the maximum oscillation frequency of the transistor to several THZ, InN having a high electron saturation velocity or a material mainly composed of InN is used for a collector layer. In order to obtain characteristics with excellent reproducibility, it is useful to insert InGaN into an interface between the collector layer and the base layer. Using the metal base transistor of the present invention makes it possible to constitute an oscillator allowing a THz band oscillation. Further, the present invention provides a spectroscopic instrument applying this oscillator to at least one of a signal source and a local oscillator.
摘要翻译：实现小型化，低成本的太赫兹频带光谱和荧光检测仪器最重要的任务是实现仪器中使用的振荡器的小型化和降低成本。金属基极晶体管用于振荡器的有源元件。为了将晶体管的最大振荡频率提高到几个THZ，具有高电子饱和速度的InN或主要由InN组成的材料用于集电极层。为了获得具有优异再现性的特性，将InGaN插入到集电极层和基极层之间的界面是有用的。使用本发明的金属基极晶体管可以构成允许THz频带振荡的振荡器。此外，本发明提供了一种将该振荡器应用于信号源和本地振荡器中的至少一个的分光仪器。

8. 发明授权

US06743691B2 Semiconductor device and method for fabricating the same 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US06743691B2
公开(公告)日：2004-06-01
申请号：US10026613
申请日：2001-12-27
申请人： Atsushi Kurokawa , Masao Yamane , Kazuhiro Mochizuki
发明人： Atsushi Kurokawa , Masao Yamane , Kazuhiro Mochizuki
IPC分类号： H01L218222
CPC分类号： H01L29/7304 , H01L21/8252 , H01L27/0605 , H01L28/20 , H01L29/73
摘要： A bipolar transistor device with a large current capacity is formed by connecting a plurality of transistor elements to each other in parallel, each transistor element having a collector layer, a base layer, and an emitter layer formed respectively in a semiconductor substrate. In the bipolar transistor device, the base layers of a plurality of the transistor elements are extended in parallel to each other and those base layers are separated from each other. In each separated base layer, a first base electrode is formed on a part of the base layer which is separated from an emitter junction with the emitter layer, and a second base electrode is formed on another portion of the base layer closer to the emitter junction than the first base electrode. To dispose the base electrodes of a plurality of the transistor elements in parallel to each other, a base wiring is connected to the first base electrodes of those elements electrically. Consequently, a ballast resistor that causes no variation in the resistance value can be connected to each of a plurality of the transistor elements.
摘要翻译：通过并联连接多个晶体管元件来形成具有大电流容量的双极晶体管器件，每个晶体管元件具有分别形成在半导体衬底中的集电极层，基极层和发射极层。在双极晶体管器件中，多个晶体管元件的基极层彼此平行地延伸，并且这些基极层彼此分离。在每个分离的基底层中，第一基极形成在与发射极层的发射极结分离的基底层的一部分上，并且第二基极形成在基极层的更靠近发射极结的另一部分比第一基极。为了将多个晶体管元件的基极电极彼此平行地配置，基极配线与这些元件的第一基极电连接。因此，不会导致电阻值变动的镇流电阻器可以连接到多个晶体管元件中的每一个。

9. 发明授权

US06573540B2 Semiconductor device and method for fabricating the same 失效
公开(公告)号：US06573540B2
公开(公告)日：2003-06-03
申请号：US10026968
申请日：2001-12-27
申请人： Atsushi Kurokawa , Masao Yamane , Kazuhiro Mochizuki
发明人： Atsushi Kurokawa , Masao Yamane , Kazuhiro Mochizuki
IPC分类号： H01L31072
CPC分类号： H01L29/7304 , H01L21/8252 , H01L27/0605 , H01L28/20 , H01L29/73
摘要： A bipolar transistor device with a large current capacity is formed by connecting a plurality of transistor elements to each other in parallel, each transistor element having a collector layer, a base layer, and an emitter layer formed respectively in a semiconductor substrate. In the bipolar transistor device, the base layers of a plurality of the transistor elements are extended in parallel to each other and those base layers are separated from each other. In each separated base layer, a first base electrode is formed on a part of the base layer which is separated from an emitter junction with the emitter layer, and a second base electrode is formed on another portion of the base layer closer to the emitter junction than the first base electrode. To dispose the base electrodes of a plurality of the transistor elements in parallel to each other, a base wiring is connected to the first base electrodes of those elements electrically. Consequently, a ballast resistor that causes no variation in the resistance value can be connected to each of a plurality of the transistor elements.

10. 发明授权

US08476731B2 Nitride semiconductor diode 有权
标题翻译：氮化物半导体二极管
公开(公告)号：US08476731B2
公开(公告)日：2013-07-02
申请号：US13349959
申请日：2012-01-13
申请人： Akihisa Terano , Kazuhiro Mochizuki , Takashi Ishigaki
发明人： Akihisa Terano , Kazuhiro Mochizuki , Takashi Ishigaki
IPC分类号： H01L29/47 , H01L29/40
CPC分类号： H01L29/872 , H01L29/0649 , H01L29/2003
摘要： In a Schottky electrode formation region on a nitride semiconductor, the total length of junctions of Schottky electrodes and a surface of a nitride semiconductor layer is longer than the perimeter of the Schottky electrode formation region. The total length is preferably 10 times longer than the perimeter. For example, the Schottky electrodes are formed concentrically and circularly.
摘要翻译：在氮化物半导体上的肖特基电极形成区域中，肖特基电极和氮化物半导体层的表面的总长度比肖特基电极形成区域的周长长。总长度优选比周长长10倍。例如，肖特基电极同心圆形地形成。

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