专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20070073448A1 Semiconductor device having a hole or a step of normal mesa shape as viewed from any cross-section and manufacturing method of the same 审中-公开
标题翻译：具有从任何横截面观察的具有孔或台阶正常台面形状的半导体器件及其制造方法
公开(公告)号：US20070073448A1
公开(公告)日：2007-03-29
申请号：US11583885
申请日：2006-10-20
申请人： Chisaki Takubo , Hiroji Yamada , Kazuhiro Mochizuki , Kenichi Tanaka , Tomonori Tanoue , Hiroyuki Uchiyama
发明人： Chisaki Takubo , Hiroji Yamada , Kazuhiro Mochizuki , Kenichi Tanaka , Tomonori Tanoue , Hiroyuki Uchiyama
IPC分类号： G05D1/10
CPC分类号： H01L21/30617 , H01L29/045 , H01L29/0657 , H01L29/66318 , H01L29/7371
摘要： A semiconductor device capable of overcoming a drawback due to the shape of a concave portion present in the zinc blende type compound semiconductor substrate in which the area of the bottom is larger than the surface in the cross sectional shape, as well as a manufacturing method thereof. A hole or step present in the semiconductor substrate constituting the semiconductor device is formed into a normal mesa shape irrespective of the orientation of the crystals on the surface of the semiconductor substrate. A wet etching solution having an etching rate for a portion below the etching mask higher than that in the direction of the depth of the semiconductor substrate is used.
摘要翻译：一种半导体器件及其制造方法，其能够克服存在于闪锌矿型化合物半导体衬底中的凹部的形状的缺陷，其中底部的面积大于截面形状的表面，以及其制造方法。存在于构成半导体器件的半导体衬底中的孔或台阶形成为正常台面形状，而与半导体衬底的表面上的晶体取向无关。使用对蚀刻掩模下方的蚀刻速率比半导体衬底的深度方向的蚀刻速度更高的湿蚀刻溶液。

2. 发明申请

US20050040497A1 Semiconductor device and manufacturing method of the same 审中-公开
标题翻译：半导体器件及其制造方法相同
公开(公告)号：US20050040497A1
公开(公告)日：2005-02-24
申请号：US10878358
申请日：2004-06-29
申请人： Chisaki Takubo , Hiroji Yamada , Kazuhiro Mochizuki , Kenichi Tanaka , Tomonori Tanoue , Hiroyuki Uchiyama
发明人： Chisaki Takubo , Hiroji Yamada , Kazuhiro Mochizuki , Kenichi Tanaka , Tomonori Tanoue , Hiroyuki Uchiyama
IPC分类号： H01L21/331 , H01L21/306 , H01L29/04 , H01L29/06 , H01L29/737
CPC分类号： H01L29/7371 , H01L21/30612 , H01L29/045 , H01L29/0657
摘要： The technical subject of the invention is to inhibit disconnection of electrodes caused by a step and bursting caused by residual air. That is, an object of the present invention is to provide a semiconductor device capable of overcoming a drawback due to the shape of a concave portion present in the zinc blende type compound semiconductor substrate in which the area of the bottom is larger than the surface in the cross sectional shape, as well as a manufacturing method thereof. According to the invention, a hole or step present in the semiconductor substrate constituting the semiconductor device is formed into a normal mesa shape irrespective of the orientation of the crystals on the surface of the semiconductor substrate. Accordingly, the present invention uses a novel wet etching solution having an etching rate for a portion below the etching mask higher than that in the direction of the depth of the semiconductor substrate.
摘要翻译：本发明的技术课题是抑制由残留空气引起的台阶和破裂引起的电极断开。也就是说，本发明的目的是提供一种半导体器件，其能够克服存在于闪锌矿型化合物半导体衬底中的凹部的形状的缺陷，其中底部的面积大于其中的表面横截面形状及其制造方法。根据本发明，构成半导体器件的半导体衬底中存在的孔或台阶形成为正常的台面形状，而与半导体衬底的表面上的晶体取向无关。因此，本发明使用对蚀刻掩模下方的蚀刻速度高于半导体衬底的深度方向的蚀刻速率的新型湿式蚀刻溶液。

3. 发明申请

US20060081879A1 Semiconductor device and a manufacturing method thereof, and semiconductor module 失效
标题翻译：半导体装置及其制造方法以及半导体模块
公开(公告)号：US20060081879A1
公开(公告)日：2006-04-20
申请号：US11247234
申请日：2005-10-12
申请人： Kenichi Tanaka , Hidetoshi Matsumoto , Isao Ohbu , Kazuhiro Mochizuki , Tomonori Tanoue , Chisaki Takubo , Hiroyuki Uchiyama
发明人： Kenichi Tanaka , Hidetoshi Matsumoto , Isao Ohbu , Kazuhiro Mochizuki , Tomonori Tanoue , Chisaki Takubo , Hiroyuki Uchiyama
IPC分类号： H01L31/109
CPC分类号： H01L23/482 , H01L24/48 , H01L2224/48091 , H01L2224/48227 , H01L2924/00014 , H01L2924/01078 , H01L2924/01079 , H01L2924/09701 , H01L2924/12041 , H01L2924/1305 , H01L2924/14 , H01L2924/1423 , H01L2924/16152 , H01L2924/19041 , H01L2924/30107 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： The present invention provides a semiconductor device which comprises active components, passive components, wiring lines and electrodes and are satisfactory in terms of mechanical strength, miniaturization and thermal stability. In the semiconductor device, openings are formed just below active components. These openings are filled with conductor layers. Conductor layers are also formed where openings are not formed.
摘要翻译：本发明提供一种半导体器件，其包括有源部件，无源部件，布线和电极，并且在机械强度，小型化和热稳定性方面令人满意。在半导体器件中，开口形成在活性部件的正下方。这些开口填充有导体层。还形成了未形成开口的导体层。

4. 发明授权

US07547929B2 Semiconductor HBT MMIC device and semiconductor module 失效
标题翻译：半导体HBT MMIC器件和半导体模块
公开(公告)号：US07547929B2
公开(公告)日：2009-06-16
申请号：US11247234
申请日：2005-10-12
申请人： Kenichi Tanaka , Hidetoshi Matsumoto , Isao Ohbu , Kazuhiro Mochizuki , Tomonori Tanoue , Chisaki Takubo , Hiroyuki Uchiyama
发明人： Kenichi Tanaka , Hidetoshi Matsumoto , Isao Ohbu , Kazuhiro Mochizuki , Tomonori Tanoue , Chisaki Takubo , Hiroyuki Uchiyama
IPC分类号： H01L29/40
CPC分类号： H01L23/482 , H01L24/48 , H01L2224/48091 , H01L2224/48227 , H01L2924/00014 , H01L2924/01078 , H01L2924/01079 , H01L2924/09701 , H01L2924/12041 , H01L2924/1305 , H01L2924/14 , H01L2924/1423 , H01L2924/16152 , H01L2924/19041 , H01L2924/30107 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： The present invention provides a semiconductor device which comprises active components, passive components, wiring lines and electrodes and are satisfactory in terms of mechanical strength, miniaturization and thermal stability. In the semiconductor device, openings are formed just below active components. These openings are filled with conductor layers. Conductor layers are also formed where openings are not formed.
摘要翻译：本发明提供一种半导体器件，其包括有源部件，无源部件，布线和电极，并且在机械强度，小型化和热稳定性方面令人满意。在半导体器件中，开口形成在活性部件的正下方。这些开口填充有导体层。还形成了未形成开口的导体层。

5. 发明授权

US07067857B2 Semiconductor device having led out conductor layers, manufacturing method of the same, and semiconductor module 失效
标题翻译：具有引出导体层的半导体器件，其制造方法和半导体模块
公开(公告)号：US07067857B2
公开(公告)日：2006-06-27
申请号：US10788277
申请日：2004-03-01
申请人： Kazuhiro Mochizuki , Isao Ohbu , Tomonori Tanoue , Chisaki Takubo , Kenichi Tanaka
发明人： Kazuhiro Mochizuki , Isao Ohbu , Tomonori Tanoue , Chisaki Takubo , Kenichi Tanaka
IPC分类号： H01L29/739 , H01L31/0328 , H01L31/0336 , H01L31/072 , H01L31/109
CPC分类号： H01L27/0823 , H01L29/41708 , H01L29/42304 , H01L29/7371 , H01L2224/05568 , H01L2224/05573 , H01L2224/16 , H01L2224/16225 , H01L2924/00014 , H01L2924/01078 , H01L2924/01079 , H01L2924/09701 , H01L2924/1305 , H01L2924/16152 , H01L2924/19105 , H01L2924/00 , H01L2224/05599
摘要： The gist of the present invention is as follows: In a monolithic microwave integrate circuit (MMIC) using a heterojunction bipolar transistor (HBT), via holes are respectively formed from the bottom of the MMIC for the emitter, base and collector. Of the via holes, one is located so as to face the HBT. The respective topside electrodes for the other via holes located so as not to face the HBT are provided in contact with the MMIC substrate.
摘要翻译：本发明的要点如下：在使用异质结双极晶体管（HBT）的单片微波积分电路（MMIC）中，从MMIC的底部分别形成用于发射极，基极和集电极的通孔。通孔中的一个位于与HBT相对的位置。用于不与HBT相对的另一个通孔的相应顶侧电极设置成与MMIC衬底接触。

6. 发明授权

US07276744B2 Semiconductor device and method of manufacturing the same 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US07276744B2
公开(公告)日：2007-10-02
申请号：US11316908
申请日：2005-12-27
申请人： Kenichi Tanaka , Tomonori Tanoue , Hidetoshi Matsumoto , Hiroshi Ohta , Kazuhiro Mochizuki , Hiroyuki Uchiyama
发明人： Kenichi Tanaka , Tomonori Tanoue , Hidetoshi Matsumoto , Hiroshi Ohta , Kazuhiro Mochizuki , Hiroyuki Uchiyama
IPC分类号： H01L29/33 , H01L31/109
CPC分类号： H01L29/7371 , H01L29/66318
摘要： This invention is intended to provide an HBT capable of achieving, if the HBT is a collector-up HBT, the constriction of the emitter layer disposed directly under an external base layer, and reduction in base-emitter junction capacity, or if the HBT is an emitter-up HBT, reduction in base-collector junction capacity. For the collector-up HBT, window structures around the sidewalls of a collector are used to etch either the emitter layer disposed directly under the external base layer, or an emitter contact layer For the emitter-up HBT, window structures around the sidewalls of an emitter are used to etch either the collector layer disposed directly under the external base layer, or a collector contact layer. In both HBTs, the external base layer is supported by a columnar structure to ensure mechanical strength.
摘要翻译：本发明旨在提供一种如果HBT是集电极HBT，则可以实现直接位于外部基极层下方的发射极层的收缩，以及基极 - 发射极结能量的降低，或HBT为发射极HBT，基极 - 集电极结电容降低。对于收集器HBT，围绕集电极侧壁的窗口结构用于蚀刻直接位于外部基极层下方的发射极层或发射极接触层。对于发射极上升HBT，围绕侧壁的窗口结构发射极用于蚀刻直接位于外部基底层下方的集电极层或集电极接触层。在两个HBT中，外部基层由柱状结构支撑以确保机械强度。

7. 发明申请

US20060138458A1 Semiconductor device and method of manufacturing the same 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US20060138458A1
公开(公告)日：2006-06-29
申请号：US11316908
申请日：2005-12-27
申请人： Kenichi Tanaka , Tomonori Tanoue , Hidetoshi Matsumoto , Hiroshi Ohta , Kazuhiro Mochizuki , Hiroyuki Uchiyama
发明人： Kenichi Tanaka , Tomonori Tanoue , Hidetoshi Matsumoto , Hiroshi Ohta , Kazuhiro Mochizuki , Hiroyuki Uchiyama
IPC分类号： H01L31/109
CPC分类号： H01L29/7371 , H01L29/66318
摘要： This invention is intended to provide an HBT capable of achieving, if the HBT is a collector-up HBT, the constriction of the emitter layer disposed directly under an external base layer, and reduction in base-emitter junction capacity, or if the HBT is an emitter-up HBT, reduction in base-collector junction capacity. For the collector-up HBT, window structures around the sidewalls of a collector are used to etch either the emitter layer disposed directly under the external base layer, or an emitter contact layer For the emitter-up HBT, window structures around the sidewalls of an emitter are used to etch either the collector layer disposed directly under the external base layer, or a collector contact layer. In both HBTs, the external base layer is supported by a columnar structure to ensure mechanical strength.
摘要翻译：本发明旨在提供一种如果HBT是集电极HBT，则可以实现直接位于外部基极层下方的发射极层的收缩，以及基极 - 发射极结能量的降低，或HBT为发射极HBT，基极 - 集电极结电容降低。对于收集器HBT，围绕集电极侧壁的窗口结构用于蚀刻直接位于外部基极层下方的发射极层或发射极接触层。对于发射极上升HBT，围绕侧壁的窗口结构发射极用于蚀刻直接位于外部基底层下方的集电极层或集电极接触层。在两个HBT中，外部基层由柱状结构支撑以确保机械强度。

8. 发明授权

US06984871B2 Semiconductor device with high structural reliability and low parasitic capacitance 失效
标题翻译：具有高结构可靠性和低寄生电容的半导体器件
公开(公告)号：US06984871B2
公开(公告)日：2006-01-10
申请号：US10441096
申请日：2003-05-20
申请人： Tomonori Tanoue , Kazuhiro Mochizuki , Hiroji Yamada
发明人： Tomonori Tanoue , Kazuhiro Mochizuki , Hiroji Yamada
IPC分类号： H01L27/082
CPC分类号： H01L29/66318 , H01L24/32 , H01L29/0657 , H01L29/0692 , H01L29/41708 , H01L29/7371 , H01L2924/1305 , H01L2924/15787 , H01L2924/00
摘要： A semiconductor device with high structural reliability and low parasitic capacitance is provided. In one example, the semiconductor device has a surface. The semiconductor device comprises a semiconductor region, wherein an emitter region, a base region, and a collector region are laminated from a side near a substrate of the semiconductor region; an insulating protection layer disposed on the surface; and a wiring layer disposed on the surface, the insulating protection layer forming a via hole from the side of the substrate of the semiconductor region, the via hole being formed to allow the wiring layer to make a contact to an electrode of the emitter region from a side of the substrate where the emitter region, the base region, and the collector region are laminated and where the semiconductor region is isolated.
摘要翻译：提供具有高结构可靠性和低寄生电容的半导体器件。在一个示例中，半导体器件具有表面。半导体器件包括半导体区域，其中从半导体区域的衬底附近的一侧层叠发射极区域，基极区域和集电极区域; 设置在所述表面上的绝缘保护层; 以及设置在所述表面上的布线层，所述绝缘保护层从所述半导体区域的所述基板的侧面形成通孔，所述通孔形成为允许所述布线层与所述发射极区域的电极接触衬底的一侧，其中发射极区域，基极区域和集电极区域被层叠并且半导体区域被隔离。

9. 发明授权

US5949097A Semiconductor device, method for manufacturing same, communication system and electric circuit system 失效
标题翻译：半导体装置及其制造方法，通信系统及电路系统
公开(公告)号：US5949097A
公开(公告)日：1999-09-07
申请号：US932939
申请日：1997-09-17
申请人： Koji Hirata , Tomonori Tanoue , Hiroshi Masuda , Hiroyuki Uchiyama , Kazuhiro Mochizuki
发明人： Koji Hirata , Tomonori Tanoue , Hiroshi Masuda , Hiroyuki Uchiyama , Kazuhiro Mochizuki
IPC分类号： H01L21/331 , H01L21/768 , H01L27/06 , H01L29/737 , H01L29/04
CPC分类号： H01L29/66318 , H01L27/0605 , H01L29/7371
摘要： The present invention relates to a contact structure not only for a semiconductor device having a hetero-junction bipolar transistor or a hetero-insulated gate field effect transistor but also for semiconductor devices at large. In a semiconductor layer of a polycrystalline or amorphous undoped III-V compound semiconductor or an alloy thereof, a through hole is formed for contact. The size of the through hole is set to permit exposure of at least part of a first conductor layer and a dielectric layer, such as an Si compound, present around the first conductor layer, and a second conductor layer is formed within the through hole so as to contact the first conductor layer. Since the semiconductor layer can be subjected to a selective dry etching for the dielectric layer, the dielectric layer is not etched at the time of forming the above through hole in the semiconductor layer. As a result an electric short-circuit of the second conductor layer with a single crystal semiconductor layer which underlies the dielectric layer can be prevented.
摘要翻译：本发明涉及不仅具有异质结双极晶体管或异质绝缘栅场效应晶体管的半导体器件的接触结构，而且还涉及用于半导体器件的半导体器件。在多晶或非晶未掺杂的III-V族化合物半导体的半导体层或其合金中，形成用于接触的通孔。通孔的尺寸被设定为允许暴露在第一导体层周围的第一导体层和诸如Si化合物的电介质层的至少一部分，并且在通孔内形成第二导体层，因此以接触第一导体层。由于可以对半导体层进行电介质层的选择性干蚀刻，所以在形成半导体层中的上述通孔时不会蚀刻电介质层。结果，可以防止具有位于电介质层下面的单晶半导体层的第二导体层的电短路。

10. 发明申请

US20060163696A1 Metal base transistor and oscillator using the same 审中-公开
标题翻译：金属基极晶体管和振荡器使用相同
公开(公告)号：US20060163696A1
公开(公告)日：2006-07-27
申请号：US11208561
申请日：2005-08-23
申请人： Kazuhiro Mochizuki , Shigehisa Tanaka , Tomonori Tanoue
发明人： Kazuhiro Mochizuki , Shigehisa Tanaka , Tomonori Tanoue
IPC分类号： H01L27/082
CPC分类号： H01L29/7606 , H01L29/2003
摘要： The most important task in realizing a downsized and low cost THz band spectroscopic and fluoroscopic instrument is to achieve downsizing and cost reduction of oscillators used in the instrument. A metal base transistor is used for an active element of the oscillator. In order to improve the maximum oscillation frequency of the transistor to several THZ, InN having a high electron saturation velocity or a material mainly composed of InN is used for a collector layer. In order to obtain characteristics with excellent reproducibility, it is useful to insert InGaN into an interface between the collector layer and the base layer. Using the metal base transistor of the present invention makes it possible to constitute an oscillator allowing a THz band oscillation. Further, the present invention provides a spectroscopic instrument applying this oscillator to at least one of a signal source and a local oscillator.
摘要翻译：实现小型化，低成本的太赫兹频带光谱和荧光检测仪器最重要的任务是实现仪器中使用的振荡器的小型化和降低成本。金属基极晶体管用于振荡器的有源元件。为了将晶体管的最大振荡频率提高到几个THZ，具有高电子饱和速度的InN或主要由InN组成的材料用于集电极层。为了获得具有优异再现性的特性，将InGaN插入到集电极层和基极层之间的界面是有用的。使用本发明的金属基极晶体管可以构成允许THz频带振荡的振荡器。此外，本发明提供了一种将该振荡器应用于信号源和本地振荡器中的至少一个的分光仪器。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式