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1. 发明授权

US5821725A Electric current compensation circuit for brushless motors for reducing ripples in output torques during phase change 失效
标题翻译：用于无刷电机的电流补偿电路，用于在相变期间减少输出转矩波动
公开(公告)号：US5821725A
公开(公告)日：1998-10-13
申请号：US731461
申请日：1996-10-16
申请人： Chung-Cheng Wang , Jin-Chern Chiou , Shih-Tung Cheng
发明人： Chung-Cheng Wang , Jin-Chern Chiou , Shih-Tung Cheng
IPC分类号： H02P6/10 , H02P5/28
CPC分类号： H02P6/10
摘要： An electric current compensation circuit for use with a multiple-phase burshless motor to reduce ripples in the output torque is disclosed. It contains a plurality of electric current compensation loops each for a respective phase winding and each of the electric compensation loops contains: (a) a first input for receiving a line current from the driver; (b) a second input for receiving the compensation current from the motor sensor; (c) a forward rectifying circuit for forwardly rectifying the line current and the compensation current; (d) a reverse rectifying circuit for reversely rectifying the line current and the compensation current; and (e) a summation circuit for summing the forwardly rectified compensation current and the reversely rectified compensation current and outputting a synthetic current to a phase winding of the motor. Each time the phase is changed, the electric current compensation circuit is triggered causing the synthetic current to be sent to the motor to allow the motor to generate an output torque with reduced ripple.
摘要翻译：公开了一种与多相无刷电机一起使用以减少输出转矩波纹的电流补偿电路。它包含多个电流补偿回路，每个电流补偿回路各自用于各自的相绕组，并且每个电补偿回路包含：（a）用于接收来自驾驶员的线电流的第一输入; （b）用于从电动机传感器接收补偿电流的第二输入; （c）正向整流线路电流和补偿电流的正向整流电路; （d）用于反向整流线路电流和补偿电流的反向整流电路; 和（e）用于将前向整流补偿电流和逆整流补偿电流相加的求和电路，并将合成电流输出到电动机的相绕组。每次相位改变时，触发电流补偿电路，使得合成电流被发送到电动机，以允许电动机产生具有减小的纹波的输出转矩。

2. 发明授权

US07994633B2 Substrate for electrical device 有权
标题翻译：电气设备基板
公开(公告)号：US07994633B2
公开(公告)日：2011-08-09
申请号：US12852458
申请日：2010-08-07
申请人： Chung-Cheng Wang
发明人： Chung-Cheng Wang
IPC分类号： H01L23/48 , H01L21/48
CPC分类号： H01L23/49805 , H01L23/3121 , H01L23/3128 , H01L23/3677 , H01L23/49861 , H01L24/48 , H01L24/49 , H01L25/0652 , H01L2224/48091 , H01L2224/48227 , H01L2224/4824 , H01L2224/49109 , H01L2924/00014 , H01L2924/01046 , H01L2924/01078 , H01L2924/01079 , H01L2924/09701 , H01L2924/15331 , H01L2924/19041 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： Substrate for electrical devices is disclosed. An embodiment for the substrate comprised of an insulator, a conductive element(s) and a conductive material(s), wherein the conductive element embedded in the insulator, and two surfaces of the conductive element exposed to two surfaces of the insulator for electrical connection respectively, wherein the upper surface of conductive element is below the upper surface of insulator and is plated by the conductive material, meanwhile the conductive element include a protruding portion which is protruded the insulator, in this manner, solder balls are not needed, moreover the conductive element can further include an extending portion; the present invention may be capable of affording a thinner electrical device thickness and enhanced reliability.
摘要翻译：公开了用于电气设备的基板。用于由绝缘体，导电元件和导电材料组成的衬底的实施例，其中嵌入绝缘体中的导电元件和暴露于绝缘体的两个表面的两个表面用于电连接其中导电元件的上表面在绝缘体的上表面下方并被导电材料电镀，同时导电元件包括突出绝缘体的突出部分，以这种方式不需要焊球，此外，导电元件还可以包括延伸部分; 本发明可以提供更薄的电气装置厚度和增强的可靠性。

3. 发明授权

US07317243B2 Encapsulated lead having step configuration 失效
标题翻译：具有步骤配置的封装引线
公开(公告)号：US07317243B2
公开(公告)日：2008-01-08
申请号：US10944808
申请日：2004-09-21
申请人： Chung-Cheng Wang
发明人： Chung-Cheng Wang
IPC分类号： H01L23/495 , H01L21/00
CPC分类号： H01L21/6835 , H01L23/24 , H01L23/3114 , H01L23/4334 , H01L23/4951 , H01L23/49861 , H01L24/48 , H01L24/49 , H01L24/94 , H01L25/03 , H01L25/105 , H01L2224/48091 , H01L2224/48247 , H01L2224/48253 , H01L2224/4826 , H01L2224/48465 , H01L2224/49109 , H01L2224/49171 , H01L2224/73215 , H01L2225/06568 , H01L2225/1035 , H01L2225/1041 , H01L2225/1058 , H01L2924/00014 , H01L2924/01019 , H01L2924/01029 , H01L2924/01046 , H01L2924/01078 , H01L2924/01079 , H01L2924/12041 , H01L2924/15311 , H01L2924/1532 , H01L2924/181 , H01L2924/18165 , H01L2924/19105 , H01L2924/3511 , H05K1/183 , H05K3/064 , H05K3/403 , H05K2201/09036 , H05K2201/09645 , H05K2201/09845 , H05K2203/0369 , H05K2203/1476 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： Substrate for electrical devices and methods of manufacturing such substrate are disclosed. An embodiment for the substrate comprised of an insulator and a plurality of conductive elements, wherein the insulator having a recess. The conductive elements embedded in the insulator. The conductive elements extend from the insulator surface to the recess. There are two portions of the conductive elements for electrical connection respectively, wherein a portion of conductive element may protrude the insulator surface for electrical connection. In this manner, solder balls are not needed. Moreover, the substrate of the present invention may also comprise an adhesive mean, which is between the conductive elements and the insulator. In addition, the substrate may further comprise a submember such as a chip, heat spreader etc., and the present invention may be capable of affording a thinner electrical device thickness, enhanced reliability, and a decreased cost in production.
摘要翻译：公开了用于电气装置的基板和制造这种基板的方法。用于由绝缘体和多个导电元件组成的衬底的实施例，其中绝缘体具有凹部。绝缘子中嵌入的导电元件。导电元件从绝缘体表面延伸到凹槽。用于电连接的导电元件分为两部分，其中导电元件的一部分可以突出绝缘体表面用于电连接。以这种方式，不需要焊球。此外，本发明的基底还可以包括位于导电元件和绝缘体之间的粘合剂。此外，基板还可以包括诸如芯片，散热器等的子部件，并且本发明可以提供更薄的电气设备厚度，增强的可靠性和降低的生产成本。

4. 发明申请

US20070132517A1 Automatic Frequency Tuning in a Phase Lock Loop 有权
标题翻译：锁相环自动调频
公开(公告)号：US20070132517A1
公开(公告)日：2007-06-14
申请号：US11164924
申请日：2005-12-12
申请人： Chung-Cheng Wang , Chao-Shi Chuang , Wen-Shih Lu , Yu-Chang Chen
发明人： Chung-Cheng Wang , Chao-Shi Chuang , Wen-Shih Lu , Yu-Chang Chen
IPC分类号： H03L7/00
CPC分类号： H03L7/10
摘要： A method for automatic frequency tuning in a phase lock loop suitable for use in multi-band VCO wireless systems having very limited initial frequency lock times is disclosed. A predetermined subset of VCOs out of a larger bank of VCOs is selected to serve as interpolation points. The interpolation point VCOs are pre-calibrated with a predetermined voltage and the resultingly generated frequency for each of the interpolation point VCOs is stored into memory as a (frequency, VCO) pair, one pair for each interpolation point VCO. When a desired frequency then is given to the system, an appropriate VCO is selected by interpolation using the (frequency, VCO) pairs of the two most adjacent interpolation points for tracking and locking.
摘要翻译：公开了一种适用于具有非常有限的初始频率锁定时间的多频带VCO无线系统的锁相环中的自动频率调谐方法。选择较大的VCO组中的VCO的预定子集用作内插点。内插点VCO以预定电压进行预校准，并且每个内插点VCO的最终产生的频率作为（频率，VCO）对存储到存储器中，对于每个内插点VCO为一对。当给系统给出期望的频率时，通过使用用于跟踪和锁定的两个最相邻插值点的（频率，VCO）对进行插值来选择适当的VCO。

5. 发明申请

US20060281433A1 Method and apparatus for demodulation 审中-公开
标题翻译：用于解调的方法和装置
公开(公告)号：US20060281433A1
公开(公告)日：2006-12-14
申请号：US11451425
申请日：2006-06-13
申请人： John-San Yang , Chung-Cheng Wang , Yu-Hua Liu
发明人： John-San Yang , Chung-Cheng Wang , Yu-Hua Liu
IPC分类号： H04B1/26
CPC分类号： H04B1/26
摘要： A demodulation method and apparatus are provided. An RF signal is down converted to generate a first in-phase signal and a first quadrature signal of a first frequency. Limiting amplification is performed on the first in-phase signal and the first quadrature signal to generate a second in-phase signal and a second quadrature signal. The frequency of the second in-phase and quadrature signals are up converted to a third in-phase signal and a quadrature signal of a second frequency. The third in-phase and quadrature signals are up converted to generate an intermediate frequency (IF) signal of a third frequency.
摘要翻译：提供了解调方法和装置。 RF信号被下变频以产生第一频率的第一同相信号和第一正交信号。对第一同相信号和第一正交信号进行限幅放大以产生第二同相信号和第二正交信号。第二同相和正交信号的频率被上变频为第三同相信号和第二频率的正交信号。第三同相和正交信号被上变频以产生第三频率的中频（IF）信号。

6. 发明授权

US07180376B2 Synthesizer and calibrating method for the same 有权
标题翻译：合成仪和校准方法相同
公开(公告)号：US07180376B2
公开(公告)日：2007-02-20
申请号：US11034484
申请日：2005-01-13
申请人： Chong-Ren Wang , Chao-Shi Chuang , Chung-Cheng Wang
发明人： Chong-Ren Wang , Chao-Shi Chuang , Chung-Cheng Wang
IPC分类号： H03L7/00
CPC分类号： H03L7/1976 , H03L7/0898
摘要： Synthesizer and calibrating method utilizing same. The frequency synthesizer modulates input signals comprising a phase locked loop circuit. The phase locked loop circuit comprises a phase frequency detector for generating a first signal, a low pass filter for outputting a filtered control signal derived from the received first signal, a voltage control oscillator for generating an output signal with a first frequency based on the control signal, a frequency divider dividing the first frequency for output to the input terminal of the phase frequency detector, a modulator coupled to the frequency divider, a pre-emphasis filter receiving and filtering the input signal for output to the modulator, and an auto loop gain calibration circuit, receiving the control signal, and calculating a current gain of the control signal in accordance with the voltage of the control signal to compensate for the frequency response mismatch between the pre-emphasis filter and the frequency synthesizer.
摘要翻译：合成器和校准方法利用它。频率合成器调制包括锁相环电路的输入信号。锁相环电路包括用于产生第一信号的相位频率检测器，用于输出从接收到的第一信号导出的经滤波的控制信号的低通滤波器，用于基于控制产生具有第一频率的输出信号的电压控制振荡器信号，将第一频率分频输出到相位频率检测器的输入端的分频器，耦合到分频器的调制器，预加重滤波器接收和滤波输入信号以输出到调制器，以及自动回路增益校准电路，接收控制信号，以及根据控制信号的电压计算控制信号的当前增益，以补偿预加重滤波器和频率合成器之间的频率响应失配。

7. 发明申请

US20060279446A1 Method and apparatus for RF signal demodulation 审中-公开
标题翻译： RF信号解调的方法和装置
公开(公告)号：US20060279446A1
公开(公告)日：2006-12-14
申请号：US11451362
申请日：2006-06-13
申请人： Chung-Cheng Wang , John-San Yang
发明人： Chung-Cheng Wang , John-San Yang
IPC分类号： H03M1/12
CPC分类号： H04B1/28 , H04B1/0028 , H04B1/0032
摘要： A radio frequency (RF) receiver is provided, comprising an antenna, a low noise amplifier, a down converter, a first analog to digital converter (ADC), a second ADC, a digital up converter. The antenna receives an RF signal, and the LNA coupled to the antenna amplifies the RF signal. The down converter, coupled to the LNA, down converts the RF signal to generate an in-phase baseband signal and a quadrature baseband signal. The first ADC, coupled to the down converter, digitizes the in-phase baseband signal to an in-phase digital signal. The second ADC, coupled to the down converter, digitizes the quadrature baseband signal to a quadrature digital signal. The digital up converter, coupled to the first and second ADCs, up converts the in-phase digital signal and quadrature digital signal to generate an intermediate frequency (IF) signal.
摘要翻译：提供了一种射频（RF）接收机，包括天线，低噪声放大器，下变频器，第一模数转换器（ADC），第二ADC，数字上变频器。天线接收RF信号，耦合到天线的LNA放大RF信号。耦合到LNA的下变频器将RF信号下变频以产生同相基带信号和正交基带信号。耦合到下变频器的第一个ADC将同相基带信号数字化为同相数字信号。耦合到下变频器的第二个ADC将正交基带信号数字化为正交数字信号。耦合到第一和第二ADC的数字上变频器向上转换同相数字信号和正交数字信号以产生中频（IF）信号。

8. 发明申请

US20050156676A1 Synthesizer and calibrating method for the same 有权
标题翻译：合成仪和校准方法相同
公开(公告)号：US20050156676A1
公开(公告)日：2005-07-21
申请号：US11034484
申请日：2005-01-13
申请人： Chong-Ren Wang , Chao-Shi Chuang , Chung-Cheng Wang
发明人： Chong-Ren Wang , Chao-Shi Chuang , Chung-Cheng Wang
IPC分类号： H03L7/00 , H03L7/089 , H03L7/16 , H03L7/197
CPC分类号： H03L7/1976 , H03L7/0898
摘要： Synthesizer and calibrating method utilizing same. The frequency synthesizer modulates input signals comprising a phase locked loop circuit. The phase locked loop circuit comprises a phase frequency detector for generating a first signal, a low pass filter for outputting a filtered control signal derived from the received first signal, a voltage control oscillator for generating an output signal with a first frequency based on the control signal, a frequency divider dividing the first frequency for output to the input terminal of the phase frequency detector, a modulator coupled to the frequency divider, a pre-emphasis filter receiving and filtering the input signal for output to the modulator, and an auto loop gain calibration circuit, receiving the control signal, and calculating a current gain of the control signal in accordance with the voltage of the control signal to compensate for the frequency response mismatch between the pre-emphasis filter and the frequency synthesizer.
摘要翻译：合成器和校准方法利用它。频率合成器调制包括锁相环电路的输入信号。锁相环电路包括用于产生第一信号的相位频率检测器，用于输出从接收到的第一信号导出的经滤波的控制信号的低通滤波器，用于基于控制产生具有第一频率的输出信号的电压控制振荡器信号，将第一频率分频输出到相位频率检测器的输入端的分频器，耦合到分频器的调制器，预加重滤波器接收和滤波输入信号以输出到调制器，以及自动回路增益校准电路，接收控制信号，以及根据控制信号的电压计算控制信号的当前增益，以补偿预加重滤波器和频率合成器之间的频率响应失配。

9. 发明申请

US20220387756A1 URETHRAL CATHETERIZATION SYSTEM, URINARY CATHETER CONVEYING DEVICE THEREOF, AND METHOD OF USING THE SAME 有权
公开(公告)号：US20220387756A1
公开(公告)日：2022-12-08
申请号：US17830845
申请日：2022-06-02
申请人： Chung-Cheng Wang , Yung-Ping Wang , Yi-Yuan Chen , Chia-Ming Hsu , Ming-Chien Chiu , Chia-Ch Lin
发明人： Chung-Cheng Wang , Yung-Ping Wang , Yi-Yuan Chen , Chia-Ming Hsu
IPC分类号： A61M25/01
摘要： A urinary catheter conveying device includes a sleeve member, a conveying assembly and a controller. The sleeve member is for sleeving onto a glans of a penis and has a guiding hole to be registered with an external urethral orifice of the glans. The conveying assembly includes a casing removably mounted to the sleeve member, and a conveying mechanism for advancing the urinary catheter to the guiding hole such that the urinary catheter is inserted into the external urethral orifice. The controller controls the conveying mechanism to advance the urinary catheter to the guiding hole. A urinary catheterization system and a method of using the urinary catheterization system are also disclosed.

10. 发明授权

US07301415B2 Automatic frequency tuning in a phase lock loop 有权
标题翻译：在锁相环中进行自动频率调谐
公开(公告)号：US07301415B2
公开(公告)日：2007-11-27
申请号：US11164924
申请日：2005-12-12
申请人： Chung-Cheng Wang , Chao-Shi Chuang , Wen-Shih Lu , Yu-Chang Chen
发明人： Chung-Cheng Wang , Chao-Shi Chuang , Wen-Shih Lu , Yu-Chang Chen
IPC分类号： H03B1/00
CPC分类号： H03L7/10
摘要： A method for automatic frequency tuning in a phase lock loop suitable for use in multi-band VCO wireless systems having very limited initial frequency lock times is disclosed. A predetermined subset of VCOs out of a larger bank of VCOs is selected to serve as interpolation points. The interpolation point VCOs are pre-calibrated with a predetermined voltage and the resultingly generated frequency for each of the interpolation point VCOs is stored into memory as a (frequency, VCO) pair, one pair for each interpolation point VCO. When a desired frequency then is given to the system, an appropriate VCO is selected by interpolation using the (frequency, VCO) pairs of the two most adjacent interpolation points for tracking and locking.
摘要翻译：公开了一种适用于具有非常有限的初始频率锁定时间的多频带VCO无线系统的锁相环中的自动频率调谐方法。选择较大的VCO组中的VCO的预定子集用作内插点。内插点VCO以预定电压进行预校准，并且每个内插点VCO的最终产生的频率作为（频率，VCO）对存储到存储器中，对于每个内插点VCO为一对。当给系统给出期望的频率时，通过使用用于跟踪和锁定的两个最相邻插值点的（频率，VCO）对进行插值来选择适当的VCO。

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