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1. 发明申请

US20070001770A1 Phase lock loop and operating method thereof 有权
标题翻译：锁相环及其操作方法
公开(公告)号：US20070001770A1
公开(公告)日：2007-01-04
申请号：US11455730
申请日：2006-06-20
申请人： Chung-Cheng Wang , Chao-Shi Chuang , Yi-Chuan Liu
发明人： Chung-Cheng Wang , Chao-Shi Chuang , Yi-Chuan Liu
IPC分类号： H03L7/00
CPC分类号： H03L7/113 , H03L7/1972
摘要： A PLL is provided, comprising a first divider, a PFD, a loop filter, a VCO, a second divider and a controller. The first divider receives a reference signal and divides the reference signal by R to obtain a divided signal. The PFD compares the divided signal and a feedback signal to generate a compared The VCO selects one of a plurality of operating curves for oscillation based on a selection signal, and generates an oscillation signal based on an operating voltage generated by signal the loop filter. The second divider divides the oscillation signal by N to obtain the feedback signal. The controller operates in an initial mode to recursively determine the selection signal by calculating differences of the feedback signal and the divided signal. When the selection signal converges to stable, the PLL switches to a normal mode to operate on the corresponding operating curve.
摘要翻译：提供PLL，包括第一分频器，PFD，环路滤波器，VCO，第二分频器和控制器。第一分频器接收参考信号并将参考信号除以R以获得分频信号。 PFD比较分频信号和反馈信号以产生比较VCO基于选择信号选择多个用于振荡的操作曲线中的一个，并且基于由环路滤波器的信号产生的工作电压产生振荡信号。第二分频器将振荡信号除以N以获得反馈信号。控制器以初始模式工作，通过计算反馈信号和分频信号的差异递归地确定选择信号。当选择信号收敛到稳定时，PLL切换到正常模式，以对相应的工作曲线进行操作。

2. 发明申请

US20050137816A1 METHOD FOR AUTOMATICALLY CALIBRATING THE FREQUENCY RANGE OF A PLL AND ASSOCIATED PLL CAPABLE OF AUTOMATIC CALIBRATION 失效
标题翻译：用于自动校准PLL的相关范围的方法和可自动校准的相关PLL
公开(公告)号：US20050137816A1
公开(公告)日：2005-06-23
申请号：US10707519
申请日：2003-12-19
申请人： Chao-Shi Chuang , Chung-Cheng Wang , Wen-Shih Lu
发明人： Chao-Shi Chuang , Chung-Cheng Wang , Wen-Shih Lu
IPC分类号： G06F19/00 , H03L7/08 , H03L7/089 , H03L7/099 , H03L7/113 , H03L7/18 , H03L7/199
CPC分类号： H03L7/113 , H03L7/0891 , H03L7/099 , H03L7/199
摘要： A PLL includes a loop filter for accumulating charge to generate a loop-filter voltage and a VCO having a plurality of frequency ranges. The VCO receives the loop-filter voltage and generates an output signal having a frequency according to the loop-filter voltage and a currently selected VCO frequency range. During PLL calibration, the loop-filter is connected to a constant voltage source; the PLL feedback signal is synchronized with the reference signal; a linear search, a binary search, or a memory lookup is used to find a first and a second VCO frequency range; first and second time durations are measured for the time durations between the second rising edges of the reference signal and the PLL feedback signal for the two VCO frequency ranges, and the optimal VCO frequency range is determined by setting the VCO frequency range to be the VCO frequency range having the shortest measured time duration.
摘要翻译： PLL包括用于累积电荷以产生环路滤波器电压的环路滤波器和具有多个频率范围的VCO。 VCO接收环路滤波器电压，并产生具有根据环路滤波器电压和当前选择的VCO频率范围的频率的输出信号。在PLL校准期间，环路滤波器连接到恒定电压源; PLL反馈信号与参考信号同步; 使用线性搜索，二进制搜索或存储器查找来找到第一和第二VCO频率范围; 对于参考信号的第二上升沿和两个VCO频率范围的PLL反馈信号之间的持续时间测量第一和第二持续时间，并且通过将VCO频率范围设置为VCO来确定最佳VCO频率范围频率范围具有最短的测量持续时间。

3. 发明授权

US07511579B2 Phase lock loop and operating method thereof 有权
标题翻译：锁相环及其操作方法
公开(公告)号：US07511579B2
公开(公告)日：2009-03-31
申请号：US11455730
申请日：2006-06-20
申请人： Chung-Cheng Wang , Chao-Shi Chuang , Yi-Chuan Liu
发明人： Chung-Cheng Wang , Chao-Shi Chuang , Yi-Chuan Liu
IPC分类号： H03L7/08
CPC分类号： H03L7/113 , H03L7/1972
摘要： A PLL is provided, comprising a first divider, a PFD, a loop filter, a VCO, a second divider and a controller. The first divider receives a reference signal and divides the reference signal by R to obtain a divided signal. The PFD compares the divided signal and a feedback signal to generate a compared The VCO selects one of a plurality of operating curves for oscillation based on a selection signal, and generates an oscillation signal based on an operating voltage generated by signal the loop filter. The second divider divides the oscillation signal by N to obtain the feedback signal. The controller operates in an initial mode to recursively determine the selection signal by calculating differences of the feedback signal and the divided signal. When the selection signal converges to stable, the PLL switches to a normal mode to operate on the corresponding operating curve.
摘要翻译：提供PLL，包括第一分频器，PFD，环路滤波器，VCO，第二分频器和控制器。第一分频器接收参考信号并将参考信号除以R以获得分频信号。 PFD比较分频信号和反馈信号以产生比较VCO基于选择信号选择多个用于振荡的操作曲线中的一个，并且基于由环路滤波器的信号产生的工作电压产生振荡信号。第二分频器将振荡信号除以N以获得反馈信号。控制器以初始模式工作，通过计算反馈信号和分频信号的差异递归地确定选择信号。当选择信号收敛到稳定时，PLL切换到正常模式，以对相应的工作曲线进行操作。

4. 发明授权

US07180376B2 Synthesizer and calibrating method for the same 有权
标题翻译：合成仪和校准方法相同
公开(公告)号：US07180376B2
公开(公告)日：2007-02-20
申请号：US11034484
申请日：2005-01-13
申请人： Chong-Ren Wang , Chao-Shi Chuang , Chung-Cheng Wang
发明人： Chong-Ren Wang , Chao-Shi Chuang , Chung-Cheng Wang
IPC分类号： H03L7/00
CPC分类号： H03L7/1976 , H03L7/0898
摘要： Synthesizer and calibrating method utilizing same. The frequency synthesizer modulates input signals comprising a phase locked loop circuit. The phase locked loop circuit comprises a phase frequency detector for generating a first signal, a low pass filter for outputting a filtered control signal derived from the received first signal, a voltage control oscillator for generating an output signal with a first frequency based on the control signal, a frequency divider dividing the first frequency for output to the input terminal of the phase frequency detector, a modulator coupled to the frequency divider, a pre-emphasis filter receiving and filtering the input signal for output to the modulator, and an auto loop gain calibration circuit, receiving the control signal, and calculating a current gain of the control signal in accordance with the voltage of the control signal to compensate for the frequency response mismatch between the pre-emphasis filter and the frequency synthesizer.
摘要翻译：合成器和校准方法利用它。频率合成器调制包括锁相环电路的输入信号。锁相环电路包括用于产生第一信号的相位频率检测器，用于输出从接收到的第一信号导出的经滤波的控制信号的低通滤波器，用于基于控制产生具有第一频率的输出信号的电压控制振荡器信号，将第一频率分频输出到相位频率检测器的输入端的分频器，耦合到分频器的调制器，预加重滤波器接收和滤波输入信号以输出到调制器，以及自动回路增益校准电路，接收控制信号，以及根据控制信号的电压计算控制信号的当前增益，以补偿预加重滤波器和频率合成器之间的频率响应失配。

5. 发明申请

US20050156676A1 Synthesizer and calibrating method for the same 有权
标题翻译：合成仪和校准方法相同
公开(公告)号：US20050156676A1
公开(公告)日：2005-07-21
申请号：US11034484
申请日：2005-01-13
申请人： Chong-Ren Wang , Chao-Shi Chuang , Chung-Cheng Wang
发明人： Chong-Ren Wang , Chao-Shi Chuang , Chung-Cheng Wang
IPC分类号： H03L7/00 , H03L7/089 , H03L7/16 , H03L7/197
CPC分类号： H03L7/1976 , H03L7/0898
摘要： Synthesizer and calibrating method utilizing same. The frequency synthesizer modulates input signals comprising a phase locked loop circuit. The phase locked loop circuit comprises a phase frequency detector for generating a first signal, a low pass filter for outputting a filtered control signal derived from the received first signal, a voltage control oscillator for generating an output signal with a first frequency based on the control signal, a frequency divider dividing the first frequency for output to the input terminal of the phase frequency detector, a modulator coupled to the frequency divider, a pre-emphasis filter receiving and filtering the input signal for output to the modulator, and an auto loop gain calibration circuit, receiving the control signal, and calculating a current gain of the control signal in accordance with the voltage of the control signal to compensate for the frequency response mismatch between the pre-emphasis filter and the frequency synthesizer.
摘要翻译：合成器和校准方法利用它。频率合成器调制包括锁相环电路的输入信号。锁相环电路包括用于产生第一信号的相位频率检测器，用于输出从接收到的第一信号导出的经滤波的控制信号的低通滤波器，用于基于控制产生具有第一频率的输出信号的电压控制振荡器信号，将第一频率分频输出到相位频率检测器的输入端的分频器，耦合到分频器的调制器，预加重滤波器接收和滤波输入信号以输出到调制器，以及自动回路增益校准电路，接收控制信号，以及根据控制信号的电压计算控制信号的当前增益，以补偿预加重滤波器和频率合成器之间的频率响应失配。

6. 发明授权

US07301415B2 Automatic frequency tuning in a phase lock loop 有权
标题翻译：在锁相环中进行自动频率调谐
公开(公告)号：US07301415B2
公开(公告)日：2007-11-27
申请号：US11164924
申请日：2005-12-12
申请人： Chung-Cheng Wang , Chao-Shi Chuang , Wen-Shih Lu , Yu-Chang Chen
发明人： Chung-Cheng Wang , Chao-Shi Chuang , Wen-Shih Lu , Yu-Chang Chen
IPC分类号： H03B1/00
CPC分类号： H03L7/10
摘要： A method for automatic frequency tuning in a phase lock loop suitable for use in multi-band VCO wireless systems having very limited initial frequency lock times is disclosed. A predetermined subset of VCOs out of a larger bank of VCOs is selected to serve as interpolation points. The interpolation point VCOs are pre-calibrated with a predetermined voltage and the resultingly generated frequency for each of the interpolation point VCOs is stored into memory as a (frequency, VCO) pair, one pair for each interpolation point VCO. When a desired frequency then is given to the system, an appropriate VCO is selected by interpolation using the (frequency, VCO) pairs of the two most adjacent interpolation points for tracking and locking.
摘要翻译：公开了一种适用于具有非常有限的初始频率锁定时间的多频带VCO无线系统的锁相环中的自动频率调谐方法。选择较大的VCO组中的VCO的预定子集用作内插点。内插点VCO以预定电压进行预校准，并且每个内插点VCO的最终产生的频率作为（频率，VCO）对存储到存储器中，对于每个内插点VCO为一对。当给系统给出期望的频率时，通过使用用于跟踪和锁定的两个最相邻插值点的（频率，VCO）对进行插值来选择适当的VCO。

7. 发明授权

US07047146B2 Method for automatically calibrating the frequency range of a PLL and associated PLL capable of automatic calibration 失效
标题翻译：自动校准可自动校准的PLL和相关PLL的频率范围的方法
公开(公告)号：US07047146B2
公开(公告)日：2006-05-16
申请号：US10707519
申请日：2003-12-19
申请人： Chao-Shi Chuang , Chung-Cheng Wang , Wen-Shih Lu
发明人： Chao-Shi Chuang , Chung-Cheng Wang , Wen-Shih Lu
IPC分类号： G01R35/00 , G06F19/00
CPC分类号： H03L7/113 , H03L7/0891 , H03L7/099 , H03L7/199
摘要： A PLL includes a loop filter for accumulating charge to generate a loop-filter voltage and a VCO having a plurality of frequency ranges. The VCO receives the loop-filter voltage and generates an output signal having a frequency according to the loop-filter voltage and a currently selected VCO frequency range. During PLL calibration, the loop-filter is connected to a constant voltage source; the PLL feedback signal is synchronized with the reference signal; a linear search, a binary search, or a memory lookup is used to find a first and a second VCO frequency range; first and second time durations are measured for the time durations between the second rising edges of the reference signal and the PLL feedback signal for the two VCO frequency ranges, and the optimal VCO frequency range is determined by setting the VCO frequency range to be the VCO frequency range having the shortest measured time duration.
摘要翻译： PLL包括用于累积电荷以产生环路滤波器电压的环路滤波器和具有多个频率范围的VCO。 VCO接收环路滤波器电压，并产生具有根据环路滤波器电压和当前选择的VCO频率范围的频率的输出信号。在PLL校准期间，环路滤波器连接到恒定电压源; PLL反馈信号与参考信号同步; 使用线性搜索，二进制搜索或存储器查找来找到第一和第二VCO频率范围; 对于参考信号的第二上升沿和两个VCO频率范围的PLL反馈信号之间的持续时间测量第一和第二持续时间，并且通过将VCO频率范围设置为VCO来确定最佳VCO频率范围频率范围具有最短的测量持续时间。

8. 发明申请

US20070132517A1 Automatic Frequency Tuning in a Phase Lock Loop 有权
标题翻译：锁相环自动调频
公开(公告)号：US20070132517A1
公开(公告)日：2007-06-14
申请号：US11164924
申请日：2005-12-12
申请人： Chung-Cheng Wang , Chao-Shi Chuang , Wen-Shih Lu , Yu-Chang Chen
发明人： Chung-Cheng Wang , Chao-Shi Chuang , Wen-Shih Lu , Yu-Chang Chen
IPC分类号： H03L7/00
CPC分类号： H03L7/10
摘要： A method for automatic frequency tuning in a phase lock loop suitable for use in multi-band VCO wireless systems having very limited initial frequency lock times is disclosed. A predetermined subset of VCOs out of a larger bank of VCOs is selected to serve as interpolation points. The interpolation point VCOs are pre-calibrated with a predetermined voltage and the resultingly generated frequency for each of the interpolation point VCOs is stored into memory as a (frequency, VCO) pair, one pair for each interpolation point VCO. When a desired frequency then is given to the system, an appropriate VCO is selected by interpolation using the (frequency, VCO) pairs of the two most adjacent interpolation points for tracking and locking.
摘要翻译：公开了一种适用于具有非常有限的初始频率锁定时间的多频带VCO无线系统的锁相环中的自动频率调谐方法。选择较大的VCO组中的VCO的预定子集用作内插点。内插点VCO以预定电压进行预校准，并且每个内插点VCO的最终产生的频率作为（频率，VCO）对存储到存储器中，对于每个内插点VCO为一对。当给系统给出期望的频率时，通过使用用于跟踪和锁定的两个最相邻插值点的（频率，VCO）对进行插值来选择适当的VCO。

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