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1. 发明申请

US20070126060A1 SRAM cell with improved layout designs 有权
标题翻译：具有改进布局设计的SRAM单元
公开(公告)号：US20070126060A1
公开(公告)日：2007-06-07
申请号：US11293340
申请日：2005-12-02
申请人： Chun-Yi Lee , Huai-Ying Huang , Chii-Ming Wu
发明人： Chun-Yi Lee , Huai-Ying Huang , Chii-Ming Wu
IPC分类号： H01L27/12
CPC分类号： H01L27/1104 , H01L21/7624 , H01L21/84 , H01L27/11 , H01L27/1203 , Y10S257/903
摘要： A 6T SRAM cell includes a first inverter having a first pull-up transistor and a first pull-down transistor serially coupled between a supply source and a complementary supply source, and a second inverter cross-coupled with the first inverter having a second pull-up transistor and a second pull-down transistor serially coupled between the supply source and the complementary supply source. The cell further includes a first pass-gate and second pass-gate transistors coupled to the first and second inverters, respectively. The first pass-gate transistor and the first pull-up transistor are respectively constructed on a first P-type well and a first N-type well adjacent to one another, which are overlaid by a first doped region and a second doped region of substantially the same width in alignment with one another, respectively.
摘要翻译： 6T SRAM单元包括具有第一上拉晶体管和串联耦合在电源和互补电源之间的第一下拉晶体管的第一反相器，与第一反相器交叉耦合的第二反相器具有第二上拉电阻，串联耦合在电源和互补电源之间的第二下拉晶体管。该单元还包括分别耦合到第一和第二反相器的第一通过栅极和第二通过栅极晶体管。第一栅极晶体管和第一上拉晶体管分别构造在彼此相邻的第一P型阱和第一N型阱上，第一P型阱和第一N型阱被第一掺杂区域和基本上相同的宽度分别对准。

2. 发明授权

US07279755B2 SRAM cell with improved layout designs 有权
公开(公告)号：US07279755B2
公开(公告)日：2007-10-09
申请号：US11293340
申请日：2005-12-02
申请人： Chun-Yi Lee , Huai-Ying Huang , Chii-Ming M. Wu
发明人： Chun-Yi Lee , Huai-Ying Huang , Chii-Ming M. Wu
IPC分类号： H01L29/94 , G11C7/00
CPC分类号： H01L27/1104 , H01L21/7624 , H01L21/84 , H01L27/11 , H01L27/1203 , Y10S257/903
摘要： A 6T SRAM cell includes a first inverter having a first pull-up transistor and a first pull-down transistor serially coupled between a supply source and a complementary supply source, and a second inverter cross-coupled with the first inverter having a second pull-up transistor and a second pull-down transistor serially coupled between the supply source and the complementary supply source. The cell further includes a first pass-gate and second pass-gate transistors coupled to the first and second inverters, respectively. The first pass-gate transistor and the first pull-up transistor are respectively constructed on a first P-type well and a first N-type well adjacent to one another, which are overlaid by a first doped region and a second doped region of substantially the same width in alignment with one another, respectively.

3. 发明申请

US20130277750A1 Semiconductor Device and Method for Forming Same 有权
公开(公告)号：US20130277750A1
公开(公告)日：2013-10-24
申请号：US13451261
申请日：2012-04-19
申请人： Jui-Yao Lai , Chun-Yi Lee , Shyh-Wei Wang , Yen-Ming Chen
发明人： Jui-Yao Lai , Chun-Yi Lee , Shyh-Wei Wang , Yen-Ming Chen
IPC分类号： H01L27/06 , H01L27/08
CPC分类号： H01L28/24 , H01L21/823842 , H01L23/5228 , H01L27/0629 , H01L27/0802 , H01L28/20 , H01L29/0649 , H01L29/0847 , H01L2924/0002 , H01L2924/00
摘要： A system and method for forming a resistor system is provided. An embodiment comprises a resistor formed in a U-shape. The resistor may comprise multiple layers of conductive materials, with a dielectric layer filling the remainder of the U-shape. The resistor may be integrated with a dual metal gate manufacturing process or may be integrated with multiple types of resistors.

4. 发明申请

US20110297044A1 OLIGOANILINE EXFOLIATING AGENTS, EXFOLIATED PLATELET-SHAPED CLAY COMPRISING THE EXFOLIATING AGENT AND PREPARATION THEREOF 审中-公开
标题翻译：异氰脲酸衍生物，包含异构体的异型板形粘土及其制备
公开(公告)号：US20110297044A1
公开(公告)日：2011-12-08
申请号：US12951668
申请日：2010-11-22
申请人： Tsung-Yen TSAI , Chun-Yi Lee
发明人： Tsung-Yen TSAI , Chun-Yi Lee
IPC分类号： C04B14/00 , C07C211/54
CPC分类号： C04B14/206
摘要： In an embodiment, an oligoaniline exfoliating agent, as shown in Formula (I), is provided. In Formula (I), R is —H or —NH2, and n is 3 to 30. In another embodiment, exfoliated platelet-shaped clay including the oligoaniline exfoliating agent and a method for preparing the exfoliated platelet-shaped clay are provided.
摘要翻译：在一个实施方案中，提供如式（I）所示的寡苯胺去角质剂。在式（I）中，R为-H或-NH 2，n为3至30.在另一个实施方案中，提供了包含低聚苯胺去角质剂的剥离片状粘土和制备剥离的片状粘土的方法。

5. 发明授权

US08041912B2 Memory devices with data protection 有权
标题翻译：具有数据保护功能的内存设备
公开(公告)号：US08041912B2
公开(公告)日：2011-10-18
申请号：US11863254
申请日：2007-09-28
申请人： Yu-Lan Kuo , Chun-Yi Lee , Kuen-Long Chang , Chun-Hsiung Hung
发明人： Yu-Lan Kuo , Chun-Yi Lee , Kuen-Long Chang , Chun-Hsiung Hung
IPC分类号： G06F12/00
CPC分类号： G11C8/20 , G06F21/79 , G11C16/22
摘要： A memory device comprises a memory array, a status register coupled with the memory array, and a security register coupled with the memory array and the status register. The memory array contains a number of memory blocks configured to have independent access control. The status register includes at least one protection bit indicative of a write-protection status of at least one corresponding block of the memory blocks that corresponds to the protection bit. The security register includes at least one register-protection bit. The register-protection bit is programmable to a memory-protection state for preventing a state change of at least the protection bit of the status register. The register-protection bit is configured to remain in the memory-protection state until the resetting of the memory device.
摘要翻译：存储器件包括存储器阵列，与存储器阵列耦合的状态寄存器，以及与存储器阵列和状态寄存器耦合的安全寄存器。存储器阵列包含被配置为具有独立访问控制的多个存储器块。状态寄存器包括至少一个保护位，指示对应于保护位的存储器块的至少一个相应块的写保护状态。安全寄存器包括至少一个寄存器保护位。寄存器保护位可编程为存储器保护状态，以防止至少状态寄存器的保护位的状态改变。寄存器保护位被配置为保持存储器保护状态，直到存储器件的复位。

6. 发明授权

US08040734B2 Current-mode sense amplifying method 有权
标题翻译：电流模式感应放大法
公开(公告)号：US08040734B2
公开(公告)日：2011-10-18
申请号：US12767418
申请日：2010-04-26
申请人： Yung-Feng Lin , Chun-Yi Lee
发明人： Yung-Feng Lin , Chun-Yi Lee
IPC分类号： G11C11/34
CPC分类号： G11C7/062 , G11C7/067 , G11C7/08 , G11C16/28 , G11C2207/063
摘要： A sense amplifying method, applied in a memory having a memory cell and a reference cell, includes: charging the memory cell and the reference cell to have a cell current and a reference current, respectively; duplicating the cell current and the reference current to respectively generate a mirrored cell current via a first current path and a mirrored reference current via a second current path and equalizing a first voltage drop generated as the mirrored cell current flows by the first current path and a second voltage drop generated as the mirrored reference current flows by the second current path; and removing the equalization of the first voltage drop and the second voltage drop and adjusting first voltage drop and the second voltage drop according to a first current flowing by the first current path and a second current flowing by the second current path.
摘要翻译：应用于具有存储单元和参考单元的存储器中的感测放大方法包括：分别对存储单元和参考单元充电以具有单元电流和参考电流; 复制单元电流和参考电流以经由第二电流路径分别经由第一电流路径和镜像参考电流产生镜像单元电流，并且均衡由第一电流路径流动的镜像单元电流产生的第一电压降和当第二电流路径流过镜像参考电流时产生的第二电压降; 以及去除所述第一电压降和所述第二电压降的均衡，并且根据由所述第一电流路径流动的第一电流和由所述第二电流路径流动的第二电流来调节第一电压降和所述第二电压降。

7. 发明授权

US08035417B1 Output buffer circuit with variable drive strength 有权
标题翻译：具有可变驱动强度的输出缓冲电路
公开(公告)号：US08035417B1
公开(公告)日：2011-10-11
申请号：US12843452
申请日：2010-07-26
申请人： Chun-Hsiung Hung , Chun-Yi Lee
发明人： Chun-Hsiung Hung , Chun-Yi Lee
IPC分类号： H03K19/094
CPC分类号： H03K19/018521 , H03K19/018528
摘要： An output buffer circuit has a variable output drive strength, depending on a buffer enable signal. Multiple output buffer circuits have a variable combined output drive strength, depending on a set of buffer enable signals.
摘要翻译：根据缓冲器使能信号，输出缓冲电路具有可变的输出驱动强度。多个输出缓冲电路具有可变的组合输出驱动强度，这取决于一组缓冲器使能信号。

8. 发明授权

US07908469B2 Method for executing power on self test on a computer system and updating SMBIOS information partially 有权
标题翻译：在计算机系统上执行自检功能的方法，部分更新SMBIOS信息
公开(公告)号：US07908469B2
公开(公告)日：2011-03-15
申请号：US11985149
申请日：2007-11-13
申请人： Ling-Hung Yu , Ying-Chih Lu , Chun-Yi Lee , Chi-Tsung Chang , Meng-Hua Cheng , Chun-Lung Wu
发明人： Ling-Hung Yu , Ying-Chih Lu , Chun-Yi Lee , Chi-Tsung Chang , Meng-Hua Cheng , Chun-Lung Wu
IPC分类号： G06F9/00 , G06F9/44
CPC分类号： G06F9/4401 , G06F15/177
摘要： A method for executing the power on self test (POST) on the computer system and a method for updating the SMBIOS information partially are provided for a computer system with a first memory and a second memory, wherein the first memory comprises a first storage block and a second storage block. A user can previously set the specific SMBIOS information in the second storage block. And during the POST stage, the default SMBIOS information in the BIOS code loaded from the first storage block to the second memory will be partially updated according to the specific SMBIOS information set by the user. As a result, the purpose of using the appropriated SMBIOS information to initiate the computer system can be achieved.
摘要翻译：一种用于在计算机系统上执行电源自检（POST）的方法和部分地用于更新SMBIOS信息的方法被提供给具有第一存储器和第二存储器的计算机系统，其中第一存储器包括第一存储块和第二个存储块。用户可以预先在第二个存储块中设置特定的SMBIOS信息。在POST阶段，从第一个存储块加载到第二个存储器的BIOS代码中的默认SMBIOS信息将根据用户设置的特定SMBIOS信息进行部分更新。因此，可以实现使用专用的SMBIOS信息来启动计算机系统的目的。

9. 发明申请

US20100285643A1 Modifying Work Function in PMOS Devices by Counter-Doping 有权
标题翻译：通过反掺杂修改PMOS器件中的工作功能
公开(公告)号：US20100285643A1
公开(公告)日：2010-11-11
申请号：US12791656
申请日：2010-06-01
申请人： Chun-Yi Lee , Harry Chuang , Ping-Wei Wang , Kong-Beng Thei
发明人： Chun-Yi Lee , Harry Chuang , Ping-Wei Wang , Kong-Beng Thei
IPC分类号： H01L21/8238
CPC分类号： H01L27/0883 , G11C11/412 , H01L27/092 , H01L27/105 , H01L27/11 , H01L27/1104 , H01L27/1116 , H01L29/1083 , H01L29/165 , H01L29/6656 , H01L29/6659 , H01L29/66636 , H01L29/7833 , H01L29/7848 , Y10S438/919
摘要： A semiconductor structure comprising an SRAM/inverter cell and a method for forming the same are provided, wherein the SRAM/inverter cell has an improved write margin. The SRAM/inverter cell includes a pull-up PMOS device comprising a gate dielectric over the semiconductor substrate, a gate electrode on the gate dielectric wherein the gate electrode comprises a p-type impurity and an n-type impurity, and a stressor formed in a source/drain region. The device drive current of the pull-up PMOS device is reduced due to the counter-doping of the gate electrode.
摘要翻译：提供了包括SRAM /反相器单元的半导体结构及其形成方法，其中SRAM /反相器单元具有改善的写入裕度。 SRAM /反相器单元包括上拉PMOS器件，其包括半导体衬底上的栅极电介质，栅极电介质上的栅电极，其中栅电极包括p型杂质和n型杂质，以及形成在源极/漏极区域。上拉PMOS器件的器件驱动电流由于栅电极的反掺杂而降低。

10. 发明申请

US20080072029A1 Method for executing power on self test on a computer system and updating SMBIOS information partially 有权
标题翻译：在计算机系统上执行自检功能的方法，部分更新SMBIOS信息
公开(公告)号：US20080072029A1
公开(公告)日：2008-03-20
申请号：US11985149
申请日：2007-11-13
申请人： Ling-Hung Yu , Ying-Chih Lu , Chun-Yi Lee , Chi-Tsung Chang , Meng-Hua Cheng , Chun-Lung Wu
发明人： Ling-Hung Yu , Ying-Chih Lu , Chun-Yi Lee , Chi-Tsung Chang , Meng-Hua Cheng , Chun-Lung Wu
IPC分类号： G06F15/177
CPC分类号： G06F9/4401 , G06F15/177
摘要： A method for executing the power on self test (POST) on the computer system and a method for updating the SMBIOS information partially are provided for a computer system with a first memory and a second memory, wherein the first memory comprises a first storage block and a second storage block. A user can previously set the specific SMBIOS information in the second storage block. And during the POST stage, the default SMBIOS information in the BIOS code loaded from the first storage block to the second memory will be partially updated according to the specific SMBIOS information set by the user. As a result, the purpose of using the appropriated SMBIOS information to initiate the computer system can be achieved.
摘要翻译：一种用于在计算机系统上执行电源自检（POST）的方法和部分地用于更新SMBIOS信息的方法被提供给具有第一存储器和第二存储器的计算机系统，其中第一存储器包括第一存储块和第二个存储块。用户可以预先在第二个存储块中设置特定的SMBIOS信息。在POST阶段，从第一个存储块加载到第二个存储器的BIOS代码中的默认SMBIOS信息将根据用户设置的特定SMBIOS信息进行部分更新。因此，可以实现使用专用的SMBIOS信息来启动计算机系统的目的。

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