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1. 发明申请

US20130277750A1 Semiconductor Device and Method for Forming Same 有权
公开(公告)号：US20130277750A1
公开(公告)日：2013-10-24
申请号：US13451261
申请日：2012-04-19
申请人： Jui-Yao Lai , Chun-Yi Lee , Shyh-Wei Wang , Yen-Ming Chen
发明人： Jui-Yao Lai , Chun-Yi Lee , Shyh-Wei Wang , Yen-Ming Chen
IPC分类号： H01L27/06 , H01L27/08
CPC分类号： H01L28/24 , H01L21/823842 , H01L23/5228 , H01L27/0629 , H01L27/0802 , H01L28/20 , H01L29/0649 , H01L29/0847 , H01L2924/0002 , H01L2924/00
摘要： A system and method for forming a resistor system is provided. An embodiment comprises a resistor formed in a U-shape. The resistor may comprise multiple layers of conductive materials, with a dielectric layer filling the remainder of the U-shape. The resistor may be integrated with a dual metal gate manufacturing process or may be integrated with multiple types of resistors.

2. 发明授权

US08786025B2 Semiconductor device and method for forming same 有权
标题翻译：半导体器件及其形成方法
公开(公告)号：US08786025B2
公开(公告)日：2014-07-22
申请号：US13451261
申请日：2012-04-19
申请人： Jui-Yao Lai , Chun-Yi Lee , Shyh-Wei Wang , Yen-Ming Chen
发明人： Jui-Yao Lai , Chun-Yi Lee , Shyh-Wei Wang , Yen-Ming Chen
IPC分类号： H01L21/70
CPC分类号： H01L28/24 , H01L21/823842 , H01L23/5228 , H01L27/0629 , H01L27/0802 , H01L28/20 , H01L29/0649 , H01L29/0847 , H01L2924/0002 , H01L2924/00
摘要： A system and method for forming a resistor system is provided. An embodiment comprises a resistor formed in a U-shape. The resistor may comprise multiple layers of conductive materials, with a dielectric layer filling the remainder of the U-shape. The resistor may be integrated with a dual metal gate manufacturing process or may be integrated with multiple types of resistors.
摘要翻译：提供一种用于形成电阻系统的系统和方法。实施例包括形成为U形的电阻器。电阻器可以包括多层导电材料，其中介电层填充U形的其余部分。电阻器可以与双金属栅极制造工艺集成，或者可以与多种类型的电阻器集成。

3. 发明授权

US08853826B2 Methods and apparatus for bipolar junction transistors and resistors 有权
标题翻译：双极结晶体管和电阻器的方法和装置
公开(公告)号：US08853826B2
公开(公告)日：2014-10-07
申请号：US13471223
申请日：2012-05-14
申请人： Jui-Yao Lai , Shyh-Wei Wang , Yen-Ming Chen
发明人： Jui-Yao Lai , Shyh-Wei Wang , Yen-Ming Chen
IPC分类号： H01L21/02
CPC分类号： H01L29/737 , H01L21/265 , H01L21/283 , H01L29/0649 , H01L29/165 , H01L29/66166 , H01L29/66242 , H01L29/7378 , H01L29/8605
摘要： Methods and apparatus for bipolar junction transistors (BJTs) are disclosed. A BJT comprises a collector made of p-type semiconductor material, a base made of n-type well on the collector; and an emitter comprising a p+ region on the base and a SiGe layer on the p+ region. The BJT can be formed by providing a semiconductor substrate comprising a collector, a base on the collector, forming a sacrificial layer on the base, patterning a first photoresist on the sacrificial layer to expose an opening surrounded by a STI within the base; implanting a p-type material through the sacrificial layer into an area of the base, forming a p+ region from the p-type implant; forming a SiGe layer on the etched p+ region to form an emitter. The process can be shared with manufacturing a polysilicon transistor up through the step of patterning a first photoresist on the sacrificial layer.
摘要翻译：公开了双极结型晶体管（BJT）的方法和装置。 BJT包括由p型半导体材料制成的集电体，在集电体上由n型阱制成的基座; 以及发射极，其包括在基极上的p +区和p +区上的SiGe层。 BJT可以通过提供包括收集器，集电器上的基底，在基底上形成牺牲层的半导体衬底来形成，在牺牲层上图案化第一光致抗蚀剂以暴露由基底内的STI包围的开口; 将p型材料通过牺牲层注入到基底的区域中，从p型植入物形成p +区; 在蚀刻的p +区上形成SiGe层以形成发射极。通过在牺牲层上图案化第一光致抗蚀剂的步骤，可以共享制造多晶硅晶体管的过程。

4. 发明申请

US20130299944A1 Methods and Apparatus for Bipolar Junction Transistors and Resistors 有权
公开(公告)号：US20130299944A1
公开(公告)日：2013-11-14
申请号：US13471223
申请日：2012-05-14
申请人： Jui-Yao Lai , Shyh-Wei Wang , Yen-Ming Chen
发明人： Jui-Yao Lai , Shyh-Wei Wang , Yen-Ming Chen
IPC分类号： H01L29/735 , H01L21/331
CPC分类号： H01L29/737 , H01L21/265 , H01L21/283 , H01L29/0649 , H01L29/165 , H01L29/66166 , H01L29/66242 , H01L29/7378 , H01L29/8605
摘要： Methods and apparatus for bipolar junction transistors (BJTs) are disclosed. A BJT comprises a collector made of p-type semiconductor material, a base made of n-type well on the collector; and an emitter comprising a p+ region on the base and a SiGe layer on the p+ region. The BJT can be formed by providing a semiconductor substrate comprising a collector, a base on the collector, forming a sacrificial layer on the base, patterning a first photoresist on the sacrificial layer to expose an opening surrounded by a STI within the base; implanting a p-type material through the sacrificial layer into an area of the base, forming a p+ region from the p-type implant; forming a SiGe layer on the etched p+ region to form an emitter. The process can be shared with manufacturing a polysilicon transistor up through the step of patterning a first photoresist on the sacrificial layer.

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