专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US07029980B2 Method of manufacturing SOI template layer 有权
标题翻译：制造SOI模板层的方法
公开(公告)号：US07029980B2
公开(公告)日：2006-04-18
申请号：US10670928
申请日：2003-09-25
申请人： Chun-Li Liu , Marius K. Orlowski , Matthew W. Stoker , Philip J. Tobin , Mariam G. Sadaka , Alexander L. Barr , Bich-Yen Nguyen , Voon-Yew Thean , Shawn G. Thomas , Ted R. White
发明人： Chun-Li Liu , Marius K. Orlowski , Matthew W. Stoker , Philip J. Tobin , Mariam G. Sadaka , Alexander L. Barr , Bich-Yen Nguyen , Voon-Yew Thean , Shawn G. Thomas , Ted R. White
IPC分类号： H01L21/331
CPC分类号： H01L29/161 , H01L21/26506 , H01L21/823807 , H01L21/823878 , H01L21/84 , H01L29/1054 , Y10S438/933
摘要： A vacancy injecting process for injecting vacancies in template layer material of an SOI substrate. The template layer material has a crystalline structure that includes, in some embodiments, both germanium and silicon atoms. A strained silicon layer is then epitaxially grown on the template layer material with the beneficial effects that straining has on electron and hole mobility. The vacancy injecting process is performed to inject vacancies and germanium atoms into the crystalline structure wherein germanium atoms recombine with the vacancies. One embodiment, a nitridation process is performed to grow a nitride layer on the template layer material and consume silicon in a way that injects vacancies in the crystalline structure while also allowing germanium atoms to recombine with the vacancies. Other examples of a vacancy injecting processes include silicidation processes, oxynitridation processes, oxidation processes with a chloride bearing gas, or inert gas post bake processes subsequent to an oxidation process.
摘要翻译：用于在SOI衬底的模板层材料中注入空位的空位注入工艺。模板层材料具有在一些实施方案中包括锗和硅原子的晶体结构。然后在模板层材料上外延生长应变硅层，具有应力对电子和空穴迁移率的有益效果。进行空位注入处理以将空位和锗原子注入晶格结构中，其中锗原子与空位重新组合。一个实施方案中，进行氮化处理以在模板层材料上生长氮化物层，并以注入晶体结构中的空位并且还允许锗原子与空位复合的方式消耗硅。空位注入方法的其它实例包括硅化工艺，氧氮化工艺，含氯化物气体的氧化工艺或氧化工艺之后的惰性气体后烘烤工艺。

2. 发明授权

US07056778B2 Semiconductor layer formation 失效
标题翻译：半导体层形成
公开(公告)号：US07056778B2
公开(公告)日：2006-06-06
申请号：US10919784
申请日：2004-08-17
申请人： Chun-Li Liu , Mariam G. Sadaka , Alexander L. Barr , Bich-Yen Nguyen , Voon-Yew Thean , Shawn G. Thomas , Ted R. White , Qianghua Xie
发明人： Chun-Li Liu , Mariam G. Sadaka , Alexander L. Barr , Bich-Yen Nguyen , Voon-Yew Thean , Shawn G. Thomas , Ted R. White , Qianghua Xie
IPC分类号： H01L21/338
CPC分类号： H01L29/161 , H01L21/26506 , H01L21/823807 , H01L21/823878 , H01L21/84 , H01L29/1054 , Y10S438/933
摘要： A process for forming strained semiconductor layers. The process include flowing a chlorine bearing gas (e.g. hydrogen chloride, chlorine, carbon tetrachloride, and trichloroethane) over the wafer while heating the wafer. In one example, the chorine bearing gas is flowed during a condensation process on a semiconductor layer that is used as a template layer for forming a strain semiconductor layer (e.g. strain silicon). In other examples, the chlorine bearing gas is flowed during a post bake of the wafer after the condensation operation.
摘要翻译：一种形成应变半导体层的工艺。该方法包括在加热晶片的同时使含氯气体（例如氯化氢，氯气，四氯化碳和三氯乙烷）流过晶片。在一个实例中，在用作形成应变半导体层（例如应变硅）的模板层的半导体层上的冷凝过程中，含有轴承气体流动。在其他实例中，在冷凝操作之后，在晶片的后烘烤期间，含氯气体流动。

3. 发明授权

US07241647B2 Graded semiconductor layer 有权
标题翻译：分级半导体层
公开(公告)号：US07241647B2
公开(公告)日：2007-07-10
申请号：US10919952
申请日：2004-08-17
申请人： Mariam G. Sadaka , Shawn G. Thomas , Ted R. White , Chun-Li Liu , Alexander L. Barr , Bich-Yen Nguyen , Voon-Yew Thean
发明人： Mariam G. Sadaka , Shawn G. Thomas , Ted R. White , Chun-Li Liu , Alexander L. Barr , Bich-Yen Nguyen , Voon-Yew Thean
IPC分类号： H01L21/00
CPC分类号： H01L29/78687 , H01L29/1054 , H01L29/6659 , H01L29/66742
摘要： A process for forming a semiconductor device. The process includes forming a template layer for forming a layer of strained silicon. In one example a layer of graded silicon germanium is formed where the germanium is at a higher concentration at the lower portion and at a lower concentration at a top portion. When subject to a condensation process, the germanium of the top portion of the layer diffuses to a remaining portion of the silicon germanium layer. Because the silicon germanium layer has a higher concentration of germanium at lower portions, germanium pile up after condensation may be reduced at the upper portion of the remaining portion of the silicon germanium layer.
摘要翻译：一种形成半导体器件的方法。该方法包括形成用于形成应变硅层的模板层。在一个示例中，形成梯度硅锗层，其中锗在下部处具有较高的浓度，在顶部处的浓度较低。当进行冷凝处理时，层的顶部的锗扩散到硅锗层的剩余部分。由于硅锗层在下部具有较高的锗浓度，所以在硅锗层的剩余部分的上部可以减少在冷凝后堆积的锗。

4. 发明授权

US07282402B2 Method of making a dual strained channel semiconductor device 有权
标题翻译：制造双应变通道半导体器件的方法
公开(公告)号：US07282402B2
公开(公告)日：2007-10-16
申请号：US11093801
申请日：2005-03-30
申请人： Mariam G. Sadaka , Alexander L. Barr , Dejan Jovanovic , Bich-Yen Nguyen , Voon-Yew Thean , Shawn G. Thomas , Ted R. White
发明人： Mariam G. Sadaka , Alexander L. Barr , Dejan Jovanovic , Bich-Yen Nguyen , Voon-Yew Thean , Shawn G. Thomas , Ted R. White
IPC分类号： H01L21/8238 , H01L21/336
CPC分类号： H01L29/1054 , H01L21/823807 , H01L21/823878 , H01L21/84 , H01L27/1203
摘要： According to the embodiments to the present disclosure, the process of making a dual strained channel semiconductor device includes integrating strained Si and compressed SiGe with trench isolation for achieving a simultaneous NMOS and PMOS performance enhancement. As described herein, the integration of NMOS and PMOS can be implemented in several ways to achieve NMOS and PMOS channels compatible with shallow trench isolation.
摘要翻译：根据本公开的实施例，制造双应变通道半导体器件的过程包括将应变Si和压缩SiGe与沟槽隔离相集成，以实现同时的NMOS和PMOS性能增强。如本文所述，NMOS和PMOS的集成可以以几种方式实现，以实现与浅沟槽隔离兼容的NMOS和PMOS沟道。

5. 发明授权

US06831350B1 Semiconductor structure with different lattice constant materials and method for forming the same 有权
标题翻译：具有不同晶格常数材料的半导体结构及其形成方法
公开(公告)号：US06831350B1
公开(公告)日：2004-12-14
申请号：US10677844
申请日：2003-10-02
申请人： Chun-Li Liu , Alexander L. Barr , John M. Grant , Bich-Yen Nguyen , Marius K. Orlowski , Tab A. Stephens , Ted R. White , Shawn G. Thomas
发明人： Chun-Li Liu , Alexander L. Barr , John M. Grant , Bich-Yen Nguyen , Marius K. Orlowski , Tab A. Stephens , Ted R. White , Shawn G. Thomas
IPC分类号： H01L2930
CPC分类号： H01L29/1054 , H01L21/0237 , H01L21/02381 , H01L21/0245 , H01L21/02507 , H01L21/02532 , H01L21/02639 , H01L21/02647 , H01L29/04 , H01L29/665 , H01L29/7833
摘要： A semiconductor structure includes a substrate comprising a first relaxed semiconductor material with a first lattice constant. A semiconductor device layer overlies the substrate, wherein the semiconductor device layer includes a second relaxed semiconductor material with a second lattice constant different from the first lattice constant. In addition, a dielectric layer is interposed between the substrate and the semiconductor device layer, wherein the dielectric layer includes a programmed transition zone disposed within the dielectric layer for transitioning between the first lattice constant and the second lattice constant. The programmed transition zone includes a plurality of layers, adjoining ones of the plurality of layers having different lattice constants with one of the adjoining ones having a first thickness exceeding a first critical thickness required to form defects and another of the adjoining ones having a second thickness not exceeding a second critical thickness. Each adjoining layer of the plurality of layers forms an interface for promoting defects in the transition zone to migrate to and terminate on an edge of the programmed transition zone. A method of making the same is also disclosed.
摘要翻译：半导体结构包括具有第一晶格常数的第一松弛半导体材料的衬底。半导体器件层覆盖在衬底上，其中半导体器件层包括具有不同于第一晶格常数的第二晶格常数的第二松弛半导体材料。此外，介电层介于基板和半导体器件层之间，其中介电层包括设置在电介质层内的编程过渡区，用于在第一晶格常数和第二晶格常数之间转变。编程的过渡区域包括多个层，多个层中相邻的层具有不同的晶格常数，其中相邻的层之一具有超过形成缺陷所需的第一临界厚度的第一厚度，而另一层具有第二厚度不超过第二临界厚度。多个层中的每个相邻层形成用于促进过渡区中的缺陷迁移到并终止于编程的过渡区的边缘的界面。还公开了制备该方法的方法。

6. 发明申请

US20130233240A1 METHODS AND APPARATUSES FOR EPITAXIAL FILMS WITH HIGH GERMANIUM CONTENT 有权
标题翻译：具有高锗含量的外源膜的方法和装置
公开(公告)号：US20130233240A1
公开(公告)日：2013-09-12
申请号：US13413495
申请日：2012-03-06
申请人： Nyles W. Cody , Shawn G. Thomas
发明人： Nyles W. Cody , Shawn G. Thomas
IPC分类号： C30B23/02 , C23C16/455 , H01L21/205
CPC分类号： C23C16/0272 , C23C16/42 , C30B25/165 , C30B29/52 , H01L21/02381 , H01L21/0245 , H01L21/02532 , H01L21/0262
摘要： The present application relates to methods for depositing a smooth, germanium rich epitaxial film by introducing silylgermane as a source gas into a reactor at low temperatures. The epitaxial film can be strained and serve as an active layer, or relaxed and serve as a buffer layer. In addition to the silylgermane gas, a diluent is provided to modulate the percentage of germanium in a deposited germanium-containing film by varying the ratio of the silylgermane gas and the diluent. The ratios can be controlled by way of dilution levels in silylgermane storage containers and/or separate flow, and are selected to result in germanium concentration greater than 55 atomic % in deposited epitaxial silicon germanium films. The diluent can include a reducing gas such as hydrogen gas or an inert gas such as nitrogen gas. Reaction chambers are configured to introduce silylgermane and the diluent to deposit the silicon germanium epitaxial films.
摘要翻译：本申请涉及通过在低温下将作为源气体的甲硅烷基锗烷引入反应器中来沉积光滑的富锗外延膜的方法。外延膜可以被应变并用作活性层，或者松弛并用作缓冲层。除了甲硅烷基锗烷气体之外，提供稀释剂以通过改变甲硅烷基锗烷气体和稀释剂的比例来调节沉积的含锗膜中的锗的百分比。这些比例可以通过在甲硅烷基锗烷储存容器和/或单独流动中的稀释水平进行控制，并且被选择以在沉积的外延硅锗膜中导致大于55原子％的锗浓度。稀释剂可以包括还原气体如氢气或惰性气体如氮气。反应室被配置成引入甲硅烷基锗烷和稀释剂以沉积硅锗外延膜。

7. 发明申请

US20080149970A1 Multi-gated carbon nanotube field effect transistor 审中-公开
标题翻译：多门控碳纳米管场效应晶体管
公开(公告)号：US20080149970A1
公开(公告)日：2008-06-26
申请号：US11643434
申请日：2006-12-21
申请人： Shawn G. Thomas , Islamshah S. Amlani
发明人： Shawn G. Thomas , Islamshah S. Amlani
IPC分类号： H01L27/00 , H01L21/762
CPC分类号： H01L51/0554 , B82Y10/00 , H01L51/0048
摘要： A multiple, independent top gated field effect transistor having an improved electron injection and reduced gate induced barrier lowering effects, and a method that allows for the destruction of metallic carbon nanotubes positioned between the source and drain of a top multi-gate transistor are provided. The field effect transistor comprises at least one carbon nanotube (14) coupled between the first and second electrodes (16, 18) and a first gate material (24) formed over a portion of the at least one carbon nanotube (14) and spaced apart from the first and second electrodes (16, 18). A dielectric material (32) is conformally coated on the first and second electrodes (16, 18), the at least one carbon nanotube (14), and the first gate material (24). A second gate material (36) is conformally coated on the dielectric material (32). Other exemplary embodiments include one gate (24, 36), three gates (24, 46, 48), and three gates (24, 54, 56; and 24, 66) having the dielectric layer (52, 56; and 62, 64) portioned with different material characteristics.
摘要翻译：提供具有改进的电子注入和降低的栅极诱发的屏障降低效果的多重独立顶栅控场效应晶体管，以及允许位于顶多栅极晶体管的源极和漏极之间的金属碳纳米管的破坏的方法。场效应晶体管包括耦合在第一和第二电极（16,18）之间的至少一个碳纳米管（14）和形成在所述至少一个碳纳米管（14）的一部分上并间隔开的第一栅极材料（24）从第一和第二电极（16,18）。介电材料（32）共形地涂覆在第一和第二电极（16,18）上，至少一个碳纳米管（14）和第一栅极材料（24）。第二栅极材料（36）被共形地涂覆在电介质材料（32）上。其他示例性实施例包括具有电介质层（52,56;和62,64）的一个栅极（24,36），三个栅极（24,46,48）和三个栅极（24,54,56;和24,66））具有不同的材料特性。

8. 发明授权

US09127345B2 Methods for depositing an epitaxial silicon germanium layer having a germanium to silicon ratio greater than 1:1 using silylgermane and a diluent 有权
标题翻译：使用甲硅烷基锗烷和稀释剂沉积锗/硅比大于1:1的外延硅锗层的方法
公开(公告)号：US09127345B2
公开(公告)日：2015-09-08
申请号：US13413495
申请日：2012-03-06
申请人： Nyles W. Cody , Shawn G. Thomas
发明人： Nyles W. Cody , Shawn G. Thomas
IPC分类号： C30B25/16 , C23C16/02 , H01L21/02 , C30B29/52 , C23C16/42
CPC分类号： C23C16/0272 , C23C16/42 , C30B25/165 , C30B29/52 , H01L21/02381 , H01L21/0245 , H01L21/02532 , H01L21/0262
摘要： The present application relates to methods for depositing a smooth, germanium rich epitaxial film by introducing silylgermane as a source gas into a reactor at low temperatures. The epitaxial film can be strained and serve as an active layer, or relaxed and serve as a buffer layer. In addition to the silylgermane gas, a diluent is provided to modulate the percentage of germanium in a deposited germanium-containing film by varying the ratio of the silylgermane gas and the diluent. The ratios can be controlled by way of dilution levels in silylgermane storage containers and/or separate flow, and are selected to result in germanium concentration greater than 55 atomic % in deposited epitaxial silicon germanium films. The diluent can include a reducing gas such as hydrogen gas or an inert gas such as nitrogen gas. Reaction chambers are configured to introduce silylgermane and the diluent to deposit the silicon germanium epitaxial films.
摘要翻译：本申请涉及通过在低温下将作为源气体的甲硅烷基锗烷引入反应器中来沉积光滑的富锗外延膜的方法。外延膜可以被应变并用作活性层，或者松弛并用作缓冲层。除了甲硅烷基锗烷气体之外，提供稀释剂以通过改变甲硅烷基锗烷气体和稀释剂的比例来调节沉积的含锗膜中的锗的百分比。这些比例可以通过在甲硅烷基锗烷储存容器和/或单独流动中的稀释水平进行控制，并且被选择以在沉积的外延硅锗膜中导致大于55原子％的锗浓度。稀释剂可以包括还原气体如氢气或惰性气体如氮气。反应室被配置成引入甲硅烷基锗烷和稀释剂以沉积硅锗外延膜。

9. 发明申请

US20090095983A1 SEMICONDUCTOR DEVICE AND METHOD OF MAKING SAME 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：US20090095983A1
公开(公告)日：2009-04-16
申请号：US12176914
申请日：2008-07-21
申请人： Shawn G. Thomas , Thomas E. Zirkle
发明人： Shawn G. Thomas , Thomas E. Zirkle
IPC分类号： H01L29/80 , H01L29/737
CPC分类号： H01L29/7833 , H01L21/02381 , H01L21/0243 , H01L21/02532 , H01L21/02639 , H01L21/02658 , H01L21/822 , H01L27/0629 , H01L29/16
摘要： In one example embodiment, an integrated semiconductor circuit (400) is provided. The integrated circuit (400) comprises a substrate (430) comprising a first material and a first electronic device (455) comprising a first depressed region (415) within the substrate (430) and a set of first device contact locations (475) in a contact level (300). The integrated circuit (400) further comprises a second electronic device 450 comprising a set of second device contact locations (451) in the contact level (300) and a second material (420) in the first depressed (415) region having a lattice mismatch with the first material.
摘要翻译：在一个示例性实施例中，提供集成半导体电路（400）。集成电路（400）包括：衬底（430），包括第一材料和第一电子器件（455），第一电子器件（455）包括在衬底（430）内的第一凹陷区域（415）和一组第一器件接触位置（475）联系级别（300）。集成电路（400）还包括第二电子设备450，其包括接触电平（300）中的一组第二器件接触位置（451）和第一凹陷（415）区域中的具有晶格失配的第二材料（420）与第一种材料。

10. 发明授权

US11766046B1 Cake cutter 有权
公开(公告)号：US11766046B1
公开(公告)日：2023-09-26
申请号：US17581438
申请日：2022-01-21
申请人： Shawn G. Thomas
发明人： Shawn G. Thomas
IPC分类号： A21C15/04 , A47G21/04 , A47J43/28
CPC分类号： A21C15/04 , A47G21/045 , A47J43/288
摘要： A cake cutter includes a handle having an L-shaped blade extending therefrom. The blade includes a first section axially extending from an end of the handle and a second section perpendicularly extending from a distal end of the first section. Integrally molded with a central portion of each blade section is a raised ridge that is positioned a predetermined distance from either end of the blade section. Accordingly, the user can cut a precisely sized slice of cake or casserole by aligning the ridges with an outer edge of a cake.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式