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1. 发明授权

US6069782A ESD damage protection using a clamp circuit 有权
标题翻译：使用钳位电路进行ESD损坏保护
公开(公告)号：US6069782A
公开(公告)日：2000-05-30
申请号：US140619
申请日：1998-08-26
申请人： Chuen-Der Lien , Tak Kwong Wong , Tzong-Kwang Yeh
发明人： Chuen-Der Lien , Tak Kwong Wong , Tzong-Kwang Yeh
IPC分类号： H01L27/02 , H02H9/00
CPC分类号： H01L27/0248
摘要： A circuit for protecting the internal circuitry of a semiconductor chip from increased power supply voltages due to electrostatic discharge events is presented. The circuit comprises a trigger circuit including a resistor and diode array coupled between a power line and a ground line and a discharge circuit which, when turned on by an output signal of the trigger circuit, conducts the excess charge on the power line to ground.
摘要翻译：提出了一种用于保护半导体芯片的内部电路免受由于静电放电事件引起的电源电压的电路。该电路包括触发电路，该触发电路包括耦合在电力线和地线之间的电阻器和二极管阵列，以及放电电路，当触发电路的输出信号导通时，放电电路将电力线上的过量电荷传导到地。

2. 发明授权

US07414460B1 System and method for integrated circuit charge recycling 有权
标题翻译：集成电路充电回收系统及方法
公开(公告)号：US07414460B1
公开(公告)日：2008-08-19
申请号：US11395061
申请日：2006-03-31
申请人： Chuen-Der Lien , Chau-Chin Wu , Tzong-Kwang Yeh
发明人： Chuen-Der Lien , Chau-Chin Wu , Tzong-Kwang Yeh
IPC分类号： G05F3/02
CPC分类号： H02M3/07
摘要： A charge recycling integrated circuit and a method for integrated circuit charge recycling. In one aspect, a charge storage collector is interposed between a high voltage supply or a low voltage supply and a function block of the integrated circuit. The charge collector is operable to selectively store a charge dissipated in the function block when the logic circuitry of the function block switches between a high voltage value and a low voltage value. The dissipated charge resulting from the switching in the logic circuitry of the function block is selectively stored to the charge collector and the charge collector selectively returns the charge stored on the charge collector to the high voltage supply, the low voltage supply or to another node in the integrated circuit as appropriate.
摘要翻译：电荷回收集成电路和集成电路充电回收方法。在一个方面，电荷存储收集器介于高压电源或低压电源和集成电路的功能块之间。当功能块的逻辑电路在高电压值和低电压值之间切换时，电荷收集器可操作以选择性地存储消耗在功能块中的电荷。由功能块的逻辑电路中的开关导致的耗散电荷被选择性地存储到电荷收集器中，并且电荷收集器选择性地将存储在电荷收集器上的电荷返回到高电压源，低电压电源或另一个节点集成电路适当。

3. 发明申请

US20060028860A1 Memory array bit line coupling capacitor cancellation 有权
标题翻译：存储阵列位线耦合电容器取消
公开(公告)号：US20060028860A1
公开(公告)日：2006-02-09
申请号：US10997708
申请日：2004-11-23
申请人： Chuen-Der Lien , Tzong-Kwang Yeh
发明人： Chuen-Der Lien , Tzong-Kwang Yeh
IPC分类号： G11C11/00
CPC分类号： G11C8/16 , G11C5/063 , G11C7/02 , G11C7/12 , G11C11/419
摘要： Capacitive coupling correction circuits are coupled between adjacent parallel dynamic (pre-charged) or static conductors. The capacitive coupling correction circuits effectively isolate a low voltage applied to a first conductor from a high pre-charged voltage stored on an adjacent second conductor (or vice versa). The adjacent parallel conductors can be bit lines of a memory cell. Each capacitive coupling correction circuit can include an inverter having an input terminal coupled to the first conductor, and an output terminal coupled to a first plate of a capacitor. A second plate of the capacitor is coupled to the second conductor. The capacitance of the capacitor is selected to be identical to a parasitic capacitance between the first and second conductors. As a result, there is a zero net voltage effect between the first and second conductors. The capacitive coupling correction circuits may be distributed along the length of the first and second conductors.
摘要翻译：电容耦合校正电路耦合在相邻的并联动态（预充电）或静态导体之间。电容耦合校正电路有效地将施加到第一导体的低电压与存储在相邻的第二导体上的高预充电电压隔离（反之亦然）。相邻的平行导体可以是存储单元的位线。每个电容耦合校正电路可以包括具有耦合到第一导体的输入端的反相器和耦合到电容器的第一板的输出端。电容器的第二板耦合到第二导体。电容器的电容被选择为与第一和第二导体之间的寄生电容相同。结果，在第一和第二导体之间存在零净电压效应。电容耦合校正电路可以沿着第一和第二导体的长度分布。

4. 发明授权

US07941723B1 Clock generator and method for providing reliable clock signal using array of MEMS resonators 有权
标题翻译：时钟发生器和使用MEMS谐振器阵列提供可靠时钟信号的方法
公开(公告)号：US07941723B1
公开(公告)日：2011-05-10
申请号：US11861869
申请日：2007-09-26
申请人： Chuen-Der Lien , Jimmy Lee
发明人： Chuen-Der Lien , Jimmy Lee
IPC分类号： G01R31/3181 , G01R31/40
CPC分类号： G01R31/31702 , G01R31/31727 , H03B5/32
摘要： A clock generator is disclosed that includes an array of MEMS resonators and a test circuit. The test circuit is operable at start-up to operate one or more of the MEMS resonators to generate test output and analyze the test output to determine whether the operated MEMS resonators meet test criteria. A MEMS resonator is selected that meets the test criteria and its output is used to generate an output clock signal. In addition, the test circuit is operable to analyze the output of the selected MEMS resonator and select a replacement MEMS resonator when the output of the selected MEMS resonator no longer meets the test criteria. The replacement MEMS resonator is then operated and its output is coupled to the output of the clock generator. Thereby, failing and potentially failing MEMS resonators are automatically replaced during operation of the clock generator in its end-use application.
摘要翻译：公开了一种包括MEMS谐振器阵列和测试电路的时钟发生器。测试电路在启动时可操作以操作一个或多个MEMS谐振器以产生测试输出并分析测试输出以确定所操作的MEMS谐振器是否符合测试标准。选择符合测试标准的MEMS谐振器，并且其输出用于产生输出时钟信号。另外，当选择的MEMS谐振器的输出不再满足测试标准时，测试电路可操作以分析所选择的MEMS谐振器的输出并选择替换的MEMS谐振器。然后更换MEMS谐振器，并将其输出耦合到时钟发生器的输出端。因此，在其最终用途应用中的时钟发生器的操作期间，故障和潜在故障的MEMS谐振器被自动替换。

5. 发明授权

US07522438B1 Method and apparatus for CAM with reduced cross-coupling interference 有权
公开(公告)号：US07522438B1
公开(公告)日：2009-04-21
申请号：US11931573
申请日：2007-10-31
申请人： Chuen-Der Lien , Chau-Chin Wu
发明人： Chuen-Der Lien , Chau-Chin Wu
IPC分类号： G11C15/00
CPC分类号： G11C15/04 , G11C7/02
摘要： A method and apparatus for a CAM with reduced cross-coupling interference have been disclosed.

6. 发明授权

US07187571B1 Method and apparatus for CAM with reduced cross-coupling interference 有权
标题翻译：具有降低的交叉耦合干扰的CAM的方法和装置
公开(公告)号：US07187571B1
公开(公告)日：2007-03-06
申请号：US10821601
申请日：2004-04-09
申请人： Chuen-Der Lien , Chau-Chin Wu
发明人： Chuen-Der Lien , Chau-Chin Wu
IPC分类号： G11C15/00 , G11C7/00
CPC分类号： G11C15/04 , G11C7/02
摘要： A method and apparatus for a CAM with reduced cross-coupling interference have been disclosed.
摘要翻译：已经公开了一种具有减小的交叉耦合干扰的CAM的方法和装置。

7. 发明授权

US06879504B1 Content addressable memory (CAM) devices having error detection and correction control circuits therein and methods of operating same 有权
标题翻译：具有错误检测和校正控制电路的内容可寻址存储器（CAM）装置及其操作方法
公开(公告)号：US06879504B1
公开(公告)日：2005-04-12
申请号：US10619638
申请日：2003-07-15
申请人： Chuen-Der Lien , Kee Park , Chau-Chin Wu , Mark Baumann
发明人： Chuen-Der Lien , Kee Park , Chau-Chin Wu , Mark Baumann
IPC分类号： G11C7/02 , G11C11/412 , G11C15/04 , G11C15/00
CPC分类号： G11C15/04 , G11C11/4125 , G11C15/043 , G11C15/046
摘要： Content addressable memory (CAM) devices include error detection and correction (EDC) control circuits therein. The EDC control circuit operates to correct soft errors in entries within a plurality of internal CAM array blocks with, at most, limited interruption to other operations performed by the CAM device. The EDC control circuit utilizes a multi-bit check word associated with each entry to detect a soft error and perform one-bit error correction on the entry. The EDC control circuit is configured to be active during a background mode of operation when the CAM array blocks are undergoing search operations in a foreground mode of operation. A CAM array block may also include a column of dual-function check bit cells that are configured to operate as a column of CAM cells when necessary to replace a defective column of CAM cells.
摘要翻译：内容可寻址存储器（CAM）装置包括其中的错误检测和校正（EDC）控制电路。 EDC控制电路用于校正多个内部CAM阵列块内的条目中的软错误，最多限制中断由CAM设备执行的其他操作。 EDC控制电路利用与每个条目相关联的多位检查字来检测软错误，并在条目上执行一位错误校正。当CAM阵列块在前台操作模式下正在进行搜索操作时，EDC控制电路被配置为在后台操作模式期间有效。 CAM阵列块还可以包括一列双功能校验位单元，其被配置为当需要更换CAM单元的缺陷列时作为CAM单元的列进行操作。

8. 发明授权

US06700827B2 Cam circuit with error correction 失效
标题翻译：具有误差校正的凸轮电路
公开(公告)号：US06700827B2
公开(公告)日：2004-03-02
申请号：US10226512
申请日：2002-08-23
申请人： Chuen-Der Lien , Michael J. Miller
发明人： Chuen-Der Lien , Michael J. Miller
IPC分类号： G11C1500
CPC分类号： G11C15/04 , G11C11/4125 , G11C15/043 , G11C15/046
摘要： A CAM circuit including a RAM array, a CAM array, a control/interface circuit, and an error detection and correction (EDC) circuit. The control/interface circuit systematically writes data from the RAM array to the CAM array, thereby preventing soft errors by continually refreshing data stored in the CAM array. The RAM array also stores check bits for each data word that can be generated by the EDC circuit when the data words are initially written to the CAM circuit. During the refresh operation, data words and associated check bits are read from the RAM array and transmitted to the EDC circuit. The EDC circuit analyzes each data word and associated check bits to detect errors, and corrects the data word, if necessary, before sending the data word to the CAM array.
摘要翻译：包括RAM阵列，CAM阵列，控制/接口电路和错误检测和校正（EDC）电路的CAM电路。控制/接口电路系统地将数据从RAM阵列写入CAM阵列，从而通过持续刷新存储在CAM阵列中的数据来防止软错误。当数据字最初写入CAM电路时，RAM阵列还存储可由EDC电路产生的每个数据字的校验位。在刷新操作期间，从RAM阵列读取数据字和相关的校验位，并发送到EDC电路。 EDC电路分析每个数据字和相关的检查位以检测错误，如果需要，在将数据字发送到CAM阵列之前校正数据字。

9. 发明授权

US06563754B1 DRAM circuit with separate refresh memory 有权
标题翻译： DRAM电路具有单独的刷新存储器
公开(公告)号：US06563754B1
公开(公告)日：2003-05-13
申请号：US09781524
申请日：2001-02-08
申请人： Chuen-Der Lien , Chau-Chin Wu
发明人： Chuen-Der Lien , Chau-Chin Wu
IPC分类号： G11C700
CPC分类号： G11C11/4125 , G11C15/04 , G11C15/043 , G11C15/046
摘要： A DRAM circuit including a first DRAM array used solely for refresh operations, and the second DRAM array for performing logic operations that is refreshed using data read from the first DRAM array. Specifically, data is read only from the first DRAM array during a read phase of the refresh operation, and is written to both the first DRAM array and the second DRAM array during the write phase of the refresh operation. Accordingly, the second DRAM array is able to simultaneously perform any type of logic operation without delay or disturbance caused by accessing the second DRAM array during the read phase. In one embodiment, the second DRAM array includes DRAM CAM cells that perform data matching operations using the data refreshed from the first DRAM array, which includes conventional DRAM memory cells. During read operations, because the data values stored in the first DRAM array and the second DRAM array are identical, data values are read from the conventional DRAM memory cells of the first DRAM array, instead of from the DRAM CAM cells.
摘要翻译：包括仅用于刷新操作的第一DRAM阵列的DRAM电路和用于执行使用从第一DRAM阵列读取的数据刷新的逻辑运算的第二DRAM阵列。具体地说，在刷新操作的读取阶段期间，数据仅从第一DRAM阵列读取，并且在刷新操作的写入阶段被写入第一DRAM阵列和第二DRAM阵列。因此，第二DRAM阵列能够在读取阶段期间同时执行任何类型的逻辑运算，而不会由于访问第二DRAM阵列而引起延迟或干扰。在一个实施例中，第二DRAM阵列包括使用从包括常规DRAM存储器单元的第一DRAM阵列刷新的数据执行数据匹配操作的DRAM CAM单元。在读取操作期间，由于存储在第一DRAM阵列和第二DRAM阵列中的数据值相同，所以从第一DRAM阵列的常规DRAM存储单元而不是从DRAM CAM单元读取数据值。

10. 发明授权

US06470418B1 Pipelining a content addressable memory cell array for low-power operation 有权
标题翻译：内置可寻址存储单元阵列，用于低功耗操作
公开(公告)号：US06470418B1
公开(公告)日：2002-10-22
申请号：US09232413
申请日：1999-01-15
申请人： Chuen-Der Lien , Chau-Chin Wu , John R. Mick
发明人： Chuen-Der Lien , Chau-Chin Wu , John R. Mick
IPC分类号： G06F1200
CPC分类号： G06F17/30982 , G11C7/1039 , G11C15/00
摘要： A content addressable memory (CAM) system that includes first and second CAM arrays, which generate first and second sets of match control signals, respectively, having higher and lower priorities, respectively. The first CAM array is enabled during a first memory cycle, and the first set of match control signals are analyzed. If a match exists in the first CAM array, a first priority encoder is enabled to process the first set of match control signals. If no match exists, the first priority encoder is not enabled, and a second memory cycle is initiated. The second CAM array is enabled during the second memory cycle, and the second set of signals is analyzed. If a match exists in the second CAM array, a second priority encoder is enabled to process the second set of match control signals. If no match exists, the second priority encoder is not enabled.
摘要翻译：一种内容寻址存储器（CAM）系统，其包括分别产生具有较高和较低优先级的第一和第二组匹配控制信号的第一和第二CAM阵列。第一个CAM阵列在第一个存储器周期中被使能，并且分析第一组匹配控制信号。如果在第一CAM阵列中存在匹配，则使能第一优先级编码器来处理第一组匹配控制信号。如果不存在匹配，则不启用第一优先级编码器，并且启动第二存储器周期。第二个CAM阵列在第二个存储周期中被使能，第二组信号被分析。如果在第二CAM阵列中存在匹配，则使能第二优先级编码器来处理第二组匹配控制信号。如果不存在匹配，则不启用第二优先级编码器。

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