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1. 发明申请

US20090187779A1 AUTOMATIC POWER MANAGEMENT METHOD 审中-公开
标题翻译：自动电源管理方法
公开(公告)号：US20090187779A1
公开(公告)日：2009-07-23
申请号：US12016272
申请日：2008-01-18
申请人： Chuan Liu , Chien-Hsun Tung , Jeng-Horng Tsai
发明人： Chuan Liu , Chien-Hsun Tung , Jeng-Horng Tsai
IPC分类号： G06F1/32
CPC分类号： G06F1/3268 , G06F1/3221 , G06F1/3228 , G06F3/0625 , G06F3/0659 , G06F3/0676 , Y02D10/154 , Y02D50/20
摘要： The application discloses methods applied to an electronic system capable of operating in a non power saving mode and a power saving mode. According to one of the methods, the idle time when the electronic system is idle in the non-power saving mode is measured. If the idle time equals or exceeds a mode entry time, the electronic system enters the power saving mode. The power down duration when the electronic system stays in the power saving mode is measured. The mode entry time is then modified based upon the power down duration.
摘要翻译：本申请公开了应用于能够以非节电模式和省电模式操作的电子系统的方法。根据这些方法之一，测量电子系统处于非节电模式时空闲的空闲时间。如果空闲时间等于或超过模式进入时间，则电子系统进入省电模式。测量电子系统处于省电模式时的断电持续时间。然后基于断电持续时间修改模式输入时间。

2. 发明授权

US07272673B2 Signal generating circuit capable of generating a validation signal and related method thereof 有权
标题翻译：能产生验证信号的信号发生电路及其相关方法
公开(公告)号：US07272673B2
公开(公告)日：2007-09-18
申请号：US11163899
申请日：2005-11-03
申请人： Chuan Liu , Chuan-Cheng Hsiao , Jeng-Horng Tsai
发明人： Chuan Liu , Chuan-Cheng Hsiao , Jeng-Horng Tsai
IPC分类号： G06F3/00
CPC分类号： G06F13/385
摘要： A signal generating system for generating a validation signal includes: a phase lock loop (PLL) for locking an output clock to a specific clock frequency; and a digital signal generation circuit. The digital signal generating circuit includes: a triggering circuit, electrically coupled to the PLL, for determining whether the output clock of the PLL is in a frequency range, and outputting a triggering signal if the output clock is in a frequency range; and a signal generating device, electrically coupled to the triggering circuit and the PLL, for generating the validation signal according to the output clock when receiving the triggering signal; wherein before the output clock is in the frequency range, the PLL continuously outputs the output clock.
摘要翻译：用于产生确认信号的信号发生系统包括：用于将输出时钟锁定到特定时钟频率的锁相环（PLL）; 和数字信号发生电路。数字信号发生电路包括：电耦合到PLL的用于确定PLL的输出时钟是否在频率范围内的触发电路，以及如果输出时钟在频率范围内则输出触发信号; 以及信号发生装置，电耦合到所述触发电路和所述PLL，用于当接收到所述触发信号时根据所述输出时钟产生所述有效信号; 其中在输出时钟处于频率范围之前，PLL连续输出输出时钟。

3. 发明授权

US07612589B2 Phase-locked loop and control method utilizing the same 有权
标题翻译：锁相环及其控制方法
公开(公告)号：US07612589B2
公开(公告)日：2009-11-03
申请号：US11871223
申请日：2007-10-12
申请人： Chuan Liu , Chuan-Cheng Hsiao , Jeng-Horng Tsai
发明人： Chuan Liu , Chuan-Cheng Hsiao , Jeng-Horng Tsai
IPC分类号： H03L7/06
CPC分类号： H03L7/099 , H03L7/10 , H03L2207/06
摘要： A phase-locked loop includes a processing unit, a voltage-controlled oscillator, and a control unit. The processing unit generates a control voltage to a node according to a phase difference between a reference clock and a first feedback clock. The voltage-controlled oscillator generates the first feedback clock according to a voltage of the node. The control unit deactivates the voltage-controlled oscillator and provides a start voltage to the node in a power-down mode, and activates the voltage-controlled oscillator to generate the first feedback clock according to the voltage of the node in a power-on mode. The control unit stops providing the start voltage in the power-on mode.
摘要翻译：锁相环包括处理单元，压控振荡器和控制单元。处理单元根据参考时钟和第一反馈时钟之间的相位差，向节点生成控制电压。压控振荡器根据节点的电压产生第一反馈时钟。控制单元停用压控振荡器，并以断电模式向节点提供启动电压，并且启动压控振荡器以根据在加电模式下的节点的电压产生第一反馈时钟。控制单元在通电模式下停止提供启动电压。

4. 发明授权

US07865803B2 Method for processing noise interference in data accessing device with serial advanced technology attachment (SATA) interface 有权
标题翻译：用串行高级技术附件（SATA）接口处理数据存取设备中的噪声干扰的方法
公开(公告)号：US07865803B2
公开(公告)日：2011-01-04
申请号：US12574925
申请日：2009-10-07
申请人： Chuan Liu , Jeng-Horng Tsai
发明人： Chuan Liu , Jeng-Horng Tsai
IPC分类号： H03M13/00
CPC分类号： G06F13/387 , G06F11/0727 , G06F11/0772 , H04L1/1607
摘要： A method for processing noise interference in a serial AT Attachment (SATA) interface. In the method, when a receiver does not receive a SOF primitive (start of frame primitive) but does receive an EOF primitive (end of frame primitive) or WTRM primitive (wait for frame termination primitive), the receiver outputs a R_OK primitive (reception with no error primitive) and sets a error flag to report to the application layer of the receiver to eliminate the interference.
摘要翻译：一种用于处理串行AT附件（SATA）接口中噪声干扰的方法。在该方法中，当接收机没有接收到SOF原语（帧原语开始），但是接收到EOF原语（帧原语结束）或WTRM原语（等待帧终止原语）时，接收机输出R_OK原语（接收没有错误原语），并设置一个错误标志来报告接收器的应用层以消除干扰。

5. 发明申请

US20090296869A1 COMMUNICATION SYSTEMS, CLOCK GENERATION CIRCUITS THEREOF, AND METHOD FOR GENERATING CLOCK SIGNAL 有权
标题翻译：通信系统，其产生电路及其产生时钟信号的方法
公开(公告)号：US20090296869A1
公开(公告)日：2009-12-03
申请号：US12407226
申请日：2009-03-19
申请人： Kuan-Hua Chao , Shiue-Shin Liu , Jeng-Horng Tsai , Chih-Ching Chen , Chuan Liu , Tse-Hsiang Hsu
发明人： Kuan-Hua Chao , Shiue-Shin Liu , Jeng-Horng Tsai , Chih-Ching Chen , Chuan Liu , Tse-Hsiang Hsu
IPC分类号： H04L7/00 , H03L7/06
CPC分类号： H03L7/081 , H03L7/087 , H03L7/1974
摘要： A clock generation circuit is provided and includes a phase locked loop (PLL) and a calibrator. The PLL is arranged to receive a first clock signal and generate the output clock signal. The PLL adjusts the frequency of the output clock signal according to a control signal. The calibrator is arranged to receive the output clock signal and a second clock signal, execute a frequency calibration between the output clock signal and the second clock signal, and generate the control signal according to results of the frequency calibration.
摘要翻译：提供时钟发生电路并且包括锁相环（PLL）和校准器。 PLL被布置成接收第一时钟信号并产生输出时钟信号。 PLL根据控制信号调节输出时钟信号的频率。校准器被布置成接收输出时钟信号和第二时钟信号，在输出时钟信号和第二时钟信号之间执行频率校准，并根据频率校准的结果产生控制信号。

6. 发明申请

US20090096496A1 PHASE-LOCKED LOOP AND CONTROL METHOD UTILIZING THE SAME 有权
标题翻译：使用相位锁相环和控制方法
公开(公告)号：US20090096496A1
公开(公告)日：2009-04-16
申请号：US11871223
申请日：2007-10-12
申请人： Chuan Liu , Chuan-Cheng Hsiao , Jeng-Horng Tsai
发明人： Chuan Liu , Chuan-Cheng Hsiao , Jeng-Horng Tsai
IPC分类号： H03L7/06
CPC分类号： H03L7/099 , H03L7/10 , H03L2207/06
摘要： A phase-locked loop includes a processing unit, a voltage-controlled oscillator, and a control unit. The processing unit generates a control voltage to a node according to a phase difference between a reference clock and a first feedback clock. The voltage-controlled oscillator generates the first feedback clock according to a voltage of the node. The control unit deactivates the voltage-controlled oscillator and provides a start voltage to the node in a power-down mode, and activates the voltage-controlled oscillator to generate the first feedback clock according to the voltage of the node in a power-on mode. The control unit stops providing the start voltage in the power-on mode.
摘要翻译：锁相环包括处理单元，压控振荡器和控制单元。处理单元根据参考时钟和第一反馈时钟之间的相位差，向节点生成控制电压。压控振荡器根据节点的电压产生第一反馈时钟。控制单元停用压控振荡器，并以断电模式向节点提供启动电压，并且启动压控振荡器以根据在加电模式下的节点的电压产生第一反馈时钟。控制单元在通电模式下停止提供启动电压。

7. 发明申请

US20070096837A1 SIGNAL GENERATING CIRCUIT CAPABLE OF GENERATING A VALIDATION SIGNAL AND RELATED METHOD THEREOF 有权
标题翻译：产生有效信号的信号发生电路及其相关方法
公开(公告)号：US20070096837A1
公开(公告)日：2007-05-03
申请号：US11163899
申请日：2005-11-03
申请人： Chuan Liu , Chuan-Cheng Hsiao , Jeng-Horng Tsai
发明人： Chuan Liu , Chuan-Cheng Hsiao , Jeng-Horng Tsai
IPC分类号： H03B1/00
CPC分类号： G06F13/385
摘要： A signal generating system for generating a validation signal includes: a phase lock loop (PLL) for locking an output clock to a specific clock frequency; and a digital signal generation circuit. The digital signal generating circuit includes: a triggering circuit, electrically coupled to the PLL, for determining whether the output clock of the PLL is in a frequency range, and outputting a triggering signal if the output clock is in a frequency range; and a signal generating device, electrically coupled to the triggering circuit and the PLL, for generating the validation signal according to the output clock when receiving the triggering signal; wherein before the output clock is in the frequency range, the PLL continuously outputs the output clock.
摘要翻译：用于产生确认信号的信号发生系统包括：用于将输出时钟锁定到特定时钟频率的锁相环（PLL）; 和数字信号发生电路。数字信号发生电路包括：电耦合到PLL的用于确定PLL的输出时钟是否在频率范围内的触发电路，以及如果输出时钟在频率范围内则输出触发信号; 以及信号发生装置，电耦合到所述触发电路和所述PLL，用于当接收到所述触发信号时根据所述输出时钟产生所述有效信号; 其中在输出时钟处于频率范围之前，PLL连续输出输出时钟。

8. 发明授权

US08451971B2 Communication systems, clock generation circuits thereof, and method for generating clock signal 有权
标题翻译：通信系统，其时钟生成电路以及用于产生时钟信号的方法
公开(公告)号：US08451971B2
公开(公告)日：2013-05-28
申请号：US12407226
申请日：2009-03-19
申请人： Kuan-Hua Chao , Shiue-Shin Liu , Jeng-Horng Tsai , Chih-Ching Chen , Chuan Liu , Tse-Hsiang Hsu
发明人： Kuan-Hua Chao , Shiue-Shin Liu , Jeng-Horng Tsai , Chih-Ching Chen , Chuan Liu , Tse-Hsiang Hsu
IPC分类号： H04L7/00 , H03L7/06
CPC分类号： H03L7/081 , H03L7/087 , H03L7/1974
摘要： A clock generation circuit is provided and includes a phase locked loop (PLL) and a calibrator. The PLL is arranged to receive a first clock signal and generate the output clock signal. The PLL adjusts the frequency of the output clock signal according to a control signal. The calibrator is arranged to receive the output clock signal and a second clock signal, execute a frequency calibration between the output clock signal and the second clock signal, and generate the control signal according to results of the frequency calibration.
摘要翻译：提供时钟发生电路并且包括锁相环（PLL）和校准器。 PLL被布置成接收第一时钟信号并产生输出时钟信号。 PLL根据控制信号调节输出时钟信号的频率。校准器被布置成接收输出时钟信号和第二时钟信号，在输出时钟信号和第二时钟信号之间执行频率校准，并根据频率校准的结果产生控制信号。

9. 发明授权

US08838691B2 Data de-duplication in service oriented architecture and web services environment 有权
标题翻译：面向服务的架构和Web服务环境中的重复数据删除
公开(公告)号：US08838691B2
公开(公告)日：2014-09-16
申请号：US13537917
申请日：2012-06-29
申请人： Chuan Liu , Hang Xiao , Ming Yan , Jean X. Yu
发明人： Chuan Liu , Hang Xiao , Ming Yan , Jean X. Yu
IPC分类号： G06F15/16
CPC分类号： G06F15/16 , H04L67/02 , H04L69/04
摘要： A mechanism is provided in a data processing system for de-duplication in a Web services environment. Responsive to receiving a signature for a portion of a request message from a client, the mechanism performs a query in a bit stream repository to determine whether the portion of the request message has been previously received. Responsive to determining the portion of the message has been previously received, the mechanism retrieves the portion of the message from the bit stream repository. The mechanism notifies the client that the portion of the message has been previously received such that the client does not send the portion of the message.
摘要翻译：在Web服务环境中用于重复数据删除的数据处理系统中提供了一种机制。响应于从客户端接收请求消息的一部分的签名，该机制在位流存储库中执行查询以确定请求消息的部分是否已经被先前接收。先前已经接收到响应于确定消息的部分，机制从比特流存储库中检索消息的一部分。该机制通知客户消息的部分已经被先前接收到，使得客户端不发送消息的该部分。

10. 发明授权

US08010868B2 Method for processing noise interference 有权
标题翻译：噪声干扰处理方法
公开(公告)号：US08010868B2
公开(公告)日：2011-08-30
申请号：US11889152
申请日：2007-08-09
申请人： Pao-Ching Tseng , Shu-Fang Tsai , Chuan Liu
发明人： Pao-Ching Tseng , Shu-Fang Tsai , Chuan Liu
IPC分类号： H03M13/00
CPC分类号： H04L1/0061 , G06F11/1004 , G11B20/18 , G11B2020/1843 , G11B2220/2516 , H04L1/18
摘要： A method for processing noise interference in a serial AT Attachment (SATA) interface. The method includes the steps of detecting whether there is an error in CRC (Cyclic Redundancy Check) checksum or whether an R_ERR primitive (reception error primitive) is received, detecting whether a FIS (Frame Information Structure) is a data type if there is any error and returning back to error state detecting step if there is no any error, detecting whether the FIS is a ATAPI packet command CDB (Command Descriptor Block) when the FIS is the data format, and writing a special tag to the CDB and returning back to the error detecting step.
摘要翻译：一种用于处理串行AT附件（SATA）接口中噪声干扰的方法。该方法包括以下步骤：检测CRC（循环冗余校验）校验和是否接收到R_ERR原语（接收错误原语）是否存在错误，检测FIS（帧信息结构）是否为数据类型，如果有错误，如果没有任何错误，返回到错误状态检测步骤，当FIS是数据格式时，检测FIS是否是ATAPI包命令CDB（命令描述符块），并将特殊标签写入CDB并返回到错误检测步骤。

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