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1. 发明授权

US08421506B2 Output buffer with process and temperature compensation 失效
标题翻译：输出缓冲器，具有过程和温度补偿
公开(公告)号：US08421506B2
公开(公告)日：2013-04-16
申请号：US12845231
申请日：2010-07-28
申请人： Chua-Chin Wang , Ron-Chi Kuo , Jen-Wei Liu , Ming-Dou Ker
发明人： Chua-Chin Wang , Ron-Chi Kuo , Jen-Wei Liu , Ming-Dou Ker
IPC分类号： H03K3/00
CPC分类号： H03K19/00384 , G01R31/31715
摘要： An output buffer with process and temperature compensation comprises an enable terminal, a clock generator, a PMOS threshold voltage detector, an NMOS threshold voltage detector, a first comparator, a second comparator, a first compensation code generator, a second compensation code generator and an output buffer stage, wherein the output buffer stage has an output stage, the output buffer stage means for controlling a drive current generated by the output stage, wherein the output stage has a first voltage output terminal, and the modulated drive current is capable of compensating slew rate of the first voltage output terminal.
摘要翻译：具有过程和温度补偿的输出缓冲器包括使能端子，时钟发生器，PMOS阈值电压检测器，NMOS阈值电压检测器，第一比较器，第二比较器，第一补偿代码发生器，第二补偿代码发生器和输出缓冲级，其中输出缓冲级具有输出级，输出缓冲级装置，用于控制由输出级产生的驱动电流，其中输出级具有第一电压输出端，并且调制驱动电流能够补偿第一个电压输出端的转换速率。

2. 发明授权

US08193837B2 Corner detector 失效
标题翻译：角检测器
公开(公告)号：US08193837B2
公开(公告)日：2012-06-05
申请号：US12845297
申请日：2010-07-28
申请人： Chua-Chin Wang , Ron-Chi Kuo , Jen-Wei Liu , Ming-Dou Ker
发明人： Chua-Chin Wang , Ron-Chi Kuo , Jen-Wei Liu , Ming-Dou Ker
IPC分类号： H03K5/22
CPC分类号： G01R31/2621
摘要： A corner detector comprises a PMOS threshold voltage detector and an NMOS threshold voltage detector, the PMOS threshold voltage detector is composed of a first clock terminal, a first CMOS inverter, a first capacitor, a PMOS threshold voltage function generator and a first voltage output terminal, wherein the PMOS threshold voltage function generator is electrically connected to the first capacitor and applied to generate a first formula of voltage signal as a function of threshold voltage, the NMOS threshold voltage detector is composed of a second clock terminal, a second CMOS inverter, a second capacitor, an NMOS threshold voltage function generator and a second voltage output terminal, wherein the NMOS threshold voltage function generator is electrically connected to the second capacitor and applied to generate a second formula of voltage signal as a function of threshold voltage.
摘要翻译：角检测器包括PMOS阈值电压检测器和NMOS阈值电压检测器，PMOS阈值电压检测器由第一时钟端子，第一CMOS反相器，第一电容器，PMOS阈值电压函数发生器和第一电压输出端子，其中所述PMOS阈值电压函数发生器电连接到所述第一电容器并施加以产生作为阈值电压的函数的电压信号的第一公式，所述NMOS阈值电压检测器由第二时钟端子，第二CMOS反相器，第二电容器，NMOS阈值电压函数发生器和第二电压输出端子，其中所述NMOS阈值电压函数发生器电连接到所述第二电容器并且被施加以产生作为阈值电压的函数的电压信号的第二公式。

3. 发明授权

US08498085B2 ESD protection circuit 失效
标题翻译： ESD保护电路
公开(公告)号：US08498085B2
公开(公告)日：2013-07-30
申请号：US13589285
申请日：2012-08-20
申请人： Federico A. Altolaguirre , Ming-Dou Ker , Chua-Chin Wang
发明人： Federico A. Altolaguirre , Ming-Dou Ker , Chua-Chin Wang
IPC分类号： H02H9/00 , H01C7/12 , H02H1/00 , H02H1/04 , H02H3/22
CPC分类号： H02H9/046
摘要： An ESD protection circuit with leakage current reduction function includes a silicon controlled rectifier, a first CMOS inverter, a first transistor, a current mirror, a PMOS capacitor and a resistor. The first CMOS inverter electrically connects with the silicon controlled rectifier. The first transistor comprises a first end, a second end and a third end, wherein the first end electrically connects with the silicon controlled rectifier and the first CMOS inverter, and the current mirror electrically connects with the third end of the first transistor. The PMOS capacitor electrically connects with the current mirror, and the resistor electrically connects with the first CMOS inverter, the second end of the first transistor and the PMOS capacitor.
摘要翻译：具有泄漏电流降低功能的ESD保护电路包括可控硅整流器，第一CMOS反相器，第一晶体管，电流镜，PMOS电容器和电阻器。第一个CMOS反相器与可控硅整流器电连接。第一晶体管包括第一端，第二端和第三端，其中第一端与可控硅整流器和第一CMOS反相器电连接，并且电流镜与第一晶体管的第三端电连接。 PMOS电容器与电流镜电连接，并且电阻器与第一CMOS反相器，第一晶体管的第二端和PMOS电容器电连接。

4. 发明授权

US07932748B1 2×VDD-tolerant logic circuits and a related 2×VDD-tolerant I/O buffer with PVT compensation 失效
公开(公告)号：US07932748B1
公开(公告)日：2011-04-26
申请号：US12640724
申请日：2009-12-17
申请人： Ming-Dou Ker , Yan-Liang Lin , Chua-Chin Wang
发明人： Ming-Dou Ker , Yan-Liang Lin , Chua-Chin Wang
IPC分类号： H03K19/0175
CPC分类号： H03K19/018592 , H03K19/00384 , H03K19/018507
摘要： A 2×VDD-tolerant input/output (I/O) buffer circuit with process, voltage, and temperature (PVT) compensation suitable for CMOS technology is disclosed. A 2×VDD-tolerant I/O buffer with a PVT compensation circuit is implemented with novel 2×VDD-tolerant logic gates. Output slew rate variations can be kept within smaller ranges to match maximum and minimum timing specifications. A 2×VDD tolerant logic circuit for implementing the I/O buffer is also disclosed.

5. 发明申请

US20110026175A1 ELECTROSTATIC DISCHARGE PROTECTING CIRCUIT WITH ULTRA-LOW STANDBY LEAKAGE CURRENT FOR TWICE SUPPLY VOLTAGE TOLERANCE 审中-公开
标题翻译：具有超低电源电压稳定性的静电放电保护电路
公开(公告)号：US20110026175A1
公开(公告)日：2011-02-03
申请号：US12562426
申请日：2009-09-18
申请人： Ming-Dou Ker , Chang-Tzu Wang , Chua-Chin Wang
发明人： Ming-Dou Ker , Chang-Tzu Wang , Chua-Chin Wang
IPC分类号： H02H9/04
CPC分类号： H01L27/0262 , H01L27/0266 , H01L2924/0002 , H01L2924/00
摘要： The invention relates to an electrostatic discharge protecting circuit with ultra-low standby leakage current for twice supply voltage tolerance. The electrostatic discharge protecting circuit of the invention includes a substrate driver, a third transistor, a start-up circuit, a RC circuit and a second resistor. The substrate driver has a first transistor and a second transistor in serious connection. The start-up circuit has a fourth transistor and a fifth transistor with diode-connected. The RC circuit has a first resistor, a sixth transistor and a seventh transistor in serious connection. Compared with the prior art, the electrostatic discharge protecting circuit with ultra-low standby leakage current for twice supply voltage tolerance of the invention with advantages of low standby leakage current, high ESD robustness, and no gate-oxide reliability issue is an excellent circuit solution for on-chip ESD protection design for mixed-voltage I/O buffers in nanometer CMOS technologies.
摘要翻译：本发明涉及具有超低电源电压容限的超低待机漏电流的静电放电保护电路。本发明的静电放电保护电路包括衬底驱动器，第三晶体管，启动电路，RC电路和第二电阻器。衬底驱动器具有严格连接的第一晶体管和第二晶体管。启动电路具有第四晶体管和具有二极管连接的第五晶体管。 RC电路具有严重连接的第一电阻器，第六晶体管和第七晶体管。与现有技术相比，具有超低待机漏电电流的静电放电保护电路具有本发明两倍的电源电压公差，具有低待机漏电流，高ESD稳健性和无栅极氧化可靠性问题的优点，是一种极好的电路解决方案用于纳米CMOS技术的混合电压I / O缓冲器的片上ESD保护设计。

6. 发明授权

US07915914B1 2×VDD-tolerant logic circuits and a related 2×VDD-tolerant I/O buffer with PVT compensation 失效
标题翻译： 2×VDD容限逻辑电路和一个带有PVT补偿的相关2×VDD容限I / O缓冲器
公开(公告)号：US07915914B1
公开(公告)日：2011-03-29
申请号：US12909529
申请日：2010-10-21
申请人： Ming-Dou Ker , Yan-Liang Lin , Chua-Chin Wang
发明人： Ming-Dou Ker , Yan-Liang Lin , Chua-Chin Wang
IPC分类号： H03K17/16 , H03K19/003
CPC分类号： H03K19/018592 , H03K19/00384 , H03K19/018507
摘要： A 2×VDD-tolerant input/output (I/O) buffer circuit with process, voltage, and temperature (PVT) compensation suitable for CMOS technology is disclosed. A 2×VDD-tolerant I/O buffer with a PVT compensation circuit is implemented with novel 2×VDD-tolerant logic gates. Output slew rate variations can be kept within smaller ranges to match maximum and minimum timing specifications. A 2×VDD tolerant logic circuit for implementing the I/O buffer is also disclosed.
摘要翻译：公开了一种适用于CMOS技术的具有过程，电压和温度（PVT）补偿的2×VDD容差输入/输出（I / O）缓冲电路。具有PVT补偿电路的2×VDD耐受I / O缓冲器采用新颖的2×VDD容限逻辑门来实现。输出转换速率变化可以保持在更小的范围内，以符合最大和最小定时规格。还公开了用于实现I / O缓冲器的2×VDD容限逻辑电路。

7. 发明申请

US20130057992A1 ESD PROTECTION CIRCUIT 失效
标题翻译： ESD保护电路
公开(公告)号：US20130057992A1
公开(公告)日：2013-03-07
申请号：US13589285
申请日：2012-08-20
申请人： Federico A. Altolaguirre , Ming-Dou Ker , Chua-Chin Wang
发明人： Federico A. Altolaguirre , Ming-Dou Ker , Chua-Chin Wang
IPC分类号： H02H9/04
CPC分类号： H02H9/046
摘要： An ESD protection circuit with leakage current reduction function includes a silicon controlled rectifier, a first CMOS inverter, a first transistor, a current mirror, a PMOS capacitor and a resistor. The first CMOS inverter electrically connects with the silicon controlled rectifier. The first transistor comprises a first end, a second end and a third end, wherein the first end electrically connects with the silicon controlled rectifier and the first CMOS inverter, and the current mirror electrically connects with the third end of the first transistor. The PMOS capacitor electrically connects with the current mirror, and the resistor electrically connects with the first CMOS inverter, the second end of the first transistor and the PMOS capacitor.
摘要翻译：具有泄漏电流降低功能的ESD保护电路包括可控硅整流器，第一CMOS反相器，第一晶体管，电流镜，PMOS电容器和电阻器。第一个CMOS反相器与可控硅整流器电连接。第一晶体管包括第一端，第二端和第三端，其中第一端与可控硅整流器和第一CMOS反相器电连接，并且电流镜与第一晶体管的第三端电连接。 PMOS电容器与电流镜电连接，并且电阻器与第一CMOS反相器，第一晶体管的第二端和PMOS电容器电连接。

8. 发明授权

US07868659B2 I/O buffer with twice the supply voltage tolerance using normal supply voltage devices 失效
标题翻译： I / O缓冲器具有两倍的电源电压容差，使用正常的电源电压器件
公开(公告)号：US07868659B2
公开(公告)日：2011-01-11
申请号：US12575787
申请日：2009-10-08
申请人： Ming-Dou Ker , Yan-Liang Lin , Chua-Chin Wang
发明人： Ming-Dou Ker , Yan-Liang Lin , Chua-Chin Wang
IPC分类号： H03K19/0175
CPC分类号： H03K19/018592 , H03K3/0375 , H03K3/356113 , H03K19/00315 , H03K19/018521
摘要： The invention relates to an I/O buffer with twice the supply voltage tolerance using normal supply voltage devices. The I/O buffer of the invention includes a driver, a first level converter, a gate-controlled circuit and a dynamic source output stage. Signals of the I/O buffer are classified into a first voltage range and a second voltage range. The first voltage range is zero to the normal supply voltage, and the second voltage range is the normal supply voltage to twice the supply voltage. Therefore, the voltage between any two terminals of any of the transistors in the I/O buffer does not exceed the normal supply voltage so that the I/O buffer of the invention can transmit and receive signals with a voltage swing twice as high as the normal power supply voltage using normal supply voltage devices and without gate-oxide reliability problems.
摘要翻译：本发明涉及一种具有两倍于电源电压容限的I / O缓冲器，其使用正常的电源电压器件。本发明的I / O缓冲器包括驱动器，第一电平转换器，门控电路和动态源输出级。 I / O缓冲器的信号分为第一电压范围和第二电压范围。第一个电压范围为正常电源电压为零，第二个电压范围为正常电源电压的两倍于电源电压。因此，I / O缓冲器中任何一个晶体管的任何两个端子之间的电压不会超过正常电源电压，因此本发明的I / O缓冲器可以以两倍的电压摆幅发送和接收信号正常电源电压采用正常供电电压器件，无栅氧化可靠性问题。

9. 发明申请

US20100253392A1 I/O BUFFER WITH TWICE THE SUPPLY VOLTAGE TOLERANCE USING NORMAL SUPPLY VOLTAGE DEVICES 失效
标题翻译：使用正常供电电压设备的二次供电电压容差的I / O缓冲器
公开(公告)号：US20100253392A1
公开(公告)日：2010-10-07
申请号：US12575787
申请日：2009-10-08
申请人： Ming-Dou KER , Yan-Liang Lin , Chua-Chin Wang
发明人： Ming-Dou KER , Yan-Liang Lin , Chua-Chin Wang
IPC分类号： H03B1/00
CPC分类号： H03K19/018592 , H03K3/0375 , H03K3/356113 , H03K19/00315 , H03K19/018521
摘要： The invention relates to an I/O buffer with twice the supply voltage tolerance using normal supply voltage devices. The I/O buffer of the invention includes a driver, a first level converter, a gate-controlled circuit and a dynamic source output stage. Signals of the I/O buffer are classified into a first voltage range and a second voltage range. The first voltage range is zero to the normal supply voltage, and the second voltage range is the normal supply voltage to twice the supply voltage. Therefore, the voltage between any two terminals of any of the transistors in the I/O buffer does not exceed the normal supply voltage so that the I/O buffer of the invention can transmit and receive signals with a voltage swing twice as high as the normal power supply voltage using normal supply voltage devices and without gate-oxide reliability problems.
摘要翻译：本发明涉及一种具有两倍于电源电压容限的I / O缓冲器，其使用正常的电源电压器件。本发明的I / O缓冲器包括驱动器，第一电平转换器，门控电路和动态源输出级。 I / O缓冲器的信号分为第一电压范围和第二电压范围。第一个电压范围为正常电源电压为零，第二个电压范围为正常电源电压的两倍于电源电压。因此，I / O缓冲器中任何一个晶体管的任何两个端子之间的电压不会超过正常的电源电压，因此本发明的I / O缓冲器可以以两倍的电压摆幅发送和接收信号正常电源电压采用正常供电电压器件，无栅氧化可靠性问题。

10. 发明授权

US08339171B1 Threshold voltage detection circuit 失效
标题翻译：阈值电压检测电路
公开(公告)号：US08339171B1
公开(公告)日：2012-12-25
申请号：US13194283
申请日：2011-07-29
申请人： Chua-Chin Wang , Ron-Chi Kuo , Hsin-Yuan Tseng
发明人： Chua-Chin Wang , Ron-Chi Kuo , Hsin-Yuan Tseng
IPC分类号： H03K3/02
CPC分类号： G11C7/1057 , G01R31/2621 , G11C16/26 , G11C19/00 , H03K19/00384
摘要： A threshold voltage detection circuit comprises a first inverter, a first transistor, a second transistor, a third transistor and a fourth transistor. The first inverter comprises a first terminal and a second terminal, a first electrode of the first transistor is electrically connected with the second terminal of the first inverter, a fourth electrode of the second transistor is electrically connected with the first terminal of the first inverter, a seventh electrode of the third transistor is electrically connected with the second terminal of the first inverter and the first electrode of the first transistor, a tenth electrode of the fourth transistor is electrically connected with a third electrode of the first transistor and a fifth electrode of the second transistor, and an eleventh electrode of the fourth transistor is electrically connected with a ninth electrode of the third transistor.
摘要翻译：阈值电压检测电路包括第一反相器，第一晶体管，第二晶体管，第三晶体管和第四晶体管。第一反相器包括第一端子和第二端子，第一晶体管的第一电极与第一反相器的第二端子电连接，第二晶体管的第四电极与第一反相器的第一端子电连接，第三晶体管的第七电极与第一反相器的第二端子和第一晶体管的第一电极电连接，第四晶体管的第十电极与第一晶体管的第三电极电连接，第五电极的第五电极第二晶体管和第四晶体管的第十一电极与第三晶体管的第九电极电连接。

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