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1. 发明授权

US6103085A Electroplating uniformity by diffuser design 有权
标题翻译：通过扩散器设计的电镀均匀性
公开(公告)号：US6103085A
公开(公告)日：2000-08-15
申请号：US205584
申请日：1998-12-04
申请人： Christy Mei-Chu Woo , John A. Iacoponi , Kai Yang
发明人： Christy Mei-Chu Woo , John A. Iacoponi , Kai Yang
IPC分类号： C25D5/08 , C25D7/12 , C25D17/00 , H01L21/288 , C25D5/04
CPC分类号： H01L21/2885 , C25D17/001 , C25D17/008 , C25D5/08
摘要： Workpieces, such as semiconductor wafers, are electroplated with improved thickness uniformity by providing a diffuser member intermediate the cathode and anode of a fountain-type electroplating apparatus. The diffuser or member has a pattern of openings specifically designed to prevent channeling and/or selective directing of electrolyte towards the workpiece. In one embodiment, the diffuser member comprises a spiral-shaped pattern of openings originating at the center of the diffuser member and extending to the periphery thereof.
摘要翻译：通过在喷泉型电镀设备的阴极和阳极之间设置扩散件，电工工件（例如半导体晶片）电镀具有改进的厚度均匀性。扩散器或构件具有专门设计成防止电解液向工件的引导和/或选择性引导的开口图案。在一个实施例中，扩散器构件包括源自扩散器构件的中心并延伸到其周边的开口的螺旋形图案。

2. 发明授权

US6117770A Method for implanting semiconductor conductive layers 有权
标题翻译：用于注入半导体导电层的方法
公开(公告)号：US6117770A
公开(公告)日：2000-09-12
申请号：US169281
申请日：1998-10-08
申请人： Shekhar Pramanick , Dirk Brown , John A. Iacoponi , Christy Mei-Chu Woo
发明人： Shekhar Pramanick , Dirk Brown , John A. Iacoponi , Christy Mei-Chu Woo
IPC分类号： H01L21/768 , H01L23/532 , H01L21/44
CPC分类号： H01L21/76886 , H01L21/76843 , H01L21/76859 , H01L21/76877 , H01L21/76883 , H01L23/53238 , H01L2924/0002
摘要： A method for implanting copper conductive layers in channel or via openings with alloying elements, such as magnesium, boron, tin, and zirconium. The implantation is performed after conductive layer chemical-mechanical-polishing (CMP) using a surface barrier layer as an implant barrier. With the surface barrier layer being removed by barrier layer CMP, this allows directed, heavy implantation of the conductive layer with the alloying elements.
摘要翻译：在具有合金元素如镁，硼，锡和锆的通道或通孔中注入铜导电层的方法。在使用表面阻挡层作为植入物屏障的导电层化学机械抛光（CMP）之后进行注入。通过阻挡层CMP去除表面阻挡层，这允许导电层与合金元素的有针对重的注入。

3. 发明授权

US6143656A Slurry for chemical mechanical polishing of copper 有权
标题翻译：用于铜化学机械抛光的浆料
公开(公告)号：US6143656A
公开(公告)日：2000-11-07
申请号：US176891
申请日：1998-10-22
申请人： Kai Yang , Steven Avanzino , Christy Mei-Chu Woo
发明人： Kai Yang , Steven Avanzino , Christy Mei-Chu Woo
IPC分类号： H01L21/321 , H01L21/768 , H01L21/44
CPC分类号： H01L21/3212 , H01L21/76802
摘要： Copper metalization is planarized by CMP employing a slurry which avoids scratching the copper surface and is highly selective to the underlying barrier layer. Embodiments include CMP a copper filled damascene opening using a slurry comprising about 0.2 to about 0.7 wt. % Al.sub.2 O.sub.3 and about 0.2 to about 2 wt. % oxalic acid to achieve a RMS no greater than about 10 .ANG..
摘要翻译：铜的金属化通过CMP平坦化，其使用避免划伤铜表面并且对下面的阻挡层具有高度选择性的浆料。实施方案包括使用包含约0.2至约0.7重量％的浆料的CMP铜填充镶嵌开口。％Al 2 O 3和约0.2至约2重量％％草酸达到RMS不大于约10 ANGSTROM。

4. 发明授权

US06332989B1 Slurry for chemical mechanical polishing of copper 有权
标题翻译：用于铜化学机械抛光的浆料
公开(公告)号：US06332989B1
公开(公告)日：2001-12-25
申请号：US09636516
申请日：2000-08-10
申请人： Kai Yang , Steven Avanzino , Christy Mei-Chu Woo
发明人： Kai Yang , Steven Avanzino , Christy Mei-Chu Woo
IPC分类号： C09K1300
CPC分类号： H01L21/3212 , H01L21/76802
摘要： Copper metalization is planarized by CMP employing a slurry which avoids scratching the copper surface and is highly selective to the underlying barrier layer. Embodiments include CMP a copper filled damascene opening using a slurry comprising about 0.2 to about 0.7 wt. % Al2O3 and about 0.2 to about 2 wt. % oxalic acid to achieve a RMS no greater than about 10 Å.
摘要翻译：铜的金属化通过CMP平坦化，其使用避免划伤铜表面并且对下面的阻挡层具有高度选择性的浆料。实施方案包括使用包含约0.2至约0.7重量％的浆料的CMP铜填充镶嵌开口。％Al 2 O 3和约0.2至约2重量％％草酸达到RMS不大于约10埃。

5. 发明授权

US06806172B1 Physical vapor deposition of nickel 失效
标题翻译：镍的物理气相沉积
公开(公告)号：US06806172B1
公开(公告)日：2004-10-19
申请号：US09826078
申请日：2001-04-05
申请人： Christy Mei-Chu Woo , Eric N. Paton , Susan Tover
发明人： Christy Mei-Chu Woo , Eric N. Paton , Susan Tover
IPC分类号： H01L21425
CPC分类号： H01L29/665 , H01L21/324 , H01L29/7833
摘要： Nickel film formation is implemented by heating a deposition chamber during deposition of nickel on a substrate or between processing of two or more substrates or both. Embodiments include forming a nickel silicide on a composite having an exposed silicon surface by introducing the substrate to a PVD chamber having at least one heating element for heating the chamber and depositing a layer of nickel directly on the exposed silicon surface of the composite while concurrently heating the chamber with the heating element.
摘要翻译：通过在将镍沉积在基底上或在两个或更多个基底或两者的处理之间加热沉积室来实现镍膜形成。实施例包括在具有暴露的硅表面的复合材料上形成硅化镍，通过将衬底引入具有至少一个用于加热室的加热元件的PVD室，并将镍层直接沉积在复合材料的暴露的硅表面上，同时加热具有加热元件的室。

6. 发明授权

US06661067B1 Nitrogen-plasma treatment for reduced nickel silicide bridging 有权
标题翻译：氮等离子体处理用于还原硅化镍桥接
公开(公告)号：US06661067B1
公开(公告)日：2003-12-09
申请号：US10260514
申请日：2002-10-01
申请人： Minh Van Ngo , Christy Mei-Chu Woo , Paul R. Besser , Robert A. Huertas
发明人： Minh Van Ngo , Christy Mei-Chu Woo , Paul R. Besser , Robert A. Huertas
IPC分类号： H01L2994
CPC分类号： H01L29/665 , H01L21/3115 , Y10S257/90
摘要： Bridging between nickel suicide layers on a gate electrode and source/drain regions along silicon nitride sidewall spacers is prevented by treating the exposed surfaces of the silicon nitride sidewall spacers with a nitrogen plasma to create a surface region having reduced free silicon. Embodiments include treating the silicon nitride sidewall spacers with a nitrogen plasma to reduce the refractive index of the surface region to less than about 1.95.
摘要翻译：通过用氮等离子体处理氮化硅侧壁间隔物的暴露表面来形成具有减少的游离硅的表面区域，防止栅电极上的硅化镍层与沿着氮化硅侧壁间隔物的源/漏区之间的桥接。实施例包括用氮等离子体处理氮化硅侧壁间隔物以将表面区域的折射率降低到小于约1.95。

7. 发明授权

US06657304B1 Conformal barrier liner in an integrated circuit interconnect 有权
标题翻译：集成电路互连中的保形阻挡衬垫
公开(公告)号：US06657304B1
公开(公告)日：2003-12-02
申请号：US10165510
申请日：2002-06-06
申请人： Christy Mei-Chu Woo , Minh Van Ngo , John E. Sanchez, Jr. , Steven C. Avanzino
发明人： Christy Mei-Chu Woo , Minh Van Ngo , John E. Sanchez, Jr. , Steven C. Avanzino
IPC分类号： H01L2352
CPC分类号： H01L21/76843 , H01L21/32051 , H01L21/76826 , H01L21/76829 , H01L21/76831 , H01L21/76871 , H01L21/76876 , H01L2221/1089
摘要： A manufacturing method, and an integrated circuit resulting therefrom, has a substrate and a semiconductor device thereon. A stop layer over the substrate has a first dielectric layer formed thereon having an opening into which a first conformal barrier is formed. A first conformal barrier liner is formed in the opening, processed, and treated to improve adhesion. Portions of the first conformal barrier liner on the sidewalls act as a barrier to diffusion of conductor core material to the first dielectric layer. A conductor material is formed in the opening over the vertical portions of the first conformal barrier liner and the first stop layer.
摘要翻译：一种制造方法和由此产生的集成电路在其上具有基板和半导体器件。衬底上的停止层具有形成在其上的第一电介质层，其上形成有第一共形势垒的开口。在开口中形成第一共形阻挡衬里，加工和处理以改善粘附性。侧壁上的第一共形阻挡衬里的部分作为导体芯材料扩散到第一介电层的障碍。导体材料形成在第一共形阻挡衬里和第一止挡层的垂直部分上的开口中。

8. 发明授权

US06593237B1 Method for manufacturing a low dielectric constant stop layer for integrated circuit interconnects 失效
标题翻译：制造用于集成电路互连的低介电常数阻挡层的方法
公开(公告)号：US06593237B1
公开(公告)日：2003-07-15
申请号：US10179047
申请日：2002-06-24
申请人： Minh Van Ngo , Christy Mei-Chu Woo
发明人： Minh Van Ngo , Christy Mei-Chu Woo
IPC分类号： H01L2144
CPC分类号： H01L23/5329 , H01L21/76807 , H01L23/5222 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit and manufacturing method therefor is provided having a semiconductor substrate with a semiconductor device and a device dielectric layer formed on the semiconductor substrate. A channel dielectric layer on the device dielectric layer has a channel opening and a conductor core filling the channel opening. A via stop layer is formed over the channel dielectric layer to have a hydrogen concentration below 15 atomic % and a via dielectric layer is formed over the via stop layer and has a via opening. A second channel dielectric layer over the via dielectric layer has a second channel opening. A second conductor core, filling the second channel opening and the via opening, is connected to the semiconductor device.
摘要翻译：提供了一种集成电路及其制造方法，其具有半导体衬底，半导体器件和形成在半导体衬底上的器件电介质层。器件电介质层上的沟道电介质层具有通道开口和填充沟道开口的导体芯。在通道电介质层上形成通孔停止层，使氢浓度低于15原子％，并且在通孔停止层上方形成通孔电介质层，并具有通孔。通孔电介质层上的第二通道介电层具有第二通道开口。填充第二通道开口和通孔开口的第二导体芯连接到半导体器件。

9. 发明授权

US06525428B1 Graded low-k middle-etch stop layer for dual-inlaid patterning 有权
标题翻译：用于双镶嵌图案的分级低k中间蚀刻停止层
公开(公告)号：US06525428B1
公开(公告)日：2003-02-25
申请号：US10183458
申请日：2002-06-28
申请人： Minh Van Ngo , Steven C. Avanzino , Christy Mei-Chu Woo , John E. Sanchez
发明人： Minh Van Ngo , Steven C. Avanzino , Christy Mei-Chu Woo , John E. Sanchez
IPC分类号： H01L2348
CPC分类号： H01L21/76832 , H01L21/76807 , H01L23/5222 , H01L23/53228 , H01L23/53238 , H01L23/53295 , H01L2924/0002 , Y10S438/931 , H01L2924/00
摘要： Improved etch selectivity, barrier metal wetting and reduced interconnect capacitance are achieved by implementing damascene processing employing a graded middle etch stop layer comprising a first silicon carbide layer, a silicon-rich layer on the first silicon carbide, and a second silicon carbide layer on the silicon-rich layer. Embodiments include sequentially depositing a porous low-k dielectric layer over a lower capped Cu line, depositing the graded middle-etch stop layer, depositing a porous low-k dielectric layer on the graded middle-etch stop layer, forming a dual damascene opening exposing the silicon-rich surface at the bottom of the trench opening, depositing a seed layer, depositing a barrier middle layer, such as Ta or a Ta/TaN composite, and filling the opening with Cu.
摘要翻译：改进的蚀刻选择性，阻挡金属润湿和降低的互连电容通过实施使用包括第一碳化硅层，第一碳化硅上的富硅层和第二碳化硅层上的第二碳化硅层的分级中间蚀刻停止层的镶嵌加工来实现富硅层。实施例包括在下部封装的Cu线上顺序沉积多孔低k电介质层，沉积渐变的中间蚀刻停止层，在分级中间蚀刻停止层上沉积多孔低k电介质层，形成双镶嵌开口露出在沟槽开口的底部的富硅表面，沉积种子层，沉积阻挡中间层，如Ta或Ta / TaN复合材料，并用Cu填充开口。

10. 发明授权

US06507123B1 Nickel silicide process using UDOX to prevent silicide shorting 有权
标题翻译：使用UDOX的硅化镍工艺防止硅化物短路
公开(公告)号：US06507123B1
公开(公告)日：2003-01-14
申请号：US09679878
申请日：2000-10-05
申请人： Christy Mei-Chu Woo , Minh Van Ngo , Jacques J. Bertrand
发明人： Christy Mei-Chu Woo , Minh Van Ngo , Jacques J. Bertrand
IPC分类号： H01L27088
CPC分类号： H01L29/665 , H01L29/6656
摘要： A MOSFET semiconductor device includes a substrate, a gate electrode, a gate oxide. first and second sets of sidewall spacers and nickel suicide layers. The gate oxide is disposed between the gate electrode and the substrate, and the substrate includes source/drain regions. The gate electrode has first and second opposing sidewalls, and the first set of sidewall spacers are formed undoped silicon oxide and are respectively disposed adjacent the first and second sidewalls. The second set of sidewall spacers are formed from silicon nitride and are respectively disposed adjacent the first set of sidewall spacers. The nickel silicide layers are disposed on the source/drain regions and the gate electrode. The second set of sidewall spacers being formed from undoped silicon oxide prevents the formation of nickel silicide on the second set of sidewall spacers. A method of manufacturing the semiconductor device is also disclosed.
摘要翻译： MOSFET半导体器件包括衬底，栅电极，栅极氧化物。第一和第二组侧壁间隔物和镍硅化物层。栅极氧化物设置在栅极电极和衬底之间，并且衬底包括源极/漏极区域。栅电极具有第一和第二相对的侧壁，并且第一组侧壁间隔物形成为未掺杂的氧化硅，并且分别设置在第一和第二侧壁附近。第二组侧壁间隔件由氮化硅形成，并且分别设置在第一组侧壁间隔件附近。硅化镍层设置在源/漏区和栅电极上。由未掺杂的氧化硅形成的第二组侧壁间隔件防止在第二组侧壁间隔物上形成硅化镍。还公开了制造半导体器件的方法。

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