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1. 发明申请

US20120030097A1 Apparatus and Method for Valuing Articles 审中-公开
标题翻译：仪器和方法评估文章
公开(公告)号：US20120030097A1
公开(公告)日：2012-02-02
申请号：US13263239
申请日：2010-04-06
申请人： Christopher John Hagan , Mark Ian Shipley
发明人： Christopher John Hagan , Mark Ian Shipley
IPC分类号： G06Q20/00 , G06Q30/00
CPC分类号： G07F7/06 , G06Q20/10 , G06Q30/0278 , G06Q30/06
摘要： Embodiments of the present invention provide apparatus for automatic valuation of articles. The apparatus may comprise an article receiving device arranged to receive an article therein; and an article assessment device arranged to determine the presence of a prescribed one or more materials in said article along with the quantity thereof, the article assessment device being arranged to determine a value of the one or more materials present in the article based on a stored amount of the value of a given quantity of each of said one or more materials, and the quantity of the one or more materials present in the article as determined by the article assessment device, and to output to the user the value of said article based on the value of the one or more materials and/or output to the user the value of the one or more materials.
摘要翻译：本发明的实施例提供用于物品自动估价的装置。该装置可以包括物品接收装置，其被布置成在其中容纳物品; 以及物品评估装置，其布置成与所述物品的数量一起确定所述物品中规定的一种或多种材料的存在，所述物品评估装置被布置为基于存储的物品来确定所述物品中存在的一种或多种物质的值所述一种或多种材料中的每一种的给定数量的值的量，以及由所述物品评估装置确定的所述物品中存在的一种或多种材料的数量，并且向所述用户输出所述物品的价值对一种或多种材料的价值和/或向用户输出一种或多种材料的价值。

2. 发明授权

US06473821B1 Multiple processor interface, synchronization, and arbitration scheme using time multiplexed shared memory for real time systems 失效
标题翻译：多处理器接口，同步和仲裁方案，使用实时系统的时间复用共享存储器
公开(公告)号：US06473821B1
公开(公告)日：2002-10-29
申请号：US09468144
申请日：1999-12-21
申请人： Terry Robert Altmayer , James Alfred Wargnier , Christopher John Hagan
发明人： Terry Robert Altmayer , James Alfred Wargnier , Christopher John Hagan
IPC分类号： G06F1200
CPC分类号： G06F13/372 , G06F13/1605
摘要： An arbitration and synchronization method and system for allowing multiple processors to access a shared memory includes an arbitrator. The arbitrator is operable with the processors for enabling each of the processors exclusive access to the memory for a predetermined time period on a rotating basis. In operation, a time period of a time frame is associated with each of the processors. The time periods of the time frame are then counted. The arbitrator then enables a processor to have exclusive access to the shared memory for the time period associated with the processor when the counted time period is the time period associated with the processor.
摘要翻译：用于允许多个处理器访问共享存储器的仲裁和同步方法和系统包括仲裁器。仲裁器可与处理器一起操作，以使得每个处理器能够以旋转的方式独占访问存储器预定的时间段。在操作中，时间帧的时间段与每个处理器相关联。然后对时间段的时间段进行计数。然后，当计数的时间段是与处理器相关联的时间段时，仲裁器使得处理器在与处理器相关联的时间段内具有对共享存储器的独占访问。

3. 发明授权

US06993551B2 Sparse-coefficient functions for reducing computational requirements 失效
公开(公告)号：US06993551B2
公开(公告)日：2006-01-31
申请号：US10122453
申请日：2002-04-12
申请人： J. William Whikehart , Christopher John Hagan
发明人： J. William Whikehart , Christopher John Hagan
IPC分类号： G06F7/52
CPC分类号： G06F7/533 , G06F5/01 , G06F7/607
摘要： A method for reducing computational steps in a digital processor including multiplications producing a plurality of multiplication products. This method specifies a desired multiplication function to be implemented in a digital processor, the desired multiplication function having a respective set of initial coefficients corresponding to each digital multiplier stage of the multiplication function. An initial total number of non-zero bits of the initial coefficients is determined and the initial coefficients are modified. Further, a resulting number of non-zero bits in the modified set of coefficients is quantified. Finally, the modified set of coefficients that result in a reduced number of non-zero bits as compared to the initial coefficients is chosen. The new modified coefficients are implemented in the device by constructing the digital multiplier stages with the modified coefficients. Thus, the digital processor performs a desired multiplication function using “sparse” coefficients to achieve a reduced execution time or lower implementation cost for a given signal conditioning function.

4. 发明授权

US06178211B1 Digital processing radio receiver with adaptive bandwidth control 有权
标题翻译：数字处理无线电接收机具有自适应带宽控制
公开(公告)号：US06178211B1
公开(公告)日：2001-01-23
申请号：US09425550
申请日：1999-10-22
申请人： J. William Whikehart , Christopher John Hagan , John William Wagner , Nicholas Lawrence Difiore , John Elliott Whitecar , James Alfred Wargnier
发明人： J. William Whikehart , Christopher John Hagan , John William Wagner , Nicholas Lawrence Difiore , John Elliott Whitecar , James Alfred Wargnier
IPC分类号： H04B1406
CPC分类号： H03G5/28 , H04B1/1036 , H04B2001/1054
摘要： A carrier-based signal is received from a tuner and is digitized to produce a digital intermediate frequency (IF) signal. Automatic gain control is applied to the carrier-based signal either prior to or after digitization. An adaptive intermediate frequency bandwidth control system detects IF signal level after channel filtering. The level is compared to a predetermined threshold having a value related to the known signal level of the AGC'ed signal which is being input to the channel filter in order to provide a measure of either 1) the presence of interfering adjacent channels, or 2) reception or a weak signal which can't be compensated for by AGC. The IF bandwidth is narrowed in either circumstance. Digital FIR or IIR filtering is used. The invention allows bandwidth switching to be done very quickly with minimal transient effects. A threshold value is selected depending upon the IF channel bandwidth being used at any given time.
摘要翻译：从调谐器接收基于载波的信号，并将其数字化以产生数字中频（IF）信号。在数字化之前或之后，对基于载波的信号应用自动增益控制。自适应中频带宽控制系统检测信道滤波后的中频信号电平。将该电平与具有与正在输入到信道滤波器的AGC信号的已知信号电平相关的值的预定阈值进行比较，以提供1）干扰相邻信道的存在或2 ）接收或由AGC无法补偿的弱信号。在任何情况下，IF带宽都变窄。使用数字FIR或IIR滤波。本发明允许以最小的瞬态效应非常快地完成带宽切换。根据在任何给定时间使用的IF信道带宽来选择阈值。

5. 发明授权

US6058148A Digital processing radio receiver with adaptive bandwidth control 失效
标题翻译：数字处理无线电接收机具有自适应带宽控制
公开(公告)号：US6058148A
公开(公告)日：2000-05-02
申请号：US883692
申请日：1997-06-27
申请人： J. William Whikehart , Christopher John Hagan , John William Wagner , Nicholas Lawrence Difiore , John Elliott Whitecar , James Alfred Wargnier
发明人： J. William Whikehart , Christopher John Hagan , John William Wagner , Nicholas Lawrence Difiore , John Elliott Whitecar , James Alfred Wargnier
IPC分类号： H03G5/28 , H04B1/10
CPC分类号： H03G5/28 , H04B1/1036 , H04B2001/1054
摘要： An adaptive intermediate frequency bandwidth control system detects IF signal levels both before and after channel filtering. The two levels are compared to provide a measure of the presence of interfering adjacent channels. This measure is compared to a programmable threshold and the IF bandwidth is narrowed if any interferers are detected. Digital FIR or IIR filtering is used. The invention allows bandwidth switching to be done very quickly with minimal transient effects. A difference threshold is selected depending upon the IF channel bandwidth being used at any given time.
摘要翻译：自适应中频带宽控制系统在信道滤波前后检测中频信号电平。比较两个级别以提供干扰相邻信道的存在的度量。将此措施与可编程阈值进行比较，如果检测到任何干扰源，则IF带宽变窄。使用数字FIR或IIR滤波。本发明允许以最小的瞬态效应非常快地完成带宽切换。根据在任何给定时间使用的IF信道带宽来选择差分阈值。

6. 发明授权

US06256358B1 Digital signal processing architecture for multi-band radio receiver 失效
标题翻译：用于多频无线电接收机的数字信号处理架构
公开(公告)号：US06256358B1
公开(公告)日：2001-07-03
申请号：US09049355
申请日：1998-03-27
申请人： J. William Whikehart , James Alfred Wargnier , Bradley Anderson Ballard , Nicholas Lawrence Difiore , John Elliott Whitecar , Christopher John Hagan
发明人： J. William Whikehart , James Alfred Wargnier , Bradley Anderson Ballard , Nicholas Lawrence Difiore , John Elliott Whitecar , Christopher John Hagan
IPC分类号： H04H106
CPC分类号： H03D5/00 , H03D3/006 , H03D3/007 , H03D7/165 , H03D2200/005 , H03D2200/0052 , H03D2200/0054 , H03D2200/0082
摘要： A digital signal processing architecture for an audio system combines multiple functions in programmable and reconfigurable blocks to achieve an efficient use of hardware and chip area. AM, FM, and audio functions can be performed using the same reconfigurable hardware while taking into account the different sample rates and processing functions required for each.
摘要翻译：用于音频系统的数字信号处理架构将可编程和可重构块中的多个功能组合以实现硬件和芯片区域的有效使用。 AM，FM和音频功能可以使用相同的可重配置硬件来执行，同时考虑到每个硬件所需的不同采样率和处理功能。

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