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    • 6. 发明授权
    • Clock timing recovery using arbitrary sampling frequency
    • 使用任意采样频率的时钟定时恢复
    • US07072431B2
    • 2006-07-04
    • US10284231
    • 2002-10-30
    • Vincent WangJ. William WhikehartJohn Elliott Whitecar
    • Vincent WangJ. William WhikehartJohn Elliott Whitecar
    • H04L7/00
    • H04L25/062H04H20/16H04H40/27H04H2201/13H04L7/0004H04L7/0331
    • A bit timing signal is regenerated from an encoded digital signal in a receiver using a predetermined sample rate Fs. An input pulse signal is generated in response to predetermined transitions of the encoded digital signal. A clock count signal is generated having a variable clock period according to cyclical counting of the clock count signal up to a count value S at the predetermined sample rate, the count value alternating between an upper value Su and a lower value Sl so that the variable clock period has an average length substantially equal to a data bit period of the encoded digital signal. The clock count signal is synchronized with the encoded digital signal by 1) counting the input pulse signals to generate a pulse count, 2) counting sampling periods between successive input pulse signals to generate a sample count, and 3) generating a sync signal if the pulse count is greater than a pulse threshold and the sample count is greater than a sample threshold. The clock count signal and the pulse count are reset in response to the sync signal.
    • 使用预定采样率F S从接收机中的编码数字信号再生位定时信号。 响应于编码数字信号的预定转换而产生输入脉冲信号。 产生具有可变时钟周期的时钟计数信号,该可变时钟周期根据时钟计数信号的周期性计数直到预定采样率的计数值S,该计数值在上限值S 和 使得可变时钟周期具有基本上等于编码数字信号的数据比特周期的平均长度的较低值S <1>。 时钟计数信号与编码的数字信号同步1)对输入脉冲信号进行计数以产生脉冲计数; 2)对连续的输入脉冲信号之间的采样周期进行计数以产生采样计数,以及3)产生同步信号,如果 脉冲计数大于脉冲阈值,并且样本计数大于采样阈值。 响应于同步信号,时钟计数信号和脉冲计数被复位。
    • 9. 发明授权
    • Timing recovery loop with non-integer length
    • 具有非整数长度的定时恢复环路
    • US07149265B2
    • 2006-12-12
    • US10440497
    • 2003-05-16
    • Yung Da WangJ. William WhikehartJohn Elliott Whitecar
    • Yung Da WangJ. William WhikehartJohn Elliott Whitecar
    • H04L7/00
    • H04H40/45H04H2201/13H04L7/0331H04L7/042
    • A timing signal is regenerated from an encoded digital signal having a data clock frequency Rb in a receiver using a predetermined sample rate Fs, wherein the data clock period 1/Rb is not an integer multiple of the predetermined sample period 1/Fs. The method comprises generating an input pulse signal in response to the encoded digital signal. Each of the input pulse signals is accumulated in a predetermined delay element which stores an accumulated value, wherein the predetermined delay element is in a delay loop including N delay elements each having a respective accumulated value. The accumulated values are circulated within the delay loop by shifting at each of the sample periods according to a predetermined shift sequence, the predetermined shift sequence including a plurality of single shifts and at least one other shift size to provide a number of shifts N+δ during a cycle of N sample periods. A synchronization pulse is generated in response to the accumulated values and a predetermined threshold. A counter is operated to output the timing signal in response to the predetermined sample rate Fs, the counter having a variable counter period according to a predetermined counter sequence. The variable counter period has an average over time corresponding to the data clock period 1/Rb. The counter is reset in response to the synchronization pulse (if synchronization becomes necessary).
    • 定时信号从接收机中具有数据时钟频率R BAT的编码数字信号再生,使用预定的采样率F S s,其中数据时钟周期1 / R b 不是预定采样周期1 / F的整数倍。 该方法包括响应于编码的数字信号产生输入脉冲信号。 每个输入脉冲信号被累积在存储累加值的预定延迟元件中,其中预定延迟元件处于包括具有相应累积值的N个延迟元件的延迟环中。 通过根据预定的移位序列在每个采样周期内移位,累积值在延迟环路内循环,该预定移位序列包括多个单移位和至少一个其它移位大小以提供多个移位N + 在N个采样周期的周期。 响应于累积值和预定阈值产生同步脉冲。 操作计数器以响应于预定采样率F SUB输出定时信号,计数器根据预定的计数器顺序具有可变计数器周期。 可变计数器周期具有对应于数据时钟周期1 / R b1的时间的平均值。 响应于同步脉冲(如果需要同步),计数器被复位。