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    • 5. 发明授权
    • Method and apparatus for digital VCDL startup
    • 数字VCDL启动的方法和装置
    • US08219344B2
    • 2012-07-10
    • US12789544
    • 2010-05-28
    • Mohammad S. MobinGregory W. SheetsLane A. SmithPaul H. Tracy
    • Mohammad S. MobinGregory W. SheetsLane A. SmithPaul H. Tracy
    • H03L7/06
    • H03L7/0812
    • Methods and apparatus are provided for improved startup of a voltage controlled delay loop that has an injection clock and a return clock. A control signal is determined for a plurality of delay elements in a voltage controlled delay loop by obtaining a histogram count of a number of occurrences of at least one predefined logic value for a plurality of delay settings of the voltage controlled delay loop; determining a histogram count that approximately corresponds to an alignment of at least one edge in the injection and return clocks; and determining the control signal based on the determined histogram count that approximately corresponds to the alignment. The voltage controlled delay loop can be started using the determined control signal. The histogram count can be obtained for a plurality of PVT combinations and the control signal can then be determined for each PVT combination.
    • 提供了用于改进启动具有注入时钟和返回时钟的电压控制延迟回路的方法和装置。 通过获得针对电压控制的延迟环路的多个延迟设置的至少一个预定逻辑值的出现次数的直方图计数,为电压控制的延迟环路中的多个延迟元件确定控制信号; 确定近似对应于所述注入和返回时钟中的至少一个边缘的对准的直方图计数; 以及基于大致对应于所述对准的所确定的直方图计数来确定所述控制信号。 可以使用所确定的控制信号来开始压控延迟环路。 可以为多个PVT组合获得直方图计数,然后可以为每个PVT组合确定控制信号。