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1. 发明授权

US08761237B2 Low nonlinear distortion variable gain amplifier 有权
标题翻译：低非线性失真可变增益放大器
公开(公告)号：US08761237B2
公开(公告)日：2014-06-24
申请号：US13288096
申请日：2011-11-03
申请人： Pervez M. Aziz , Hiroshi Kimura
发明人： Pervez M. Aziz , Hiroshi Kimura
IPC分类号： H03H7/30 , H03H7/40 , H03K5/159
CPC分类号： H03F3/195 , H03F3/211 , H03F3/45183 , H03F2200/294 , H03F2203/45454 , H03F2203/45466 , H03F2203/45701 , H03G5/165 , H04L25/03057
摘要： A variable gain amplifier (VGA) useful in a receiver that recovers transmitted digital signals. A first amplifier in the VGA has a first gain, an input coupled to an input of the VGA, and an output coupled to a load. A second amplifier in the VGA has a second gain, an input coupled to the input of the VGA, and an output coupled to the load. In a first mode of operation, the first gain is substantially zero and the second gain ranges between a maximum gain and a fraction of the maximum gain. In a second mode of operation the first gain is substantially the maximum gain and the second gain ranges between the maximum gain and the fraction of the maximum gain, and an algebraic sum of the first gain and second gain is no greater than the maximum gain to reduce non-linear distortion at low VGA gain.
摘要翻译：一种可变增益放大器（VGA），可用于恢复传输的数字信号的接收机。 VGA中的第一放大器具有第一增益，耦合到VGA的输入的输入和耦合到负载的输出。 VGA中的第二放大器具有第二增益，耦合到VGA的输入的输入和耦合到负载的输出。在第一工作模式中，第一增益基本为零，第二增益范围为最大增益和最大增益的一部分。在第二种操作模式中，第一增益基本上是最大增益，第二增益在最大增益和最大增益分数之间的范围内，第一增益和第二增益的代数和不大于在低VGA增益下降低非线性失真。

2. 发明申请

US20130148712A1 CONDITIONAL ADAPTATION OF LINEAR FILTERS IN A SYSTEM HAVING NONLINEARITY 有权
标题翻译：线性滤波器在非线性系统中的条件适应
公开(公告)号：US20130148712A1
公开(公告)日：2013-06-13
申请号：US13315831
申请日：2011-12-09
申请人： Amaresh Malipatil , Pervez M. Aziz , Mohammad S. Mobin , Ye Liu
发明人： Amaresh Malipatil , Pervez M. Aziz , Mohammad S. Mobin , Ye Liu
IPC分类号： H04L27/01
CPC分类号： H04L25/03057 , H04L7/033 , H04L7/0331 , H04L25/0292 , H04L25/0307 , H04L25/03159 , H04L25/03885 , H04L2025/03636 , H04L2025/037
摘要： Described embodiments adjust configurable parameters of at least one filter of a communication system. The method includes conditioning, by an analog front end (AFE) of a receiver in the communication system, an input signal applied to the receiver. Sampled values of the conditioned input signal are generated and digitized. An error detection module generates an error signal based on digitized values of the input signal and a target value. A decision feedback equalizer generates an adjustment signal based on the digitized values of the input signal and values of the error signal. A summer subtracts the adjustment signal from the conditioned input signal, generating an adjusted input signal. An adaptation module determines a conditional adaptation signal based on a comparison of sampled values of the adjusted input signal and values of the error signal. The adaptation module adjusts a transfer function of at least one filter based on the conditional adaptation signal.
摘要翻译：描述的实施例调整通信系统的至少一个滤波器的可配置参数。该方法包括通过通信系统中的接收机的模拟前端（AFE）调整施加到接收机的输入信号。生成调节输入信号的采样值并进行数字化。误差检测模块基于输入信号的数字化值和目标值产生误差信号。判决反馈均衡器基于输入信号的数字化值和误差信号的值生成调整信号。夏季从调节的输入信号中减去调整信号，产生经调整的输入信号。适应模块基于经调整的输入信号的采样值和误差信号的值的比较来确定条件适配信号。适应模块基于条件适应信号来调整至少一个滤波器的传递函数。

3. 发明申请

US20130114665A1 Low Nonlinear Distortion Variable Gain Amplifier 有权
标题翻译：低非线性失真可变增益放大器
公开(公告)号：US20130114665A1
公开(公告)日：2013-05-09
申请号：US13288096
申请日：2011-11-03
申请人： Pervez M. Aziz , Hiroshi Kimura
发明人： Pervez M. Aziz , Hiroshi Kimura
IPC分类号： H04L27/01 , H03F3/45 , H03G3/20 , H03G3/30
CPC分类号： H03F3/195 , H03F3/211 , H03F3/45183 , H03F2200/294 , H03F2203/45454 , H03F2203/45466 , H03F2203/45701 , H03G5/165 , H04L25/03057
摘要： A variable gain amplifier (VGA) useful in a receiver that recovers transmitted digital signals. A first amplifier in the VGA has a first gain, an input coupled to an input of the VGA, and an output coupled to a load. A second amplifier in the VGA has a second gain, an input coupled to the input of the VGA, and an output coupled to the load. In a first mode of operation, the first gain is substantially zero and the second gain ranges between a maximum gain and a fraction of the maximum gain. In a second mode of operation the first gain is substantially the maximum gain and the second gain ranges between the maximum gain and the fraction of the maximum gain, and an algebraic sum of the first gain and second gain is no greater than the maximum gain to reduce non-linear distortion at low VGA gain.
摘要翻译：一种可变增益放大器（VGA），可用于恢复传输的数字信号的接收机。 VGA中的第一放大器具有第一增益，耦合到VGA的输入的输入和耦合到负载的输出。 VGA中的第二放大器具有第二增益，耦合到VGA的输入的输入和耦合到负载的输出。在第一工作模式中，第一增益基本为零，第二增益范围为最大增益和最大增益的一部分。在第二种操作模式中，第一增益基本上是最大增益，第二增益在最大增益和最大增益分数之间的范围内，第一增益和第二增益的代数和不大于在低VGA增益下降低非线性失真。

4. 发明授权

US08416907B2 Method and apparatus for integral state initialization and quality of lock monitoring in a clock and data recovery system 有权
标题翻译：用于整体状态初始化的方法和装置以及时钟和数据恢复系统中锁定监视的质量
公开(公告)号：US08416907B2
公开(公告)日：2013-04-09
申请号：US12846390
申请日：2010-07-29
申请人： Pervez M. Aziz , Gregory W. Sheets , Vladimir Sindalovsky
发明人： Pervez M. Aziz , Gregory W. Sheets , Vladimir Sindalovsky
IPC分类号： H04L7/00 , H04L25/00 , H04L25/40
CPC分类号： H03L7/0807 , H03L7/087 , H03L7/093 , H04L7/0004 , H04L7/0331
摘要： Methods and apparatus are provided for improving the performance of second order CDR systems. The integral state of the CDR system is initialized to a value that is based on an expected frequency profile that may be known a priori for certain applications. One or more quality of lock (QOL) metrics are also monitored that are derived from the integral register state value. A quality of a locking between a received signal and a local clock generated by a Clock and Data Recovery (CDR) system is evaluated by monitoring a state value of an integral register in a digital loop filter of the CDR system; evaluating one or more predefined criteria based on the integral register state value; and identifying a poor lock condition if the one or more predefined criteria are not satisfied.
摘要翻译：提供了用于提高二级CDR系统的性能的方法和装置。 CDR系统的整体状态被初始化为基于对于某些应用可以是先验已知的预期频率分布的值。还监视从积分寄存器状态值导出的一个或多个锁定质量（QOL）度量。通过监视CDR系统的数字环路滤波器中的积分寄存器的状态值来评估由时钟和数据恢复（CDR）系统产生的接收信号和本地时钟之间的锁定的质量; 基于积分寄存器状态值来评估一个或多个预定标准; 并且如果不满足一个或多个预定标准，则识别差的锁定条件。

5. 发明授权

US08315298B2 Method and apparatus for rate-dependent equalization 失效
标题翻译：用于速率依赖均衡的方法和装置
公开(公告)号：US08315298B2
公开(公告)日：2012-11-20
申请号：US11930780
申请日：2007-10-31
申请人： Pervez M Aziz , Mohammad S Mobin , Gregory W Sheets , Lane A Smith , Paul H. Tracy
发明人： Pervez M Aziz , Mohammad S Mobin , Gregory W Sheets , Lane A Smith , Paul H. Tracy
IPC分类号： H03H7/30
CPC分类号： H04L25/03057 , H04L25/0262 , H04L2025/03547
摘要： Methods and apparatus are provided for equalizing a received signal. A received signal is equalized by determining a data rate of the received signal; obtaining one or more equalization parameters associated with the determined data rate; and equalizing the received signal using the obtained one or more equalization parameters. The equalization parameters may comprise, for example, one or more of a gain parameter, zero control for a high pass filter and one or more threshold settings for one or more latches used during the equalizing step, such as data latches or transition latches (or both).
摘要翻译：提供了用于均衡接收信号的方法和装置。接收到的信号通过确定接收信号的数据速率来均衡; 获得与所确定的数据速率相关联的一个或多个均衡参数; 以及使用所获得的一个或多个均衡参数来均衡所接收的信号。均衡参数可以包括例如增益参数，高通滤波器的零控制和在均衡步骤期间使用的一个或多个锁存器的一个或多个阈值设置中的一个或多个，诸如数据锁存器或转换锁存器（或都）。

6. 发明申请

US20120014460A1 Compensation for Transmission Line Length Variation in a Serdes System 有权
标题翻译： Serdes系统中传输线路长度变化的补偿
公开(公告)号：US20120014460A1
公开(公告)日：2012-01-19
申请号：US13243190
申请日：2011-09-23
申请人： Pervez M. Aziz , Adam Healey , Shawn Logan
发明人： Pervez M. Aziz , Adam Healey , Shawn Logan
IPC分类号： H04B3/00 , H04L25/00
CPC分类号： H04L25/03885 , H04L1/203
摘要： Described embodiments provide a method and system for signal compensation in a SERDES communication system that includes monitoring the quality of a data signal after passing through a transmission channel. The quality of the data signal is monitored with at least one of a BER calculation algorithm and a received eye quality monitoring algorithm. Variations in channel length of the transmission channel are compensated for by i) adjusting a length of transmission line delay of the data signal from the transmission channel, ii) comparing the data signal quality with a threshold for the adjusted data signal; and iii) repeating i) and ii) until the data signal quality meets the threshold.
摘要翻译：所描述的实施例提供了一种在SERDES通信系统中用于信号补偿的方法和系统，其包括在通过传输信道之后监视数据信号的质量。使用BER计算算法和接收到的眼睛质量监视算法中的至少一个来监视数据信号的质量。通过i）调整来自传输信道的数据信号的传输线延迟的长度来补偿传输信道的信道长度的变化，ii）将数据信号质量与调整数据信号的阈值进行比较; 和iii）重复i）和ii）直到数据信号质量满足阈值。

7. 发明授权

US08027409B2 Noise prediction-based signal detection and cross-talk mitigation 有权
标题翻译：基于噪声预测的信号检测和串扰缓解
公开(公告)号：US08027409B2
公开(公告)日：2011-09-27
申请号：US11962409
申请日：2007-12-21
申请人： Pervez M. Aziz , Mohammad S. Mobin , Gregory W. Sheets
发明人： Pervez M. Aziz , Mohammad S. Mobin , Gregory W. Sheets
IPC分类号： H03K9/00
CPC分类号： H04L25/03057 , H03K5/135 , H03M9/00
摘要： In an exemplary embodiment, noise prediction-based data detection is described with respect to a SERDES (serializer/deserializer) backplane primary channel subject to inter-symbol interference (ISI) noise and added cross-talk noise from other channels. Noise prediction-based data detection combines an added error component from inter-symbol interference (ISI) noise and an added error component from cross-talk noise into an overall noise prediction error term and cancels effects of residual ISI and cross-talk for various components of the exemplary embodiment.
摘要翻译：在示例性实施例中，关于经由符号间干扰（ISI）噪声的SERDES（串行器/解串行器）背板主信道和来自其他信道的增加的串扰噪声来描述基于噪声预测的数据检测。基于噪声预测的数据检测将来自符号间干扰（ISI）噪声的附加误差分量和来自串扰噪声的附加误差分量组合成总体噪声预测误差项，并消除各种组件的残留ISI和串扰的影响的示例性实施例。

8. 发明授权

US07583458B2 Channel optimization metrics 有权
标题翻译：渠道优化指标
公开(公告)号：US07583458B2
公开(公告)日：2009-09-01
申请号：US10900546
申请日：2004-07-28
申请人： Viswanath Annampedu , Pervez M. Aziz
发明人： Viswanath Annampedu , Pervez M. Aziz
IPC分类号： G11B5/09 , G11B20/10
CPC分类号： G11B20/10212 , G11B20/10037 , G11B20/10046 , G11B20/10296 , G11B20/10481
摘要： A recording system, such as a magnetic or optical recording system, employs optimization metrics that are independent of a target partial response for equalization of a signal read from a recording channel. The optimization metrics employ samples adjacent to codeword boundaries of codewords representing encoded data, such as servo data, read from a recording medium. The optimization metrics are used to select filter parameters and/or tap weights for equalization. The filter parameters and/or tap weights might be derived based on the type of data read from the recording medium, the type of detector employed to detect the codewords of the read data, and the type of encoder/decoder employed for the read data.
摘要翻译：诸如磁或光记录系统的记录系统采用独立于用于对从记录通道读取的信号进行均衡的目标部分响应的优化度量。优化度量采用与表示从记录介质读取的编码数据（例如伺服数据）的码字的码字边界相邻的样本。优化度量用于选择滤波器参数和/或抽头权重以进行均衡。滤波器参数和/或抽头权重可以基于从记录介质读取的数据的类型，用于检测读取数据的代码字的检测器的类型以及用于读取数据的编码器/解码器的类型来导出。

9. 发明申请

US20090086807A1 METHODS AND APPARATUS FOR DETERMINING THRESHOLD OF ONE OR MORE DFE TRANSITION LATCHES BASED ON INCOMING DATA EYE 有权
标题翻译：用于确定基于入眼数据的一个或多个DFE转换锁存器的阈值的方法和装置
公开(公告)号：US20090086807A1
公开(公告)日：2009-04-02
申请号：US11864110
申请日：2007-09-28
申请人： Pervez M. Aziz , Mohammad S. Mobin
发明人： Pervez M. Aziz , Mohammad S. Mobin
IPC分类号： H04L27/01
CPC分类号： H04L25/03063 , H04L25/0307
摘要： Methods and apparatus are provided for determining the threshold position of one or mote DFE latches using an evaluation of the incoming data eye. A threshold position is determined for one or more transition latches employed by a decision-feedback equalizer by obtaining a plurality of samples of a data eye using a data eye monitor; obtaining a vertical eye opening metric from the data eye monitor; and determining the threshold position for the one or more transition latches based on the vertical eye opening metric. A decision-feedback equalizer is also disclosed that comprises at least one data latch having a data threshold; and at least one transition latching having a transition threshold, wherein the transition threshold and the data threshold ate unequal
摘要翻译：提供方法和装置，用于使用输入数据眼的评估来确定一个或微尘DFE锁存器的阈值位置。通过使用数据眼睛监视器获得数据眼睛的多个采样来确定由判决反馈均衡器采用的一个或多个转换锁存器的阈值位置; 从数据眼监视器获得垂直眼睛开度度量; 以及基于所述垂直眼图开度度量确定所述一个或多个过渡锁存器的阈值位置。还公开了一种包括具有数据阈值的至少一个数据锁存器的判决反馈均衡器; 以及至少一个具有转变阈值的转换锁存器，其中转换阈值和数据阈值不相等

10. 发明授权

US06606728B1 Rate (M/N) code encoder, detector, and decoder for control data 失效
标题翻译：速率（M / N）编码器，检测器和解码器用于控制数据
公开(公告)号：US06606728B1
公开(公告)日：2003-08-12
申请号：US09413082
申请日：1999-10-06
申请人： Pervez M. Aziz
发明人： Pervez M. Aziz
IPC分类号： H03M1303
CPC分类号： G11B20/10287 , G11B20/10009 , G11B20/10055 , G11B20/1426 , H03M5/145
摘要： A system for block encoding and block decoding of servo data with a rate (M/N) code, where M is an integer greater than 1 and N is an integer that is greater than M. Two codes are described for the encoding and decoding processes: a rate (2/6) code and a rate (2/8) code. In general, block encoding and-block decoding maps between M servo data bits and N coded symbol bits. Such block encoding with a rate (M/N) code may be employed in a magnetic recording system for encoding servo data that is written to a servo data sector on a magnetic recording medium. Encoded servo data is read from the magnetic medium and block decoded. A forced maximum-likelihood, partial-response (PRML) detector is used to detect the N coded symbol bits from channel samples read from the magnetic medium. Block encoding provides greater coding gain for a detector when the characteristics of the block code are used to improve performance of the PRML detector that is used to detect the N coded symbol bits. Such PRML detector may employ a Viterbi algorithm (VA). State transition decisions over a block of N channel samples, or N clock cycles, form a path through a trellis of the VA, and the characteristics of the block code are used to force decisions for state transitions in the trellis. The PRML detector may force a decision for each state transition based on a priori knowledge of the known valid transitions defined by the rate (M/N) code symbol bits.
摘要翻译：一种利用速率（M / N）码对伺服数据进行块编码和块解码的系统，其中M是大于1的整数，N是大于M的整数。描述了编码和解码过程的两个代码：代码（2/6）和代码（2/8）。通常，块编码和块解码映射在M个伺服数据位和N个编码符号位之间。在磁记录系统中可以采用具有速率（M / N）码的这种块编码，用于对写在磁记录介质上的伺服数据扇区的伺服数据进行编码。编码伺服数据从磁介质读取并进行解码。使用强制最大似然，部分响应（PRML）检测器来从磁介质读取的信道样本中检测N个编码符号位。当块代码的特性用于提高用于检测N个编码符号位的PRML检测器的性能时，块编码为检测器提供更大的编码增益。这种PRML检测器可以采用维特比算法（Viterbi algorithm）。在N个通道样本块或N个时钟周期上的状态转换决策形成通过VA的网格的路径，并且使用块代码的特征来强制格架中的状态转换的决定。 PRML检测器可以基于由速率（M / N）码符号位定义的已知有效转换的先验知识来强制对每个状态转换的决定。

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