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    • 3. 发明授权
    • Buried layer substrate isolation in integrated circuits
    • 集成电路中埋地层衬底隔离
    • US06831346B1
    • 2004-12-14
    • US09849047
    • 2001-05-04
    • Gabriel LiKenelm G. D. MurrayJose ArreolaShahin SharifzadehK. Nirmal Ratnakumar
    • Gabriel LiKenelm G. D. MurrayJose ArreolaShahin SharifzadehK. Nirmal Ratnakumar
    • H01L2900
    • H01L29/41758H01L21/761H01L21/823878H01L29/0847
    • In an embodiment of an integrated circuit structure having buried layer substrate isolation and a method for forming same, a buried layer having conductivity type opposite to that of an overlying well region is used for wells containing transistors prone to noise generation, where the wells are of the same conductivity type as the substrate. The buried layer may in some embodiments include a first portion underlying the transistor and a second portion spaced apart from and laterally surrounding the first portion. In some embodiments, the circuit may include a doped annular region of the same conductivity type as the buried layer, where the annular region contacts a portion of the buried layer and laterally surrounds the transistor. The circuit may further include metallization adapted to connect the well and annular region to opposite polarities of a power supply voltage, or in some embodiments to preclude such connection.
    • 在具有掩埋层衬底隔离的集成电路结构及其形成方法的实施例中,具有与上覆阱区相反的导电类型的掩埋层用于容纳产生噪声的晶体管的阱,其中阱为 与基片相同的导电类型。 在一些实施例中,掩埋层可以包括晶体管下面的第一部分和与第一部分间隔开并横向包围第一部分的第二部分。 在一些实施例中,电路可以包括与埋层相同的导电类型的掺杂环形区域,其中环形区域接触掩埋层的一部分并横向围绕晶体管。 电路还可以包括适于将阱和环形区域连接到电源电压的相反极性的金属化,或者在一些实施例中以排除这种连接。