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1. 发明申请

US20130020347A1 Strip Dispenser 审中-公开
标题翻译：剥线器
公开(公告)号：US20130020347A1
公开(公告)日：2013-01-24
申请号：US13491811
申请日：2012-06-08
申请人： Christopher Gieda , David Honan , Nathan Rollins , Michael Price , Andrew Simon , Shane Yellin
发明人： Christopher Gieda , David Honan , Nathan Rollins , Michael Price , Andrew Simon , Shane Yellin
IPC分类号： B65D83/08
CPC分类号： B65D83/0847 , B65D83/0876 , G01N33/4875
摘要： A strip dispenser (70) for dispensing one strip (S) from a plurality of strips (S). The strip dispenser (70) includes a container (2) that is constructed and arranged to hold a number of strips (S). There is a first structure (3) that defines one or more thin slots (8) that are generally parallel to the perimeter of the container (2), and that have a smallest dimension that is greater than the smallest dimension of a strip (S), where the slots (8) are configured and arranged to inhibit two strips that are stuck together back to back from passing through the slot (8) together. There is also a strip sorting structure (4) that inhibits a strip (S) that has at least partially passed through a slot (8) from fully leaving the container (2) until the strip (S) is pulled out of the container (2) by the user.
摘要翻译：一种带状分配器（70），用于从多个条带（S）分配一个条带（S）。条带式分配器（70）包括容器（2），其被构造和布置成容纳多个条带（S）。存在限定一个或多个薄的狭槽（8）的第一结构（3），其大致平行于容器（2）的周边，并且具有大于带材的最小尺寸的最小尺寸（S ），其中所述狭槽（8）被配置和布置成禁止两个条带背靠背地粘合在一起通过所述狭槽（8）。还有一种条带分类结构（4），其阻止至少部分地穿过狭槽（8）的条带（S）完全离开容器（2）直到条带（S）从容器中拉出（ 2）由用户。

2. 发明申请

US20110163118A1 Metered Dispenser 审中-公开
标题翻译：计量分配器
公开(公告)号：US20110163118A1
公开(公告)日：2011-07-07
申请号：US12985619
申请日：2011-01-06
申请人： Christopher Gieda , David Honan , Nathan Rollins , Shane Yellin , Andrew Simon
发明人： Christopher Gieda , David Honan , Nathan Rollins , Shane Yellin , Andrew Simon
IPC分类号： G01F11/26
CPC分类号： G01F11/24
摘要： A dispensing apparatus includes a container having an opening, and a doser coupled with the container about the container opening. The doser includes a housing forming a chamber with an interior wall, an inlet, and an outlet. The inlet is diametrically offset from the outlet, and substantially aligned with the opening of the container. The doser also includes a covering member to alternatively cover and open the inlet and the outlet. The covering member is movable about a range of positions to substantially completely cover at least one of the inlet and outlet at all positions in the range. The covering member covers no more than a portion of the chamber interior wall when the covering member completely opens the outlet.
摘要翻译：分配装置包括具有开口的容器和与容器围绕容器开口连接的加料器。加料器包括形成具有内壁，入口和出口的室的壳体。入口与出口直径偏离，并与容器的开口基本对齐。加料器还包括覆盖构件以备选地覆盖和打开入口和出口。覆盖部件可在一定范围的位置上移动，以在该范围内的所有位置基本上完全覆盖入口和出口中的至少一个。当覆盖构件完全打开出口时，覆盖构件覆盖室内壁的不超过一部分。

3. 发明授权

US06784105B1 Simultaneous native oxide removal and metal neutral deposition method 有权
标题翻译：同时自然氧化物去除和金属中性沉积法
公开(公告)号：US06784105B1
公开(公告)日：2004-08-31
申请号：US10410496
申请日：2003-04-09
申请人： Chih-Chao Yang , Yun Wang , Larry Clevenger , Andrew Simon , Stephen Greco , Kaushik Chanda , Terry Spooner , Andy Cowley , Sunfei Fang
发明人： Chih-Chao Yang , Yun Wang , Larry Clevenger , Andrew Simon , Stephen Greco , Kaushik Chanda , Terry Spooner , Andy Cowley , Sunfei Fang
IPC分类号： H01L2144
CPC分类号： H01L21/76844 , H01L21/76805 , H01L21/76838 , H01L21/76862 , H01L21/76865
摘要： A method of fabricating a semiconductor device having a dielectric structure on which an interconnect structure is optionally patterned using lithographic and etching techniques, within a single deposition chamber, is provided. The dielectric structure may optionally be covered by diffusion barrier materials prior to a sputter etching process. This sputter etching process is used to remove the native oxide on an underneath metal conductor surface and includes a directional gaseous bombardment with simultaneous deposition of metal neutral. Diffusion barrier materials may also be deposited into the pattern.
摘要翻译：提供一种制造具有电介质结构的半导体器件的方法，其中使用光刻和蚀刻技术在单个淀积室内使互连结构任意地图案化。在溅射蚀刻工艺之前，电介质结构可任选地被扩散阻挡材料覆盖。该溅射蚀刻工艺用于去除下面的金属导体表面上的自然氧化物，并且包括具有同时沉积金属中性的定向气体轰击。扩散阻挡材料也可以沉积到图案中。

4. 发明申请

US20120153359A1 NICKEL-SILICIDE FORMATION WITH DIFFERENTIAL PT COMPOSITION 有权
标题翻译：具有差异PT组成的镍 - 硅化物形成
公开(公告)号：US20120153359A1
公开(公告)日：2012-06-21
申请号：US13408246
申请日：2012-02-29
申请人： Asa Frye , Andrew Simon
发明人： Asa Frye , Andrew Simon
IPC分类号： H01L29/772
CPC分类号： H01L21/28518 , H01L29/665
摘要： Embodiments of the invention provide a method of forming nickel-silicide. The method may include depositing first and second metal layers over at least one of a gate, a source, and a drain region of a field-effect-transistor (FET) through a physical vapor deposition (PVD) process, wherein the first metal layer is deposited using a first nickel target material containing platinum (Pt), and the second metal layer is deposited on top of the first metal layer using a second nickel target material containing no or less platinum than that in the first nickel target material; and annealing the first and second metal layers covering the FET to form a platinum-containing nickel-silicide layer at a top surface of the gate, source, and drain regions.
摘要翻译：本发明的实施例提供一种形成硅化镍的方法。该方法可以包括通过物理气相沉积（PVD）工艺在场效应晶体管（FET）的栅极，源极和漏极区域中的至少一个上沉积第一和第二金属层，其中第一金属层使用含有铂（Pt）的第一镍靶材料沉积，并且使用不比第一镍靶材料中不含铂的第二镍靶材料将第二金属层沉积在第一金属层的顶部上; 以及退火覆盖所述FET的所述第一和第二金属层，以在所述栅极，源极和漏极区域的顶表面处形成含铂的硅化镍层。

5. 发明申请

US20110169058A1 NICKEL-SILICIDE FORMATION WITH DIFFERENTIAL PT COMPOSITION 有权
标题翻译：具有差异PT组成的镍 - 硅化物形成
公开(公告)号：US20110169058A1
公开(公告)日：2011-07-14
申请号：US12684144
申请日：2010-01-08
申请人： Asa Frye , Andrew Simon
发明人： Asa Frye , Andrew Simon
IPC分类号： H01L29/78 , H01L21/3205
CPC分类号： H01L21/28518 , H01L29/665
摘要： Embodiments of the invention provide a method of forming nickel-silicide. The method may include depositing first and second metal layers over at least one of a gate, a source, and a drain region of a field-effect-transistor (FET) through a physical vapor deposition (PVD) process, wherein the first metal layer is deposited using a first nickel target material containing platinum (Pt), and the second metal layer is deposited on top of the first metal layer using a second nickel target material containing no or less platinum than that in the first nickel target material; and annealing the first and second metal layers covering the FET to form a platinum-containing nickel-silicide layer at a top surface of the gate, source, and drain regions.
摘要翻译：本发明的实施例提供一种形成硅化镍的方法。该方法可以包括通过物理气相沉积（PVD）工艺在场效应晶体管（FET）的栅极，源极和漏极区域中的至少一个上沉积第一和第二金属层，其中第一金属层使用含有铂（Pt）的第一镍靶材料沉积，并且使用不比第一镍靶材料中不含铂的第二镍靶材料将第二金属层沉积在第一金属层的顶部上; 以及退火覆盖所述FET的所述第一和第二金属层，以在所述栅极，源极和漏极区域的顶表面处形成含铂的硅化镍层。

6. 发明申请

US20050167838A1 DEVICE AND METHODOLOGY FOR REDUCING EFFECTIVE DIELECTRIC CONSTANT IN SEMICONDUCTOR DEVICES 有权
标题翻译：用于减少半导体器件中有效介电常数的器件和方法
公开(公告)号：US20050167838A1
公开(公告)日：2005-08-04
申请号：US10707996
申请日：2004-01-30
申请人： Daniel Edelstein , Matthew Colburn , Edward Cooney , Timothy Dalton , John Fitzsimmons , Jeffrey Gambino , Elbert Huang , Michael Lane , Vincent McGahay , Lee Nicholson , Satyanarayana Nitta , Sampath Purushothaman , Sujatha Sankaran , Thomas Shaw , Andrew Simon , Anthony Stamper
发明人： Daniel Edelstein , Matthew Colburn , Edward Cooney , Timothy Dalton , John Fitzsimmons , Jeffrey Gambino , Elbert Huang , Michael Lane , Vincent McGahay , Lee Nicholson , Satyanarayana Nitta , Sampath Purushothaman , Sujatha Sankaran , Thomas Shaw , Andrew Simon , Anthony Stamper
IPC分类号： H01L21/033 , H01L21/302 , H01L21/311 , H01L21/4763 , H01L21/768 , H01L23/48 , H01L23/522 , H01L23/532 , H01L29/40
CPC分类号： B82Y30/00 , H01L21/0332 , H01L21/31111 , H01L21/31144 , H01L21/7682 , H01L21/76829 , H01L23/5222 , H01L23/53295 , H01L2924/0002 , Y10S438/947 , H01L2924/00
摘要： A method for manufacturing a structure includes providing a structure having an insulator layer with at least one interconnect and forming a sub lithographic template mask on the insulator layer. A selective etching step is used for etching the insulator layer through the sub lithographic template mask to form sub lithographic features near the at least one interconnect. A supra lithographic blocking mask may also be utilized. In another aspect, the method includes forming pinch off sections of sub lithographic size formed in a capping layer on the insulator layer. A semiconductor structure includes an insulator layer having at least one interconnect feature and at least one column formed in the insulator layer. A plurality of sub lithographic features formed on a top portion of the insulator layer and communicating with the at least one column is also provided. The plurality of sub lithographic features have a cross section or diameter less than any of the at least one column. A gap may be prohibited from forming on or near scribe lanes and vias
摘要翻译：一种制造结构的方法包括提供具有至少一个互连的绝缘层的结构，并在绝缘体层上形成次光刻模板掩模。选择性蚀刻步骤用于通过子光刻模板掩模蚀刻绝缘体层，以在至少一个互连附近形成亚光刻特征。还可以使用超光刻阻挡掩模。另一方面，该方法包括形成在绝缘体层上的覆盖层中形成的亚光刻尺寸的夹断部分。半导体结构包括具有至少一个互连特征的绝缘体层和形成在绝缘体层中的至少一个列。还提供了形成在绝缘体层的顶部并与至少一个柱连通的多个次级光刻特征。所述多个亚光刻特征具有小于或小于所述至少一列中的任何一个的横截面或直径。可能禁止在划线车道和通道上或附近形成间隙

7. 发明授权

US08741773B2 Nickel-silicide formation with differential Pt composition 有权
标题翻译：具有差异Pt组成的硅化镍形成
公开(公告)号：US08741773B2
公开(公告)日：2014-06-03
申请号：US12684144
申请日：2010-01-08
申请人： Asa Frye , Andrew Simon
发明人： Asa Frye , Andrew Simon
IPC分类号： H01L29/78
CPC分类号： H01L21/28518 , H01L29/665
摘要： Embodiments of the invention provide a method of forming nickel-silicide. The method may include depositing first and second metal layers over at least one of a gate, a source, and a drain region of a field-effect-transistor (FET) through a physical vapor deposition (PVD) process, wherein the first metal layer is deposited using a first nickel target material containing platinum (Pt), and the second metal layer is deposited on top of the first metal layer using a second nickel target material containing no or less platinum than that in the first nickel target material; and annealing the first and second metal layers covering the FET to form a platinum-containing nickel-silicide layer at a top surface of the gate, source, and drain regions.
摘要翻译：本发明的实施例提供一种形成硅化镍的方法。该方法可以包括通过物理气相沉积（PVD）工艺在场效应晶体管（FET）的栅极，源极和漏极区域中的至少一个上沉积第一和第二金属层，其中第一金属层使用含有铂（Pt）的第一镍靶材料沉积，并且使用不比第一镍靶材料中不含铂的第二镍靶材料将第二金属层沉积在第一金属层的顶部上; 以及退火覆盖所述FET的所述第一和第二金属层，以在所述栅极，源极和漏极区域的顶表面处形成含铂的硅化镍层。

8. 发明授权

US07704876B2 Dual damascene interconnect structures having different materials for line and via conductors 有权
标题翻译：双镶嵌互连结构具有不同的材料用于线路和通孔导体
公开(公告)号：US07704876B2
公开(公告)日：2010-04-27
申请号：US11847657
申请日：2007-08-30
申请人： Jeffrey Gambino , Edward Cooney, III , Anthony Stamper , William Thomas Motsiff , Michael Lane , Andrew Simon
发明人： Jeffrey Gambino , Edward Cooney, III , Anthony Stamper , William Thomas Motsiff , Michael Lane , Andrew Simon
IPC分类号： H01L21/4763
CPC分类号： H01L21/76811 , H01L21/76807 , H01L21/76808 , H01L21/76813 , H01L21/76843 , H01L21/76846 , H01L21/76865 , H01L21/76877 , H01L23/53238 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： Methods are disclosed for forming dual damascene back-end-of-line (BEOL) interconnect structures using materials for the vias or studs which are different from those used for the line conductors, or using materials for the via liner which are different from those used for the trench liner, or having a via liner thickness different from that of the trench liner. Preferably, a thick refractory metal is used in the vias for improved mechanical strength while using only a thin refractory metal in the trenches to provide low resistance.
摘要翻译：公开了用于形成双镶嵌后端（BEOL）互连结构的方法，其使用与用于线路导体的那些不同的通孔或螺柱的材料，或者使用不同于所使用的通孔衬垫的材料用于沟槽衬垫，或者具有不同于沟槽衬套的通孔衬垫厚度。优选地，在通孔中使用厚的难熔金属以改善机械强度，同时仅在沟槽中使用薄的难熔金属来提供低电阻。

9. 发明授权

US07300867B2 Dual damascene interconnect structures having different materials for line and via conductors 失效
标题翻译：双镶嵌互连结构具有不同的材料用于线路和通孔导体
公开(公告)号：US07300867B2
公开(公告)日：2007-11-27
申请号：US11174985
申请日：2005-07-05
申请人： Jeffrey Gambino , Edward Cooney, III , Anthony Stamper , William Thomas Motsiff , Michael Lane , Andrew Simon
发明人： Jeffrey Gambino , Edward Cooney, III , Anthony Stamper , William Thomas Motsiff , Michael Lane , Andrew Simon
IPC分类号： H01L21/4763
CPC分类号： H01L21/76811 , H01L21/76807 , H01L21/76808 , H01L21/76813 , H01L21/76843 , H01L21/76846 , H01L21/76865 , H01L21/76877 , H01L23/53238 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： Methods are disclosed for forming dual damascene back-end-of-line (BEOL) interconnect structures using materials for the vias or studs which are different from those used for the line conductors, or using materials for the via liner which are different from those used for the trench liner, or having a via liner thickness different from that of the trench liner. Preferably, a thick refractory metal is used in the vias for improved mechanical strength while using only a thin refractory metal in the trenches to provide low resistance.
摘要翻译：公开了用于形成双镶嵌后端（BEOL）互连结构的方法，其使用与用于线路导体的那些不同的通孔或螺柱的材料，或者使用不同于所使用的通孔衬垫的材料用于沟槽衬垫，或者具有不同于沟槽衬套的通孔衬垫厚度。优选地，在通孔中使用厚的难熔金属以改善机械强度，同时仅在沟槽中使用薄的难熔金属来提供低电阻。

10. 发明授权

US06958540B2 Dual damascene interconnect structures having different materials for line and via conductors 有权
标题翻译：双镶嵌互连结构具有不同的材料用于线路和通孔导体
公开(公告)号：US06958540B2
公开(公告)日：2005-10-25
申请号：US10604026
申请日：2003-06-23
申请人： Jeffrey Gambino , Edward Cooney, III , Anthony Stamper , William Thomas Motsiff , Michael Lane , Andrew Simon
发明人： Jeffrey Gambino , Edward Cooney, III , Anthony Stamper , William Thomas Motsiff , Michael Lane , Andrew Simon
IPC分类号： H01L21/768 , H01L23/42 , H01L23/52 , H01L29/40
CPC分类号： H01L21/76811 , H01L21/76807 , H01L21/76808 , H01L21/76813 , H01L21/76843 , H01L21/76846 , H01L21/76865 , H01L21/76877 , H01L23/53238 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： Interconnect structures are disclosed for forming dual damascene back-end-of-line (BEOL) structure using materials for the vias or studs which are different from those used for the line conductors, or using materials for the via liner which are different from those used for the trench liner, or having a via liner thickness different from that of the trench liner. Preferably, a thick refractory metal is used in the vias for improved mechanical strength while using only a thin refractory metal in the trenches to provide low resistance.
摘要翻译：公开了用于形成双镶嵌后端（BEOL）结构的互连结构，其使用与用于线路导体的那些不同的通孔或螺柱的材料，或者使用不同于所使用的通孔衬垫的材料用于沟槽衬垫，或者具有不同于沟槽衬套的通孔衬垫厚度。优选地，在通孔中使用厚的难熔金属以改善机械强度，同时仅在沟槽中使用薄的难熔金属来提供低电阻。

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