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1. 发明授权

US06795515B1 Method and apparatus for locating sampling points in a synchronous data stream 失效
标题翻译：用于定位同步数据流中采样点的方法和装置
公开(公告)号：US06795515B1
公开(公告)日：2004-09-21
申请号：US09547919
申请日：2000-04-11
申请人： Christopher G. Riedle , Jean-Claude Abbiate , Alain Richard Blanc , Daniel Wind
发明人： Christopher G. Riedle , Jean-Claude Abbiate , Alain Richard Blanc , Daniel Wind
IPC分类号： H03K19096
CPC分类号： H04L7/0338 , H04L7/046
摘要： An apparatus and process for updating a sample time in a serial link which converts serial data in parallel data. A delay line stores multiple samples of at least two data bits received over the serial link. The contents of the delay line are matched so that they can be analyzed by a processor to determine an optimum sampling position in the delay line. The processor is programmed to analyze contents of the latch by creating a sample mask from a plurality of delay line samples. The sample mask identifies transition edges of first and second data bits within the delay line. The transition edges are validated with respect to the presence, for first and second initial sampling positions for the respective data bits. New sampling positions are determined from the validated edges, and the initial sampling positions are updated with sampling positions which have been determined from the new sampling positions. In this way phase jitter induced by environmental concerns is minimized using new sampling positions along the delay line for coding the data into parallel data.
摘要翻译：一种用于更新以并行数据转换串行数据的串行链路中的采样时间的装置和处理。延迟线存储通过串行链路接收的至少两个数据位的多个样本。延迟线的内容被匹配，使得它们可以被处理器分析以确定延迟线中的最佳采样位置。处理器被编程为通过从多个延迟线样本中创建采样掩模来分析锁存器的内容。采样掩码识别延迟线内的第一和第二数据位的转换边缘。对于相应数据位的第一和第二初始采样位置的存在，过渡边缘被验证。从验证的边缘确定新的采样位置，并且利用从新采样位置确定的采样位置更新初始采样位置。以这种方式，使用沿着延迟线的新采样位置来最小化由环境问题引起的相位抖动，以将数据编码为并行数据。

2. 发明授权

US06611217B2 Initialization system for recovering bits and group of bits from a communications channel 失效
标题翻译：用于从通信信道恢复比特和比特组的初始化系统
公开(公告)号：US06611217B2
公开(公告)日：2003-08-26
申请号：US10150337
申请日：2002-05-17
申请人： Brian Buchanan , John Marshall , Christopher G. Riedle
发明人： Brian Buchanan , John Marshall , Christopher G. Riedle
IPC分类号： H03M900
CPC分类号： G11C7/1084 , G11C7/1078 , G11C2207/2254 , H03M9/00 , H04J3/047 , H04L7/0337 , H04L7/046
摘要： A system normally converts a parallel data word to a single serial data stream to use a high speed serial link. The parallel data word is partitioned into N sub-sets or nibbles and each nibble is then serialized and transmitted over N serial links using high speed differential drivers. Each of the N serialized nibbles are received in a differential receiver. The serialized nibbles are then coverted back into N parallel nibbles and the N parallel nibbles are then assembled back to the original parallel data word. To increase reliability, the received data is coupled to a tapped delay element having M stages of delay. A training sequence and algorithm are used to determine which of the taps of the delay element are a desired delay distance away from data transitions. These taps are then used to sample the incoming signals to reconstruct the parallel data word.
摘要翻译：系统通常将并行数据字转换为单个串行数据流以使用高速串行链路。并行数据字被分割为N个子集或半字节，然后每个半字节被串行化并通过使用高速差分驱动器的N个串行链路传输。 N个串行化的半字节中的每一个都被接收在差分接收器中。然后将串行化的半字节复盖为N个并行半字节，然后将N个并行半字节组装回原始并行数据字。为了提高可靠性，接收的数据被耦合到具有M级延迟的抽头延迟元件。使用训练序列和算法来确定延迟元件的抽头中的哪一个是远离数据转换的期望的延迟距离。然后使用这些抽头对输入信号进行采样以重建并行数据字。

3. 发明授权

US06430242B1 Initialization system for recovering bits and group of bits from a communications channel 失效
标题翻译：用于从通信信道恢复比特和比特组的初始化系统
公开(公告)号：US06430242B1
公开(公告)日：2002-08-06
申请号：US09330713
申请日：1999-06-11
申请人： Brian Buchanan , John Marshall , Christopher G. Riedle
发明人： Brian Buchanan , John Marshall , Christopher G. Riedle
IPC分类号： H03K19096
CPC分类号： G11C7/1084 , G11C7/1078 , G11C2207/2254 , H03M9/00 , H04J3/047 , H04L7/0337 , H04L7/046
摘要： An interface system that conveys data at approximately 500 MBitsps between modules. The interface system performs multistream serialization at the transmitter and multistream de-serialization at the Receiver. As a consequence, fewer interface connections are required between the modules.
摘要翻译：一个接口系统，可在模块之间传输大约500 MB的数据。接口系统在发射机处执行多流串行化，并在接收机处执行多流逆序列化。因此，模块之间需要更少的接口连接。

4. 发明授权

US06970435B1 Data alignment compensator 失效
标题翻译：数据对准补偿器
公开(公告)号：US06970435B1
公开(公告)日：2005-11-29
申请号：US09330743
申请日：1999-06-11
申请人： Brian Buchanan , John Marshall , Christopher G. Riedle
发明人： Brian Buchanan , John Marshall , Christopher G. Riedle
IPC分类号： H04B7/005 , H04L1/20 , H04L12/26
CPC分类号： H04L1/205
摘要： An apparatus and method that correct skew associated with data receive from different transmission links. A known training pattern is sent through the transmission links. The training pattern is recovered and forwarded through delay registers/selecter logic to a memory buffer. A programmed controller accesses the memory and searches for the training pattern. If the training pattern is found for each transmission link, the offsets between the transmission links are determined and are used by the delay registers/selecter logic to adjust the position of the pattern so that the patterns from each link is linearly aligned within the memory buffer.
摘要翻译：纠正与来自不同传输链路的数据接收相关的偏差的装置和方法。通过传输链路发送已知的训练模式。训练模式被恢复并通过延迟寄存器/选择器逻辑转发到存储器缓冲器。编程控制器访问存储器并搜索训练模式。如果针对每个传输链路找到训练模式，则确定传输链路之间的偏移量并由延迟寄存器/选择器逻辑使用以调整模式的位置，使得来自每个链路的模式在存储器缓冲器内线性对准。

5. 发明授权

US07111092B1 Buffer management technique for a hypertransport data path protocol 有权
标题翻译：超传输数据路径协议的缓冲管理技术
公开(公告)号：US07111092B1
公开(公告)日：2006-09-19
申请号：US10826076
申请日：2004-04-16
申请人： John W. Mitten , Christopher G. Riedle , David Richard Barach , Kenneth H. Potter, Jr. , Kent Hoult , Jeffery B. Scott
发明人： John W. Mitten , Christopher G. Riedle , David Richard Barach , Kenneth H. Potter, Jr. , Kent Hoult , Jeffery B. Scott
IPC分类号： G06F13/00
CPC分类号： G06F13/4221
摘要： A buffer-management technique efficiently manages a set of data buffers accessible to first and second devices interconnected by a split transaction bus, such as a Hyper-Transport (HPT) bus. To that end, a buffer manager controls access to a set of “free” buffer descriptors, each free buffer descriptor referencing a corresponding buffer in the set of data buffers. Advantageously, the buffer manager ensures that the first and second devices are allocated a sufficient number of free buffer descriptors for use in a HPT data path protocol in which the first and second devices have access to respective sets of free buffer descriptors. Because buffer management over the HPT bus is optimized by the buffer manager, the amount of processing bandwidth traditionally consumed managing descriptors can be reduced.
摘要翻译：缓冲器管理技术有效地管理由分离事务总线（例如超传输（HPT）总线）互连的第一和第二设备可访问的一组数据缓冲器。为此，缓冲区管理器控制对一组“空闲”缓冲区描述符的访问，每个空闲缓冲区描述符引用该组数据缓冲区中的相应缓冲区。有利地，缓冲器管理器确保第一和第二设备被分配足够数量的可用于HPT数据路径协议的空闲缓冲器描述符，其中第一和第二设备可以访问相应的一组空闲缓冲区描述符。由于缓冲管理器优化了HPT总线上的缓冲区管理，所以可以减少传统上消耗管理描述符的处理带宽。

6. 发明授权

US06650661B1 System that compensates for variances due to process and temperature changes 失效
标题翻译：补偿由于过程和温度变化引起的差异的系统
公开(公告)号：US06650661B1
公开(公告)日：2003-11-18
申请号：US09330735
申请日：1999-06-11
申请人： Brian Buchanan , Carl Thomas Gray , Christopher G. Riedle , Raymond Paul Rizzo
发明人： Brian Buchanan , Carl Thomas Gray , Christopher G. Riedle , Raymond Paul Rizzo
IPC分类号： H04L700
CPC分类号： H03M9/00 , H04J3/047 , H04L7/0338 , H04L7/046
摘要： A device and method that adjust data due to temperature variations is disclosed. The data is captured in a multi-stage delay line. A first controller parses the data and identifies an Edge1 value and an Edge2 value for bits in the delay line. The edge values are used to generate signals that set a Multiplexer 1 (MUX1) and a Multiplexer 2 (MUX2) to select bits from the delay line. A second controller processes an edge sample from bits in the delay line to determine if the data has shifted in the delay line relative to the current multiplexer settings. An edge sample is a snapshot of the delay line values. The new edge values generated by the second controller are selectively filtered and integrated with initial edge values to generate new settings for the MUX1 and MUX2.
摘要翻译：公开了一种由于温度变化而调整数据的装置和方法。数据被捕获在多级延迟线中。第一个控制器解析数据并识别延迟线中的位的Edge1值和Edge2值。边缘值用于产生设置多路复用器1（MUX1）和多路复用器2（MUX2）以从延迟线选择位的信号。第二控制器从延迟线中的位处理边缘采样，以确定数据是否相对于当前多路复用器设置在延迟线中移位。边缘样本是延迟线值的快照。由第二控制器产生的新边缘值被选择性地滤波并与初始边缘值集成以产生MUX1和MUX2的新设置。

7. 发明授权

US07117308B1 Hypertransport data path protocol 有权
标题翻译：超传输数据路径协议
公开(公告)号：US07117308B1
公开(公告)日：2006-10-03
申请号：US10818670
申请日：2004-04-06
申请人： John W. Mitten , Christopher G. Riedle , David Richard Barach , Kenneth H. Potter, Jr. , Kent Hoult , Jeffery B. Scott
发明人： John W. Mitten , Christopher G. Riedle , David Richard Barach , Kenneth H. Potter, Jr. , Kent Hoult , Jeffery B. Scott
IPC分类号： G06F12/00
CPC分类号： G06F13/387
摘要： A data path protocol eliminates most of the conventional read transactions required to transfer data between devices interconnected by a split transaction bus, such as a HyperTransport (HPT) bus. To that end, each device is configured to manage its own set of buffer descriptors, unlike previous data path protocols in which only one device managed all the buffer descriptors. As such, neither device has to perform a read transaction to retrieve a “free” buffer descriptor from the other device. As a result, only write transactions are performed for transferring descriptors across the HPT bus, thereby decreasing the amount of traffic over the bus and eliminating conventional latencies associated with read transactions. In addition, because descriptors are separately managed in each device, the data path protocol also conserves processing bandwidth that is traditionally consumed by managing ownership of the buffer descriptors within a single device.
摘要翻译：数据路径协议消除了通过分组事务总线（如HyperTransport（HPT）总线）互连的设备之间传输数据所需的大多数常规读取事务。为此，每个设备配置为管理其自己的一组缓冲区描述符，与之前的数据路径协议不同，其中只有一个设备管理所有缓冲区描述符。因此，两个设备都不得不执行读取事务以从另一个设备检索“空闲”缓冲区描述符。因此，仅执行用于在HPT总线上传送描述符的写入事务，从而减少总线上的业务量并消除与读取事务相关联的传统延迟。此外，由于在每个设备中分别管理描述符，所以数据路径协议还节省了传统上通过管理单个设备中的缓冲区描述符的所有权而消耗的处理带宽。

8. 发明授权

US06222380B1 High speed parallel/serial link for data communication 有权
标题翻译：用于数据通信的高速并行/串行链路
公开(公告)号：US06222380B1
公开(公告)日：2001-04-24
申请号：US09330968
申请日：1999-06-11
申请人： Robert Glen Gerowitz , Carl Thomas Gray , John Marshall , Christopher G. Riedle , Raymond Paul Rizzo
发明人： Robert Glen Gerowitz , Carl Thomas Gray , John Marshall , Christopher G. Riedle , Raymond Paul Rizzo
IPC分类号： H03K19173
CPC分类号： H03M9/00 , C22C21/08 , C22F1/047 , C22F1/05
摘要： An interface system that conveys data at approximately 500 MBitsps between modules. The interface system performs multistream serialization at the transmitter and multistream de-serialization at the Receiver. As a consequence, fewer interface connections are required between the modules.
摘要翻译：一个接口系统，可在模块之间传输大约500 MB的数据。接口系统在发射机处执行多流串行化，并在接收机处执行多流逆序列化。因此，模块之间需要更少的接口连接。

9. 发明授权

US5778172A Enhanced real-time topology analysis system or high speed networks 失效
标题翻译：增强的实时拓扑分析系统或高速网络
公开(公告)号：US5778172A
公开(公告)日：1998-07-07
申请号：US635811
申请日：1996-04-22
申请人： Christopher G. Riedle , Paul C. Hershey
发明人： Christopher G. Riedle , Paul C. Hershey
IPC分类号： H04L12/24 , G06F11/30
CPC分类号： H04L41/12 , H04L41/32
摘要： The disclosed system allows determination of topological aspects of a high speed data communications network in real time without interfering with the operation of the network. The topographical information determined by the present invention includes the cable length of the network, the cable length between stations on the network, and the station addresses and relative order of stations on the network. The system determines the cable length of the network by dividing the amount of time that a token spends on the cables of the network as it travels completely around the network by the propagation speed per unit length of the cables of the network. The system determines the length of cable between any two adjacent stations on the network by determining the length of time between frames transmitted by the adjacent stations, and dividing this time by the propagation speed per unit length of the cable of the network. Lastly, the system determines the number of stations and the addresses of these stations on the network by extracting source addresses from the pertinent network frames.
摘要翻译：所公开的系统允许实时地确定高速数据通信网络的拓扑方面，而不干扰网络的操作。由本发明确定的地形信息包括网络的电缆长度，网络上的站点之间的电缆长度，以及站点地址和网络上站点的相对顺序。系统通过将网络的电缆上的网络周期的传播速度乘以网络电缆的每单位长度的传播速度来划分网络电缆的时间量，从而确定网络的电缆长度。该系统通过确定由相邻站发送的帧之间的时间长度，并将该时间除以网络的电缆每单位长度的传播速度来确定网络上任何两个相邻站之间的电缆长度。最后，系统通过从相关网络帧中提取源地址来确定站点数量和这些站点的地址。

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