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1. 发明授权

US07865786B2 Scanned memory testing of multi-port memory arrays 失效
标题翻译：多端口内存阵列的扫描内存测试
公开(公告)号：US07865786B2
公开(公告)日：2011-01-04
申请号：US12349652
申请日：2009-01-07
申请人： Robert Glen Gerowitz , Kenichi Tsuchiya
发明人： Robert Glen Gerowitz , Kenichi Tsuchiya
IPC分类号： G11C29/32 , G11C29/46
CPC分类号： G11C29/32 , G11C8/16 , G11C2029/3202
摘要： A system for at-functional-clock-speed continuous scan array built-in self testing (ABIST) of multiport memory is disclosed. During ABIST testing, functional addressing latches from a first port are used as shadow latches for a second port's addressing latches. The arrangement reduces the amount of test-only hardware on a chip and reduces the need to write complex testing software. Higher level functions may be inserted between the shadow latches and the addressing latches to automatically provide functions such as inversions.
摘要翻译：公开了一种用于多功能时钟速度连续扫描阵列内置自检（ABIST）多端口存储器的系统。在ABIST测试期间，来自第一端口的功能寻址锁存器用作第二端口寻址锁存器的阴影锁存器。这种安排减少了芯片上测试硬件的数量，并减少了编写复杂测试软件的需要。可以在阴影锁存器和寻址锁存器之间插入更高级别的功能，以自动提供诸如反转的功能。

2. 发明申请

US20100042396A1 Automated Method for Validating Manufacturing Test Rules Pertaining to an Electronic Component 有权
标题翻译：用于验证与电子部件有关的制造测试规则的自动化方法
公开(公告)号：US20100042396A1
公开(公告)日：2010-02-18
申请号：US12191538
申请日：2008-08-14
申请人： Carisa Anne Cassani , Robert Glen Gerowitz , Michael Patrick Muhlada , Chad Everett Winemiller
发明人： Carisa Anne Cassani , Robert Glen Gerowitz , Michael Patrick Muhlada , Chad Everett Winemiller
IPC分类号： G06G7/62
CPC分类号： G06F11/263 , G06F11/261
摘要： The invention is generally directed to a method and apparatus for validating a specified manufacturing test rule, which pertains to an electronic component. One embodiment comprising a method includes the step of generating a file of test data sets, wherein each test data set in the file is valid for the rule. Each test data set includes a stimulus comprising one or more single input vectors, and further includes a set of results that are expected, when the stimulus is applied to the electronic component. The method further comprises constructing a testbench to prepare each of a plurality of testcases for simulation, wherein each testcase corresponds to the stimulus and the expected output results of one of the test data sets, and each testcase is disposed to be simulated separately, or independently, from every other testcase. The method further comprises selectively preparing each of the testcases for simulation, in order to provide simulated results for the stimulus corresponding to each testcase. The expected results and the simulated results are compared for each testcase, in order to determine whether there are any differences therebetween. Each of the above steps can be carried out using means that are completely automated. Thus, the entire method for validating manufacturing test rules can likewise be completely automated. Also, the processing applied to different test cases can occur simultaneously or in parallel, to substantially reduce the processing burden.
摘要翻译：本发明一般涉及用于验证与电子部件有关的特定制造测试规则的方法和装置。包括方法的一个实施例包括生成测试数据集的文件的步骤，其中文件中设置的每个测试数据对于该规则是有效的。每个测试数据集包括包括一个或多个单个输入向量的刺激，并且还包括当将刺激应用于电子部件时预期的一组结果。该方法还包括构建测试台以准备用于模拟的多个测试箱中的每一个，其中每个测试用例对应于一个测试数据组的刺激和预期输出结果，并且每个测试用例被设置为单独模拟或独立地模拟，从每个其他测试用例。该方法还包括选择性地准备每个用于模拟的测试箱，以便提供对应于每个测试箱的刺激的模拟结果。对每个测试用例比较预期结果和模拟结果，以确定它们之间是否存在差异。可以使用完全自动化的装置来执行上述步骤中的每一个。因此，用于验证制造测试规则的整个方法同样可以完全自动化。此外，应用于不同测试用例的处理可以同时或并行地发生，从而大大减少处理负担。

3. 发明授权

US07506225B2 Scanned memory testing of multi-port memory arrays 有权
标题翻译：多端口内存阵列的扫描内存测试
公开(公告)号：US07506225B2
公开(公告)日：2009-03-17
申请号：US11250953
申请日：2005-10-14
申请人： Robert Glen Gerowitz , Kenichi Tsuchiya
发明人： Robert Glen Gerowitz , Kenichi Tsuchiya
IPC分类号： G11C29/30 , G11C29/54
CPC分类号： G11C29/32 , G11C8/16 , G11C2029/3202
摘要： A system for at-functional-clock-speed continuous scan array built-in self testing (ABIST) of multiport memory is disclosed. During ABIST testing, functional addressing latches from a first port are used as shadow latches for a second port's addressing latches. The arrangement reduces the amount of test-only hardware on a chip and reduces the need to write complex testing software. Higher level functions may be inserted between the shadow latches and the addressing latches to automatically provide functions such as inversions.
摘要翻译：公开了一种用于多功能时钟速度连续扫描阵列内置自检（ABIST）多端口存储器的系统。在ABIST测试期间，来自第一端口的功能寻址锁存器用作第二端口寻址锁存器的阴影锁存器。这种安排减少了芯片上测试硬件的数量，并减少了编写复杂测试软件的需要。可以在阴影锁存器和寻址锁存器之间插入更高级别的功能，以自动提供诸如反转的功能。

4. 发明申请

US20090116323A1 SCANNED MEMORY TESTING OF MULTI-PORT MEMORY ARRAYS 失效
标题翻译：多端口存储器阵列的扫描记忆测试
公开(公告)号：US20090116323A1
公开(公告)日：2009-05-07
申请号：US12349652
申请日：2009-01-07
申请人： Robert Glen Gerowitz , Kenichi Tsuchiya
发明人： Robert Glen Gerowitz , Kenichi Tsuchiya
IPC分类号： G11C29/00 , G11C8/16
CPC分类号： G11C29/32 , G11C8/16 , G11C2029/3202
摘要： A system for at-functional-clock-speed continuous scan array built-in self testing (ABIST) of multiport memory is disclosed. During ABIST testing, functional addressing latches from a first port are used as shadow latches for a second port's addressing latches. The arrangement reduces the amount of test-only hardware on a chip and reduces the need to write complex testing software. Higher level functions may be inserted between the shadow latches and the addressing latches to automatically provide functions such as inversions.
摘要翻译：公开了一种用于多功能时钟速度连续扫描阵列内置自检（ABIST）多端口存储器的系统。在ABIST测试期间，来自第一端口的功能寻址锁存器用作第二端口寻址锁存器的阴影锁存器。这种安排减少了芯片上测试硬件的数量，并减少了编写复杂测试软件的需要。可以在阴影锁存器和寻址锁存器之间插入更高级别的功能，以自动提供诸如反转的功能。

5. 发明授权

US06519757B1 Hardware design language generation for input/output logic level 失效
标题翻译：用于输入/输出逻辑电平的硬件设计语言生成
公开(公告)号：US06519757B1
公开(公告)日：2003-02-11
申请号：US09546982
申请日：2000-04-11
申请人： Bryan Keith Bullis , Robert Glen Gerowitz
发明人： Bryan Keith Bullis , Robert Glen Gerowitz
IPC分类号： G06F1750
CPC分类号： G06F17/5045
摘要： Descriptive statements representative of a communication level coupling the functional logic of an integrated circuit to the external environment is translated into complex functional specification language for input to hardware design programs. Plain language within the functional specifications is converted to proper design language to implement hardware described by the functional specification.
摘要翻译：表示将集成电路的功能逻辑耦合到外部环境的通信级别的描述性语句被转换成用于输入到硬件设计程序的复杂功能规范语言。功能规范中的普通语言被转换为适当的设计语言，以实现由功能规范描述的硬件。

6. 发明授权

US06407569B1 Integrated circuit with in situ circuit arrangement for testing integrity of differential receiver inputs 有权
标题翻译：具有原位电路装置的集成电路，用于测试差分接收器输入的完整性
公开(公告)号：US06407569B1
公开(公告)日：2002-06-18
申请号：US09275295
申请日：1999-03-24
申请人： Jeffrey Paul Boettler , Robert Glen Gerowitz , William Arthur Noon , Howard James Schubert, Jr. , Chad Everett Winemiller
发明人： Jeffrey Paul Boettler , Robert Glen Gerowitz , William Arthur Noon , Howard James Schubert, Jr. , Chad Everett Winemiller
IPC分类号： G01R3128
CPC分类号： G01R31/318572 , G01R31/31926
摘要： Stuck-at fault, shorted and open circuit conditions occurring in the differential inputs to Differential Receivers on a Large Scale Integrated (LSI) chip are detected by a test circuit arrangement fabricated on the chip. The test circuit arrangement includes Pass Gate devices operatively coupled to the differential inputs and an Exclusive NOR circuit (XNOR) coupled to the Pass Gate devices. Pull devices are coupled to the Pass Gate devices and the differential inputs. By activating the Pass Gate devices and applying a test sequence to the differential inputs, the state of the output of the XNOR circuit indicates if an open circuit, stuck-at or short exists in the inputs to the Differential Receiver.
摘要翻译：在大规模集成（LSI）芯片上的差分接收器的差分输入中出现的故障，短路和开路状况由芯片上制造的测试电路布置检测。测试电路装置包括可操作地耦合到差分输入的通过栅极器件和耦合到通过栅极器件的异或异或电路（XNOR）。拉动装置耦合到通过门装置和差分输入。通过激活Pass Gate器件并将测试序列应用于差分输入，XNOR电路的输出状态指示差分接收器的输入中是否存在开路，卡住或短路。

7. 发明授权

US08136059B2 Indeterminate state logic insertion 有权
标题翻译：不确定状态逻辑插入
公开(公告)号：US08136059B2
公开(公告)日：2012-03-13
申请号：US12257610
申请日：2008-10-24
申请人： Robert Glen Gerowitz , Michael Patrick Muhlada , Chad Everett Winemiller
发明人： Robert Glen Gerowitz , Michael Patrick Muhlada , Chad Everett Winemiller
IPC分类号： G06F17/50
CPC分类号： G06F17/505
摘要： Illustrative embodiments provide a computer-implemented method for resolving indeterminate states by inserting logic into a design. The computer-implemented method receives an original design input from a requester to form a received input and determines whether the received input contains an indeterminate output. Responsive to a determination that the received input contains an indeterminate output, the computer-implemented method generates a temporary design from the received input, wherein the temporary design contains “unique” output and all inputs, updates the temporary design, and synthesizes the original design and each temporary design individually to form a synthesized original design and a set of synthesized temporary designs. The computer-implemented method merges the synthesized original design with the set of synthesized temporary design to form a final design; and returns the final design to the requester.
摘要翻译：说明性实施例提供了一种用于通过将逻辑插入到设计中来解决不确定状态的计算机实现的方法。计算机实现的方法从请求者接收原始设计输入以形成接收到的输入，并确定接收的输入是否包含不确定的输出。响应于确定接收到的输入包含不确定的输出，计算机实现的方法从接收到的输入生成临时设计，其中临时设计包含“唯一”输出和所有输入，更新临时设计，并且合成原始设计和每个临时设计单独形成合成的原始设计和一组合成的临时设计。计算机实现的方法将合成原始设计与合成临时设计集合合并形成最终设计; 并将最终设计返回给请求者。

8. 发明授权

US06222380B1 High speed parallel/serial link for data communication 有权
标题翻译：用于数据通信的高速并行/串行链路
公开(公告)号：US06222380B1
公开(公告)日：2001-04-24
申请号：US09330968
申请日：1999-06-11
申请人： Robert Glen Gerowitz , Carl Thomas Gray , John Marshall , Christopher G. Riedle , Raymond Paul Rizzo
发明人： Robert Glen Gerowitz , Carl Thomas Gray , John Marshall , Christopher G. Riedle , Raymond Paul Rizzo
IPC分类号： H03K19173
CPC分类号： H03M9/00 , C22C21/08 , C22F1/047 , C22F1/05
摘要： An interface system that conveys data at approximately 500 MBitsps between modules. The interface system performs multistream serialization at the transmitter and multistream de-serialization at the Receiver. As a consequence, fewer interface connections are required between the modules.
摘要翻译：一个接口系统，可在模块之间传输大约500 MB的数据。接口系统在发射机处执行多流串行化，并在接收机处执行多流逆序列化。因此，模块之间需要更少的接口连接。

9. 发明授权

US08135571B2 Validating manufacturing test rules pertaining to an electronic component 有权
标题翻译：验证与电子元件相关的制造测试规则
公开(公告)号：US08135571B2
公开(公告)日：2012-03-13
申请号：US12191538
申请日：2008-08-14
申请人： Carisa Anne Cassani , Robert Glen Gerowitz , Michael Patrick Muhlada , Chad Everett Winemiller
发明人： Carisa Anne Cassani , Robert Glen Gerowitz , Michael Patrick Muhlada , Chad Everett Winemiller
IPC分类号： G06G7/62 , G06F9/44 , G06F13/10 , G06F17/50
CPC分类号： G06F11/263 , G06F11/261
摘要： The invention is directed to validating a specified manufacturing test rule, which pertains to an electronic component. The method includes generating a file of test data sets, wherein each test data set in the file is valid for the rule. Each test data set includes a stimulus comprising one or more single input vectors, and further includes a set of results that are expected. The method further comprises constructing a testbench to prepare testcases for simulation, wherein each testcase corresponds to the stimulus and the expected output results of one of the test data sets, and each testcase is disposed to be simulated separately, or independently, from every other testcase. The method further comprises selectively preparing each of the testcases for simulation, in order to provide simulated results for the stimulus corresponding to each testcase. The expected results and the simulated results are compared for each testcase.
摘要翻译：本发明旨在验证涉及电子部件的指定制造测试规则。该方法包括生成测试数据集的文件，其中文件中设置的每个测试数据对于该规则是有效的。每个测试数据集包括包括一个或多个单个输入向量的刺激，并且还包括预期的一组结果。该方法还包括构建测试台以准备用于模拟的测试用例，其中每个测试用例对应于一个测试数据组的激励和预期输出结果，并且每个测试用例被设置为单独地或独立地从每个其他测试用例模拟。该方法还包括选择性地准备每个用于模拟的测试箱，以便提供对应于每个测试箱的刺激的模拟结果。对每个测试用例比较预期结果和模拟结果。

10. 发明授权

US08065641B2 Automatically creating manufacturing test rules pertaining to an electronic component 有权
标题翻译：自动创建与电子元件相关的制造测试规则
公开(公告)号：US08065641B2
公开(公告)日：2011-11-22
申请号：US12203038
申请日：2008-09-02
申请人： Robert Glen Gerowitz , Michael Patrick Muhlada , Chad Everett Winemiller
发明人： Robert Glen Gerowitz , Michael Patrick Muhlada , Chad Everett Winemiller
IPC分类号： G06F17/50 , G06F9/45
CPC分类号： G06F17/5068 , G06F2217/12 , Y02P90/265
摘要： A system for creating manufacturing test rules. Stimuli for an electronic design are generated automatically by a stimuli generator. The stimuli generator takes into account certain limitations of the design when automatically generating the manufacturing test rules. The design is tested by a testbench using the stimuli. A simulation log for the design is generated by the testbench. The simulation log is then processed by a simulation log processor. An HDL representation of the design is generated by the simulation log processor using the processed simulation log. A gate-level version of the design is generated by a synthesis tool using the HDL representation of the design. The gate-level version of the design is further processed by the synthesis tool to make any necessary modifications. Then, the gate-level version of the design is outputted as the final manufacturing test rule. Thus, creating manufacturing test rules can be completely automated.
摘要翻译：用于创建制造测试规则的系统。电子设计的刺激是由刺激发生器自动产生的。当自动生成制造测试规则时，刺激发生器考虑到设计的某些限制。该设计由使用刺激的测试台进行测试。该设计的仿真日志由测试平台生成。仿真日志由仿真日志处理器处理。设计的HDL表示由仿真日志处理器使用处理的仿真日志生成。设计的门级版本由使用设计的HDL表示的综合工具生成。设计的门级版本由综合工具进一步处理，以进行任何必要的修改。然后，设计的门级版本作为最终制造测试规则输出。因此，创建制造测试规则可以完全自动化。

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