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1. 发明授权

US06927493B2 Sealing and protecting integrated circuit bonding pads 有权
公开(公告)号：US06927493B2
公开(公告)日：2005-08-09
申请号：US10678709
申请日：2003-10-03
申请人： Christo P. Bojkov , Michael L. Krumnow
发明人： Christo P. Bojkov , Michael L. Krumnow
IPC分类号： H01L23/485 , H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L24/05 , H01L24/45 , H01L24/48 , H01L2224/04042 , H01L2224/05083 , H01L2224/05111 , H01L2224/05116 , H01L2224/05118 , H01L2224/05123 , H01L2224/05124 , H01L2224/05147 , H01L2224/05155 , H01L2224/05157 , H01L2224/0516 , H01L2224/05164 , H01L2224/05556 , H01L2224/05639 , H01L2224/05644 , H01L2224/05655 , H01L2224/05664 , H01L2224/05669 , H01L2224/45014 , H01L2224/45124 , H01L2224/45139 , H01L2224/45144 , H01L2224/45147 , H01L2224/48463 , H01L2224/48639 , H01L2224/48644 , H01L2224/48655 , H01L2224/48664 , H01L2224/48669 , H01L2224/48739 , H01L2224/48755 , H01L2224/48764 , H01L2224/48769 , H01L2224/48839 , H01L2224/48844 , H01L2224/48855 , H01L2224/48864 , H01L2224/85205 , H01L2924/01007 , H01L2924/01012 , H01L2924/01013 , H01L2924/01014 , H01L2924/01018 , H01L2924/01022 , H01L2924/01023 , H01L2924/01024 , H01L2924/01027 , H01L2924/01028 , H01L2924/01029 , H01L2924/0103 , H01L2924/01031 , H01L2924/01032 , H01L2924/01033 , H01L2924/01042 , H01L2924/01046 , H01L2924/01047 , H01L2924/0105 , H01L2924/01073 , H01L2924/01074 , H01L2924/01075 , H01L2924/01076 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/05042 , H01L2924/10253 , H01L2924/14 , H01L2924/3011 , H01L2924/3025 , H01L2924/00014 , H01L2924/00 , H01L2224/48869 , H01L2224/48744
摘要： A metal structure (600) for a bonding pad on integrated circuit wafers, which have interconnecting metallization (101) protected by an insulating layer (102) and selectively exposed by windows in the insulating layer. The structure comprises a patterned seed metal layer (104) positioned on the interconnecting metallization exposed by the window so that the seed metal establishes ohmic contact to the metallization as well as a practically impenetrable seal of the interface between the seed metal and the insulating layer. Further, a metal stud (301) is formed on the seed metal and aligned with the window. The metal stud is conformally covered by a barrier metal layer (501) and an outermost bondable metal layer (502).

2. 发明授权

US07262126B2 Sealing and protecting integrated circuit bonding pads 有权
标题翻译：封装和保护集成电路焊盘
公开(公告)号：US07262126B2
公开(公告)日：2007-08-28
申请号：US11173289
申请日：2005-06-30
申请人： Christo P. Bojkov , Michael L. Krumnow
发明人： Christo P. Bojkov , Michael L. Krumnow
IPC分类号： H01L21/4763 , H01L21/44
CPC分类号： H01L24/05 , H01L24/45 , H01L24/48 , H01L2224/04042 , H01L2224/05083 , H01L2224/05111 , H01L2224/05116 , H01L2224/05118 , H01L2224/05123 , H01L2224/05124 , H01L2224/05147 , H01L2224/05155 , H01L2224/05157 , H01L2224/0516 , H01L2224/05164 , H01L2224/05556 , H01L2224/05639 , H01L2224/05644 , H01L2224/05655 , H01L2224/05664 , H01L2224/05669 , H01L2224/45014 , H01L2224/45124 , H01L2224/45139 , H01L2224/45144 , H01L2224/45147 , H01L2224/48463 , H01L2224/48639 , H01L2224/48644 , H01L2224/48655 , H01L2224/48664 , H01L2224/48669 , H01L2224/48739 , H01L2224/48755 , H01L2224/48764 , H01L2224/48769 , H01L2224/48839 , H01L2224/48844 , H01L2224/48855 , H01L2224/48864 , H01L2224/85205 , H01L2924/01007 , H01L2924/01012 , H01L2924/01013 , H01L2924/01014 , H01L2924/01018 , H01L2924/01022 , H01L2924/01023 , H01L2924/01024 , H01L2924/01027 , H01L2924/01028 , H01L2924/01029 , H01L2924/0103 , H01L2924/01031 , H01L2924/01032 , H01L2924/01033 , H01L2924/01042 , H01L2924/01046 , H01L2924/01047 , H01L2924/0105 , H01L2924/01073 , H01L2924/01074 , H01L2924/01075 , H01L2924/01076 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/05042 , H01L2924/10253 , H01L2924/14 , H01L2924/3011 , H01L2924/3025 , H01L2924/00014 , H01L2924/00 , H01L2224/48869 , H01L2224/48744
摘要： A metal structure (600) for a bonding pad on integrated circuit wafers, which have interconnecting metallization (101) protected by an insulating layer (102) and selectively exposed by windows in the insulating layer. The structure comprises a patterned seed metal layer (104) positioned on the interconnecting metallization exposed by the window so that the seed metal establishes ohmic contact to the metallization as well as a practically impenetrable seal of the interface between the seed metal and the insulating layer. Further, a metal stud (301) is formed on the seed metal and aligned with the window. The metal stud is conformally covered by a barrier metal layer (501) and an outermost bondable metal layer (502).
摘要翻译：一种用于集成电路晶片上的接合焊盘的金属结构（600），其具有由绝缘层（102）保护并且被绝缘层中的窗口选择性地暴露的互连金属化（101）。该结构包括位于由窗户暴露的互连金属化处的图案种子金属层（104），使得种子金属与金属化建立欧姆接触以及种子金属和绝缘层之间的界面的实际上不可渗透的密封。此外，金属螺柱（301）形成在种子金属上并与窗口对准。金属螺柱由阻挡金属层（501）和最外面的可粘合金属层（502）保形地覆盖。

3. 发明授权

US5947783A Method of forming a cathode assembly comprising a diamond layer 失效
标题翻译：形成包括金刚石层的阴极组件的方法
公开(公告)号：US5947783A
公开(公告)日：1999-09-07
申请号：US920011
申请日：1997-08-26
申请人： Christo P. Bojkov , Richard Lee Fink , Nalin Kumar , Alexei Tikhonski , Zvi Yaniv
发明人： Christo P. Bojkov , Richard Lee Fink , Nalin Kumar , Alexei Tikhonski , Zvi Yaniv
IPC分类号： G09G3/22 , G09G3/34 , H01J1/304 , H01J9/02 , H01J29/46
CPC分类号： H01J29/467 , G09G3/22 , H01J1/304 , H01J9/025 , H01J2201/30457 , H01J2329/00
摘要： A cathode assembly includes a substrate, a plurality of electrically conducting strips deposited on the substrate, and a continuous layer of diamond material deposited over the plurality of electrically conducting strips and portions of the substrate exposed between the plurality of electrically conducting strips.
摘要翻译：阴极组件包括衬底，沉积在衬底上的多个导电条，以及沉积在多个导电条上的连续金刚石层，以及暴露在多个导电条之间的衬底的部分。

4. 发明授权

US07271030B2 Direct bumping on integrated circuit contacts enabled by metal-to-insulator adhesion 有权
标题翻译：通过金属与绝缘体的粘接直接碰撞集成电路触点
公开(公告)号：US07271030B2
公开(公告)日：2007-09-18
申请号：US11302863
申请日：2005-12-13
申请人： Christo P. Bojkov , Orlando F. Torres
发明人： Christo P. Bojkov , Orlando F. Torres
IPC分类号： H01L21/00
CPC分类号： H01L24/12 , H01L23/3192 , H01L24/05 , H01L24/45 , H01L24/48 , H01L2224/0231 , H01L2224/0401 , H01L2224/04042 , H01L2224/05018 , H01L2224/05073 , H01L2224/05147 , H01L2224/05155 , H01L2224/05556 , H01L2224/05568 , H01L2224/05572 , H01L2224/05639 , H01L2224/05644 , H01L2224/05655 , H01L2224/05664 , H01L2224/05669 , H01L2224/13022 , H01L2224/13099 , H01L2224/45014 , H01L2224/45124 , H01L2224/45144 , H01L2224/45147 , H01L2224/48463 , H01L2224/4847 , H01L2224/48639 , H01L2224/48644 , H01L2224/48655 , H01L2224/48664 , H01L2224/48669 , H01L2224/48739 , H01L2224/48755 , H01L2224/48764 , H01L2224/48769 , H01L2224/48839 , H01L2224/48844 , H01L2224/48855 , H01L2224/48864 , H01L2924/0002 , H01L2924/01006 , H01L2924/01007 , H01L2924/01012 , H01L2924/01013 , H01L2924/01014 , H01L2924/01018 , H01L2924/01019 , H01L2924/01022 , H01L2924/01023 , H01L2924/01024 , H01L2924/01027 , H01L2924/01028 , H01L2924/01029 , H01L2924/0103 , H01L2924/01031 , H01L2924/01032 , H01L2924/01033 , H01L2924/01042 , H01L2924/01046 , H01L2924/01047 , H01L2924/01049 , H01L2924/0105 , H01L2924/01073 , H01L2924/01074 , H01L2924/01075 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01083 , H01L2924/01087 , H01L2924/014 , H01L2924/05042 , H01L2924/10253 , H01L2924/14 , H01L2924/3011 , H01L2924/00014 , H01L2924/00 , H01L2224/48869 , H01L2224/48744 , H01L2224/05552 , H01L2924/00012
摘要： A semiconductor device including a contact pad and circuit metallization on the surface of an integrated circuit (IC) chip comprises a stack of protection layers over the surface of the chip. The stack consists of a first inorganic layer (303, preferably silicon nitride) on the chip surface, followed by a polymer layer (306, preferably benzocyclobutene) on the first inorganic layer (303), and finally an outermost second inorganic layer (310, preferably silicon dioxide) on the polymer layer (303). A window (301a) in the stack of layers exposes the metallization (301) of the IC. A patterned seed metal layer (307, preferably copper) is on the metallization (301) in the window and on the second inorganic layer (310) around the window. A buffer metal layer (308, preferably copper) is positioned on the seed metal layer (307). A metal reflow element (309) is attached to the buffer metal (308).
摘要翻译：在集成电路（IC）芯片的表面上包括接触焊盘和电路金属化的半导体器件包括在芯片的表面上的一叠保护层。叠层由芯片表面上的第一无机层（303，优选氮化硅）组成，其后是第一无机层（303）上的聚合物层（306，优选苯并环丁烯），最后是最外层的第二无机层优选二氧化硅）在聚合物层（303）上。叠层中的窗口（301a）暴露了IC的金属化（301）。图案化的种子金属层（307，优选铜）在窗口上的金属化（301）和窗口周围的第二无机层（310）上。缓冲金属层（308，优选铜）位于种子金属层（307）上。金属回流元件（309）附接到缓冲金属（308）。

5. 发明授权

US08035226B1 Wafer level package integrated circuit incorporating solder balls containing an organic plastic-core 有权
标题翻译：包含含有有机塑料芯的焊球的晶圆级封装集成电路
公开(公告)号：US08035226B1
公开(公告)日：2011-10-11
申请号：US12134026
申请日：2008-06-05
申请人： Duane T. Wilcoxen , Christo P. Bojkov , Ajay Kumar Ghai , Steve Detlev Cate
发明人： Duane T. Wilcoxen , Christo P. Bojkov , Ajay Kumar Ghai , Steve Detlev Cate
IPC分类号： H01L23/48
CPC分类号： H01L24/13 , H01L23/3192 , H01L24/05 , H01L2224/02381 , H01L2224/0239 , H01L2224/024 , H01L2224/0401 , H01L2224/05571 , H01L2224/05572 , H01L2224/05624 , H01L2224/05647 , H01L2224/1319 , H01L2224/13561 , H01L2224/13582 , H01L2224/13611 , H01L2224/13639 , H01L2224/13647 , H01L2924/0002 , H01L2924/01013 , H01L2924/01023 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/0105 , H01L2924/01074 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/14 , H01L2924/351 , H01L2224/05552 , H01L2924/00
摘要： An integrated circuit including solder balls containing an elastic or resilient material core, a hard or rigid shell substantially enclosing the core, and an electrical contact layer substantially enclosing the shell. The elastic or resilient core serves as a stress buffer layer in a wafer level package (WLP) integrated circuit. The elastic or resilient material core may include an organic plastic material, such as a Divinilbenzene cross-linked co-polymer of relatively high resistance. This material has a relatively good elongation property so that it can effectively absorb forces exerted upon the integrated circuit by, for example, the flexing of a printed circuit board (PCB) or other structure to which the integrated circuit is attached. The hard or rigid shell serves to contain the elastic or resilient core and may include copper. The electrical contact layer serve to provide a good adhesive electrical contact to an under bump metallization (UBM) layer, may include a lead free, Tin-Gold (SnAg) material.
摘要翻译：一种集成电路，其包括包含弹性或弹性材料芯的焊球，基本上包围该芯的硬质或刚性外壳以及基本上围绕外壳的电接触层。弹性或弹性芯在晶片级封装（WLP）集成电路中用作应力缓冲层。弹性或弹性材料芯可以包括有机塑料材料，例如具有较高电阻的Divinilbenzene交联共聚物。该材料具有相对良好的伸长性能，使得其可以有效地吸收通过例如印刷电路板（PCB）或集成电路所连接的其它结构的弯曲来施加在集成电路上的力。硬壳或硬壳用于容纳弹性或弹性芯，并且可包括铜。电接触层用于向凸块下金属化（UBM）层提供良好的粘合电接触，可包括无铅锡 - 金（SnAg）材料。

6. 发明授权

US07005752B2 Direct bumping on integrated circuit contacts enabled by metal-to-insulator adhesion 有权
标题翻译：通过金属与绝缘体的粘接直接碰撞集成电路触点
公开(公告)号：US07005752B2
公开(公告)日：2006-02-28
申请号：US10689386
申请日：2003-10-20
申请人： Christo P. Bojkov , Orlando F. Torres
发明人： Christo P. Bojkov , Orlando F. Torres
IPC分类号： H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L24/12 , H01L23/3192 , H01L24/05 , H01L24/45 , H01L24/48 , H01L2224/0231 , H01L2224/0401 , H01L2224/04042 , H01L2224/05018 , H01L2224/05073 , H01L2224/05147 , H01L2224/05155 , H01L2224/05556 , H01L2224/05568 , H01L2224/05572 , H01L2224/05639 , H01L2224/05644 , H01L2224/05655 , H01L2224/05664 , H01L2224/05669 , H01L2224/13022 , H01L2224/13099 , H01L2224/45014 , H01L2224/45124 , H01L2224/45144 , H01L2224/45147 , H01L2224/48463 , H01L2224/4847 , H01L2224/48639 , H01L2224/48644 , H01L2224/48655 , H01L2224/48664 , H01L2224/48669 , H01L2224/48739 , H01L2224/48755 , H01L2224/48764 , H01L2224/48769 , H01L2224/48839 , H01L2224/48844 , H01L2224/48855 , H01L2224/48864 , H01L2924/0002 , H01L2924/01006 , H01L2924/01007 , H01L2924/01012 , H01L2924/01013 , H01L2924/01014 , H01L2924/01018 , H01L2924/01019 , H01L2924/01022 , H01L2924/01023 , H01L2924/01024 , H01L2924/01027 , H01L2924/01028 , H01L2924/01029 , H01L2924/0103 , H01L2924/01031 , H01L2924/01032 , H01L2924/01033 , H01L2924/01042 , H01L2924/01046 , H01L2924/01047 , H01L2924/01049 , H01L2924/0105 , H01L2924/01073 , H01L2924/01074 , H01L2924/01075 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01083 , H01L2924/01087 , H01L2924/014 , H01L2924/05042 , H01L2924/10253 , H01L2924/14 , H01L2924/3011 , H01L2924/00014 , H01L2924/00 , H01L2224/48869 , H01L2224/48744 , H01L2224/05552 , H01L2924/00012
摘要： A semiconductor device including a contact pad and circuit metallization on the surface of an integrated circuit (IC) chip comprises a stack of protection layers over the surface of the chip. The stack consists of a first inorganic layer (303, preferably silicon nitride) on the chip surface, followed by a polymer layer (306, preferably benzocyclobutene) on the first inorganic layer (303), and finally an outermost second inorganic layer (310, preferably silicon dioxide) on the polymer layer (303). A window (301a) in the stack of layers exposes the metallization (301) of the IC. A patterned seed metal layer (307, preferably copper) is on the metallization (301) in the window and on the second inorganic layer (310) around the window. A buffer metal layer (308, preferably copper) is positioned on the seed metal layer (307). A metal reflow element (309) is attached to the buffer metal (308).
摘要翻译：在集成电路（IC）芯片的表面上包括接触焊盘和电路金属化的半导体器件包括在芯片的表面上的一叠保护层。叠层由芯片表面上的第一无机层（303，优选氮化硅）组成，其后是第一无机层（303）上的聚合物层（306，优选苯并环丁烯），最后是最外层的第二无机层优选二氧化硅）在聚合物层（303）上。叠层中的窗口（301a）暴露了IC的金属化（301）。图案化的种子金属层（307，优选铜）在窗口上的金属化（301）和窗口周围的第二无机层（310）上。缓冲金属层（308，优选铜）位于种子金属层（307）上。金属回流元件（309）附接到缓冲金属（308）。

7. 发明授权

US06979647B2 Method for chemical etch control of noble metals in the presence of less noble metals 有权
标题翻译：在贵金属存在下贵金属的化学蚀刻控制方法
公开(公告)号：US06979647B2
公开(公告)日：2005-12-27
申请号：US10653548
申请日：2003-09-02
申请人： Christo P. Bojkov , Diane L. Arbuthnot , Robert F. Kunesh
发明人： Christo P. Bojkov , Diane L. Arbuthnot , Robert F. Kunesh
IPC分类号： C23F1/18 , C23F1/30 , H01L21/3213 , H01L21/60 , H01L21/44
CPC分类号： H01L24/48 , C23F1/18 , C23F1/30 , H01L21/32134 , H01L24/03 , H01L24/05 , H01L24/11 , H01L24/45 , H01L2224/0401 , H01L2224/04042 , H01L2224/05083 , H01L2224/05111 , H01L2224/05116 , H01L2224/05118 , H01L2224/05123 , H01L2224/05124 , H01L2224/05147 , H01L2224/05155 , H01L2224/05157 , H01L2224/0516 , H01L2224/05639 , H01L2224/05644 , H01L2224/05664 , H01L2224/1134 , H01L2224/11462 , H01L2224/11464 , H01L2224/1147 , H01L2224/1308 , H01L2224/13084 , H01L2224/13111 , H01L2224/13116 , H01L2224/13118 , H01L2224/13124 , H01L2224/13139 , H01L2224/13144 , H01L2224/13147 , H01L2224/13155 , H01L2224/13157 , H01L2224/1316 , H01L2224/13164 , H01L2224/13169 , H01L2224/13171 , H01L2224/45014 , H01L2224/45124 , H01L2224/45139 , H01L2224/45144 , H01L2224/45147 , H01L2224/48463 , H01L2224/48639 , H01L2224/48644 , H01L2224/48664 , H01L2224/48739 , H01L2224/48764 , H01L2224/48839 , H01L2224/48844 , H01L2224/48864 , H01L2924/00013 , H01L2924/01007 , H01L2924/01012 , H01L2924/01013 , H01L2924/01014 , H01L2924/01016 , H01L2924/01018 , H01L2924/01022 , H01L2924/01023 , H01L2924/01024 , H01L2924/01027 , H01L2924/01028 , H01L2924/01029 , H01L2924/0103 , H01L2924/01031 , H01L2924/01032 , H01L2924/01033 , H01L2924/01042 , H01L2924/01046 , H01L2924/01047 , H01L2924/0105 , H01L2924/01073 , H01L2924/01074 , H01L2924/01075 , H01L2924/01076 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/05042 , H01L2924/14 , H01L2924/3025 , H01L2924/00014 , H01L2224/13099 , H01L2924/00 , H01L2224/48744 , H01L2224/29099 , H01L2224/11901 , H01L2224/1146
摘要： A method for preparing a bonding pad on an integrated circuit wafer by the steps of depositing a conductive seed layer (104) on the bonding pad; depositing a metal layer (301, 302, and 303) over a portion of the conductive seed layer; and immersing the wafer in an etchant solution (501) to remove the portion of the seed layer not covered by the metal layer. The etchant solution contains a chelating agent that bonds ions from the seed layer. When the seed layer is copper or a refractory metal, and the metal layer is gold or palladium, the preferred chelating agent is selected from, but is not limited to, but is not limited to, the families of ethylenediaminetetraacetic acids (EDTA), 8-hydroxy-quinolines, including 8-hydroxy-quinoline-5-sulfonic acid, porphyrins, and phthalocyanines.
摘要翻译：一种通过以下步骤制备集成电路晶片上的焊盘的方法：在焊盘上沉积导电种子层（104）; 在导电种子层的一部分上沉积金属层（301,302和303）; 以及将晶片浸入蚀刻剂溶液（501）中以去除未被金属层覆盖的种子层的部分。蚀刻剂溶液含有螯合剂，其结合种子层的离子。当种子层是铜或难熔金属，并且金属层是金或钯时，优选的螯合剂选自但不限于但不限于乙二胺四乙酸（EDTA），8 - 羟基 - 喹啉，包括8-羟基 - 喹啉-5-磺酸，卟啉和酞菁。

8. 发明授权

US06504311B1 Cold-cathode cathodoluminescent lamp 失效
标题翻译：冷阴极阴极发光灯
公开(公告)号：US06504311B1
公开(公告)日：2003-01-07
申请号：US08621531
申请日：1996-03-25
申请人： Nalin Kumar , Christo P. Bojkov , Martin A. Kykta
发明人： Nalin Kumar , Christo P. Bojkov , Martin A. Kykta
IPC分类号： H05B3700
CPC分类号： H01J63/06 , H01J2893/0031
摘要： A pulsed lamp is supplied wherein electrons are supplied from a substantially flat cold cathode having low effective field emission work function and are accelerated to excite light emission from a phosphor layer on a transparent anode plate. The emission site density of the cathode and emission current characteristics vs electric field are selected to provide high light output while requiring only small duty cycle pulses from a voltage generator.
摘要翻译：提供脉冲灯，其中电子从具有低有效场发射功函数的基本平坦的冷阴极提供，并被加速以激发透明阳极板上的荧光体层的发光。选择阴极的发射部位密度和发射电流特性对电场以提供高的光输出，同时仅需要来自电压发生器的小的占空比脉冲。

9. 发明授权

US6084338A Cathode assembly with diamond particles and layer 有权
标题翻译：带金刚石颗粒和层的阴极组件
公开(公告)号：US6084338A
公开(公告)日：2000-07-04
申请号：US312548
申请日：1999-05-14
申请人： Christo P. Bojkov , Richard Lee Fink , Nalin Kumar , Alexei Tikhonski , Zvi Yaniv
发明人： Christo P. Bojkov , Richard Lee Fink , Nalin Kumar , Alexei Tikhonski , Zvi Yaniv
IPC分类号： G09G3/22 , G09G3/34 , H01J1/304 , H01J9/02 , H01J29/46 , H01J19/24 , H01J1/30
CPC分类号： H01J29/467 , G09G3/22 , H01J1/304 , H01J9/025 , H01J2201/30457 , H01J2329/00
摘要： A cathode assembly includes a substrate (1101), a plurality of electrically conductive strips (1102), nano-size diamond particles (1701), and a layer (1801) of diamond material deposited (CVD) over the diamond particles (1701).
摘要翻译：阴极组件包括衬底（1101），多个导电条（1102），纳米尺寸金刚石颗粒（1701）和在金刚石颗粒（1701）上沉积（CVD）的金刚石材料层（1801）。

10. 发明授权

US5973452A Display 失效
标题翻译：显示
公开(公告)号：US5973452A
公开(公告)日：1999-10-26
申请号：US922842
申请日：1997-08-26
申请人： Christo P. Bojkov , Richard Lee Fink , Nalin Kumar , Alexei Tikhonski , Zvi Yaniv
发明人： Christo P. Bojkov , Richard Lee Fink , Nalin Kumar , Alexei Tikhonski , Zvi Yaniv
IPC分类号： G09G3/22 , G09G3/34 , H01J1/304 , H01J9/02 , H01J29/46 , H01J1/30
CPC分类号： H01J29/467 , G09G3/22 , H01J1/304 , H01J9/025 , H01J2201/30457 , H01J2329/00
摘要： The present invention provides for a field emission device including an anode assembly and a cathode assembly, wherein the cathode assembly further includes a substrate, a plurality of electrically conducting strips deposited on the substrate, and a continuous layer of diamond material deposited over the plurality of electrically conducting strips and portions of the substrate exposed between the plurality of electrically conducting strips. The field emission device may further include a grid assembly including a perforated silicon substrate, a first dielectric layer deposited on the silicon substrate, and a first conducting layer deposited on the first dielectric layer, wherein the first dielectric layer and the first conducting layer have perforations coinciding with perforations of the silicon substrate. The grid assembly may further include a second dielectric layer deposited on an underside of the silicon substrate, wherein the second dielectric layer has perforations coinciding with perforations of the silicon substrate.
摘要翻译：本发明提供一种包括阳极组件和阴极组件的场发射装置，其中阴极组件还包括衬底，沉积在衬底上的多个导电条以及沉积在多个衬底上的金刚石材料的连续层导电条和基板的部分暴露在多个导电条之间。场发射器件还可以包括栅极组件，其包括多孔硅衬底，沉积在硅衬底上的第一介电层和沉积在第一介电层上的第一导电层，其中第一介电层和第一导电层具有穿孔与硅衬底的穿孔重合。栅格组件还可以包括沉积在硅衬底的下侧上的第二电介质层，其中第二介电层具有与硅衬底的穿孔重合的穿孔。

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