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    • 6. 发明授权
    • Apparatus and method for a fast locking phase locked loop
    • 用于快速锁定锁相环的装置和方法
    • US06236278B1
    • 2001-05-22
    • US09505028
    • 2000-02-16
    • Christian Olgaard
    • Christian Olgaard
    • H03L706
    • H03L7/1972H03L7/0898H03L7/107H03L7/18H03L7/1978Y10S331/02
    • A control circuit for causing a phase lock loop (PLL) frequency synthesizer to achieve a fast phase lock time while also providing improved loop performance during normal phase locked operation. The phase locking time of the PLL is minimized by initially configuring the PLL to operate in a fractional mode with high frequency signals presented to the inputs of the loop phase detector, thereby producing a fast phase lock time. Once the PLL has achieved phase lock, its operation mode is transitioned to either an integer mode or an open loop mode without loss of phase lock, thus causing lower frequency signals or no signals, respectively, to be presented to the inputs of the loop phase detector and thereby significantly reducing spurious signal tones.
    • 一种用于使锁相环(PLL)频率合成器实现快速锁相时间,同时在正常锁相操作期间还提供改进的环路性能的控制电路。 PLL的相位锁定时间通过初始配置PLL以分频模式工作而被最小化,其中高频信号呈现给环路相位检测器的输入,由此产生快速锁相时间。 一旦PLL已经实现锁相,其工作模式转变为整数模式或开环模式,而不会失去锁相,从而分别将低频信号或无信号提供给环路相位的输入 检测器,从而显着减少杂散信号音。
    • 8. 发明授权
    • Frequency synthesizer with digital frequency lock loop
    • 具有数字频率锁定回路的频率合成器
    • US06268780B1
    • 2001-07-31
    • US09558927
    • 2000-04-26
    • Christian OlgaardBenny Madsen
    • Christian OlgaardBenny Madsen
    • H03L708
    • H03C3/0975H03C3/0941H03C3/0958H03L7/14H03L7/181H03L2207/10
    • A frequency synthesizer with a digital frequency lock loop (FLL) having a fast frequency lock time uses a frequency counter circuit in the feedback loop to count the output signal frequency and produce frequency count data. A modulation control circuit provides modulation data and a corresponding modulation control signal for modulating the FLL signal source. A microprocessor processes the frequency count data along with the modulation data to provide a frequency control signal for controlling the nominal, or center, frequency of the FLL signal source. By processing these data together, thereby accounting for the amount of modulation applied to the FLL signal source, the center frequency can be maintained more consistently notwithstanding the presence of modulation within the feedback loop signal.
    • 具有快速锁定时间的数字频率锁定环(FLL)的频率合成器使用反馈回路中的频率计数器电路对输出信号频率进行计数并产生频率计数数据。 调制控制电路提供用于调制FLL信号源的调制数据和相应的调制控制信号。 微处理器与调制数据一起处理频率计数数据,以提供用于控制FLL信号源的标称或中心频率的频率控制信号。 通过将这些数据一起处理,从而考虑了施加到FLL信号源的调制量,即使反馈环路信号中存在调制,中心频率也可以保持一致。
    • 9. 发明授权
    • Mirror model for designing a continuous-time filter with reduced filter
noise
    • 用于设计具有降低的滤波器噪声的连续时间滤波器的电流镜模型
    • US5926060A
    • 1999-07-20
    • US644467
    • 1996-05-10
    • Christian OlgaardIvan Riis Nielsen
    • Christian OlgaardIvan Riis Nielsen
    • G05F3/26H03F3/30H03M11/04H03K17/16G05F3/16
    • H03M11/04H03F3/3001G05F3/262G05F3/265H03F2200/372
    • A current mirror model is provided for designing a continuous-time filter with reduced filter noise. The current mirror model includes an input branch having a voltage V.sub.in across a series circuit including a voltage source and a resistor of resistance value R.sub.m. The voltage source has a voltage value substantially equal to the value 4kTR.sub.m, where k is the Boltzmann constant and T is the temperature. An output branch is coupled to the input branch. The output branch has a first current source and a second current source. The first current source is controlled by the voltage V.sub.in and sources a current substantially equal to a transconductance G.sub.m of the output branch times the voltage V.sub.in. The output branch transconductance G.sub.m has a transconductance value substantially less than a value of an input branch conductance 1/R.sub.m. The second current source, coupled in parallel to the first current source, sources a current substantially equal to the value 4kTG.sub.m.
    • 提供电流镜模型用于设计具有降低的滤波器噪声的连续时间滤波器。 电流镜模型包括具有电压Vin的输入分支,该串联电路包括电压源和电阻值Rm的电阻器。 电压源具有基本上等于值4kTRm的电压值,其中k是玻耳兹曼常数,T是温度。 输出分支耦合到输入分支。 输出分支具有第一电流源和第二电流源。 第一电流源由电压Vin控制,并且将基本上等于输出分支的跨导Gm的电流源电压到电压Vin。 输出分支跨导Gm具有基本上小于输入分支电导1 / Rm的值的跨导值。 与第一电流源并联耦合的第二电流源产生基本上等于值4kTGm的电流。