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    • 2. 发明授权
    • Frequency synthesizer with digital frequency lock loop
    • 具有数字频率锁定回路的频率合成器
    • US06268780B1
    • 2001-07-31
    • US09558927
    • 2000-04-26
    • Christian OlgaardBenny Madsen
    • Christian OlgaardBenny Madsen
    • H03L708
    • H03C3/0975H03C3/0941H03C3/0958H03L7/14H03L7/181H03L2207/10
    • A frequency synthesizer with a digital frequency lock loop (FLL) having a fast frequency lock time uses a frequency counter circuit in the feedback loop to count the output signal frequency and produce frequency count data. A modulation control circuit provides modulation data and a corresponding modulation control signal for modulating the FLL signal source. A microprocessor processes the frequency count data along with the modulation data to provide a frequency control signal for controlling the nominal, or center, frequency of the FLL signal source. By processing these data together, thereby accounting for the amount of modulation applied to the FLL signal source, the center frequency can be maintained more consistently notwithstanding the presence of modulation within the feedback loop signal.
    • 具有快速锁定时间的数字频率锁定环(FLL)的频率合成器使用反馈回路中的频率计数器电路对输出信号频率进行计数并产生频率计数数据。 调制控制电路提供用于调制FLL信号源的调制数据和相应的调制控制信号。 微处理器与调制数据一起处理频率计数数据,以提供用于控制FLL信号源的标称或中心频率的频率控制信号。 通过将这些数据一起处理,从而考虑了施加到FLL信号源的调制量,即使反馈环路信号中存在调制,中心频率也可以保持一致。