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1. 发明申请

US20090104735A1 SEMICONDUCTOR PACKAGE HAVING INCREASED RESISTANCE TO ELECTROSTATIC DISCHARGE 有权
标题翻译：具有抗静电放电电阻的半导体封装
公开(公告)号：US20090104735A1
公开(公告)日：2009-04-23
申请号：US12337519
申请日：2008-12-17
申请人： Choshu Ito , William M. Loh , Rajagopalan Parthasarathy
发明人： Choshu Ito , William M. Loh , Rajagopalan Parthasarathy
IPC分类号： H01L21/50
CPC分类号： H01L23/60 , H01L23/552 , H01L24/48 , H01L24/73 , H01L2224/16225 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/73204 , H01L2224/73215 , H01L2224/73253 , H01L2224/73265 , H01L2924/00014 , H01L2924/01087 , H01L2924/14 , H01L2924/15311 , H01L2924/16152 , H01L2924/16195 , H01L2924/16251 , H01L2924/3011 , H01L2924/3025 , H01L2924/00012 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： Embodiments of the invention include a semiconductor integrated circuit package that includes a substrate having an integrated circuit die attached thereto. The package includes a ESD shield attached to the substrate. The ESD shield configured to increase the ESD hardness of the package. The ESD shield can further serve to stiffen the package to prevent warping and operate as a heat spreader.
摘要翻译：本发明的实施例包括半导体集成电路封装，其包括具有附接到其上的集成电路管芯的衬底。该封装包括附接到基板的ESD屏蔽。 ESD屏蔽被配置为增加封装的ESD硬度。 ESD屏蔽件可进一步用于加强封装以防止翘曲并作为散热器进行操作。

2. 发明授权

US07498664B2 Semiconductor package having increased resistance to electrostatic discharge 有权
标题翻译：具有增加的对静电放电的抗性的半导体封装
公开(公告)号：US07498664B2
公开(公告)日：2009-03-03
申请号：US11304862
申请日：2005-12-14
申请人： Choshu Ito , William M. Loh , Rajagopalan Parthasarathy
发明人： Choshu Ito , William M. Loh , Rajagopalan Parthasarathy
IPC分类号： H01L23/552
CPC分类号： H01L23/60 , H01L23/552 , H01L24/48 , H01L24/73 , H01L2224/16225 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/73204 , H01L2224/73215 , H01L2224/73253 , H01L2224/73265 , H01L2924/00014 , H01L2924/01087 , H01L2924/14 , H01L2924/15311 , H01L2924/16152 , H01L2924/16195 , H01L2924/16251 , H01L2924/3011 , H01L2924/3025 , H01L2924/00012 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： Embodiments of the invention include a semiconductor integrated circuit package that includes a substrate having an integrated circuit die attached thereto. The package includes a ESD shield attached to the substrate. The ESD shield configured to increase the ESD hardness of the package. The ESD shield can further serve to stiffen the package to prevent warping and operate as a heat spreader.
摘要翻译：本发明的实施例包括半导体集成电路封装，其包括具有附接到其上的集成电路管芯的衬底。该封装包括附接到基板的ESD屏蔽。 ESD屏蔽被配置为增加封装的ESD硬度。 ESD屏蔽件可进一步用于加强封装以防止翘曲并作为散热器进行操作。

3. 发明授权

US08258016B2 Semiconductor package having increased resistance to electrostatic discharge 有权
标题翻译：具有增加的对静电放电的抗性的半导体封装
公开(公告)号：US08258016B2
公开(公告)日：2012-09-04
申请号：US12337519
申请日：2008-12-17
申请人： Choshu Ito , William M. Loh , Rajagopalan Parthasarathy
发明人： Choshu Ito , William M. Loh , Rajagopalan Parthasarathy
IPC分类号： H01L21/44
CPC分类号： H01L23/60 , H01L23/552 , H01L24/48 , H01L24/73 , H01L2224/16225 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/73204 , H01L2224/73215 , H01L2224/73253 , H01L2224/73265 , H01L2924/00014 , H01L2924/01087 , H01L2924/14 , H01L2924/15311 , H01L2924/16152 , H01L2924/16195 , H01L2924/16251 , H01L2924/3011 , H01L2924/3025 , H01L2924/00012 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： Embodiments of the invention include a semiconductor integrated circuit package that includes a substrate having an integrated circuit die attached thereto. The package includes a ESD shield attached to the substrate. The ESD shield configured to increase the ESD hardness of the package. The ESD shield can further serve to stiffen the package to prevent warping and operate as a heat spreader.
摘要翻译：本发明的实施例包括半导体集成电路封装，其包括具有附接到其上的集成电路管芯的衬底。该封装包括附接到基板的ESD屏蔽。 ESD屏蔽被配置为增加封装的ESD硬度。 ESD屏蔽件可进一步用于加强封装以防止翘曲并作为散热器进行操作。

4. 发明申请

US20070132083A1 Semiconductor package having increased resistance to electrostatic discharge 有权
标题翻译：具有增加的对静电放电的抗性的半导体封装
公开(公告)号：US20070132083A1
公开(公告)日：2007-06-14
申请号：US11304862
申请日：2005-12-14
申请人： Choshu Ito , William Loh , Rajagopalan Parthasarathy
发明人： Choshu Ito , William Loh , Rajagopalan Parthasarathy
IPC分类号： H01L23/02
CPC分类号： H01L23/60 , H01L23/552 , H01L24/48 , H01L24/73 , H01L2224/16225 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/73204 , H01L2224/73215 , H01L2224/73253 , H01L2224/73265 , H01L2924/00014 , H01L2924/01087 , H01L2924/14 , H01L2924/15311 , H01L2924/16152 , H01L2924/16195 , H01L2924/16251 , H01L2924/3011 , H01L2924/3025 , H01L2924/00012 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： Embodiments of the invention include a semiconductor integrated circuit package that includes a substrate having an integrated circuit die attached thereto. The package includes a ESD shield attached to the substrate. The ESD shield configured to increase the ESD hardness of the package. The ESD shield can further serve to stiffen the package to prevent warping and operate as a heat spreader.
摘要翻译：本发明的实施例包括半导体集成电路封装，其包括具有附接到其上的集成电路管芯的衬底。该封装包括附接到基板的ESD屏蔽。 ESD屏蔽被配置为增加封装的ESD硬度。 ESD屏蔽件可进一步用于加强封装以防止翘曲并作为散热器进行操作。

5. 发明授权

US07375543B2 Electrostatic discharge testing 失效
标题翻译：静电放电试验
公开(公告)号：US07375543B2
公开(公告)日：2008-05-20
申请号：US11187401
申请日：2005-07-21
申请人： Choshu Ito , William M. Loh , Jau-Wen Chen
发明人： Choshu Ito , William M. Loh , Jau-Wen Chen
IPC分类号： G01R31/26 , H02H9/00
CPC分类号： G01R31/002
摘要： The present invention provides a system and method for electrostatic discharge (ESD) testing. The system includes a circuit that has a switch coupled to an input/output (I/O) circuit of a device under test (DUT), a charge source coupled to the switch, and a control circuit coupled to the switch, wherein the control circuit turns on the switch to discharge an ESD current from the charge source to the I/O circuit, and wherein the circuit is integrated into the DUT. According to the system and method disclosed herein, the system provides on-chip ESD testing of a DUT without requiring expensive and specialized test equipment.
摘要翻译：本发明提供一种用于静电放电（ESD）测试的系统和方法。该系统包括电路，其具有耦合到被测器件（DUT）的输入/输出（I / O）电路的开关，耦合到开关的电荷源和耦合到开关的控制电路，其中控制电路接通开关以将ESD电流从电荷源放电到I / O电路，并且其中电路集成到DUT中。根据本文公开的系统和方法，该系统提供DUT的片上ESD测试，而不需要昂贵且专门的测试设备。

6. 发明授权

US07551414B2 Electrostatic discharge series protection 失效
标题翻译：静电放电系列保护
公开(公告)号：US07551414B2
公开(公告)日：2009-06-23
申请号：US11300938
申请日：2005-12-15
申请人： William M. Loh , Choshu Ito , Jau-Wen Chen
发明人： William M. Loh , Choshu Ito , Jau-Wen Chen
IPC分类号： H02H9/00
CPC分类号： H01L27/0248
摘要： An improvement to a digital integrated circuit of the type having a functional circuit that is susceptible to damage from an electrostatic discharge. An electrostatic discharge protection element is placed in series with the functional circuit and disposed upstream in a normal direction of current flow from the functional circuit. The electrostatic discharge protection element includes at least one of a resistive choke that exhibits thermal runaway and an inductive choke.
摘要翻译：对具有易受静电放电损坏的功能电路的类型的数字集成电路的改进。静电放电保护元件与功能电路串联放置并且设置在来自功能电路的电流的正常方向的上游。静电放电保护元件包括具有热失控的电阻扼流圈和感应扼流圈中的至少一个。

7. 发明授权

US07777996B2 Circuit protection system 有权
标题翻译：电路保护系统
公开(公告)号：US07777996B2
公开(公告)日：2010-08-17
申请号：US11174135
申请日：2005-06-30
申请人： William M. Loh , Ken Doniger , Payman Zarkesh-Ha , Jau-Wen Chen , Choshu Ito
发明人： William M. Loh , Ken Doniger , Payman Zarkesh-Ha , Jau-Wen Chen , Choshu Ito
IPC分类号： H02H9/00
CPC分类号： H01L27/0266
摘要： A system and method for protecting a circuit. The system includes a protection circuit that includes an inverter and a capacitor coupled to the inverter. The inverter and the capacitor are implemented using logic circuits of a circuit core, and the inverter shunts electrostatic discharge ESD current through the capacitor. According to the system and method disclosed herein, because the protection circuit shunt circuit shunts ESD current using logic circuits of the circuit core, ESD protection is achieved while not requiring large FETs. Also, the protection circuit protects circuits against ESD events that conventional FET cannot protect.
摘要翻译：一种用于保护电路的系统和方法。该系统包括保护电路，该保护电路包括逆变器和耦合到逆变器的电容器。逆变器和电容器使用电路核心的逻辑电路实现，并且逆变器分流通过电容器的静电放电ESD电流。根据本文公开的系统和方法，由于保护电路并联电路使用电路核心的逻辑电路来分流ESD电流，所以在不需要大的FET的情况下实现ESD保护。此外，保护电路保护电路免受常规FET无法保护的ESD事件。

8. 发明申请

US20100194616A1 Systems and Methods for Synchronous, Retimed Analog to Digital Conversion 有权
标题翻译：用于同步，重定时模数转换的系统和方法
公开(公告)号：US20100194616A1
公开(公告)日：2010-08-05
申请号：US12669481
申请日：2008-06-06
申请人： Erik Chmelar , Choshu Ito , William Loh
发明人： Erik Chmelar , Choshu Ito , William Loh
IPC分类号： H03M1/12
CPC分类号： H03M1/1215 , H03M1/002 , H03M1/361
摘要： Various embodiments of the present invention provide systems and methods for analog to digital conversion. For example, a retimed analog to digital converter is disclosed that includes a first set of sub-level interleaves and a second set of sub-level interleaves. The first set of sub-level interleaves includes a first sub-level interleave with a first set of comparators synchronized to a first clock phase, and a second sub-level interleave with a second set of comparators synchronized to a second clock phase. The second set of sub-level interleaves includes a third sub-level interleave with a third set of comparators synchronized to a third clock phase, and a fourth sub-level interleave with a fourth set of comparators synchronized to a fourth clock phase. A global interleave selects one of the first set of comparators based at least in part on an output from the second set of sub-level interleaves, and one of the third set of comparators based at least in part on an output from the first set of sub-level interleaves. In some instances of the aforementioned embodiments, an output of the first sub-level interleave and an output of the second sub-level interleave are synchronized to the third clock phase, and an output of the third sub-level interleave and an output of the fourth sub-level interleave are synchronized to the first clock phase.
摘要翻译：本发明的各种实施例提供了用于模数转换的系统和方法。例如，公开了一种重新定时的模数转换器，其包括第一组子电平交织和第二组子电平交织。第一组子电平交织包括与第一时钟相位同步的第一组比较器的第一子电平交织以及与第二时钟相位同步的第二组比较器的第二子电平交织。第二组子电平交织包括与第三组比较器同步到第三时钟相位的第三子电平交织以及与第四时钟相位同步的第四组比较器的第四子电平交织。至少部分地基于来自第二组子电平交织组的输出和第三组比较器中的一个，至少部分地基于第一组比较器的输出，选择第一组比较器中的一个，子级交错。在上述实施例的一些情况下，第一子电平交织的输出和第二子电平交织的输出被同步到第三时钟相位，并且第三子电平交织的输出和第四子电平交错同步到第一时钟相位。

9. 发明授权

US07696915B2 Analog-to-digital converter having reduced number of activated comparators 有权
标题翻译：具有减少的激活的比较器数量的模数转换器
公开(公告)号：US07696915B2
公开(公告)日：2010-04-13
申请号：US12108791
申请日：2008-04-24
申请人： Erik Chmelar , Choshu Ito
发明人： Erik Chmelar , Choshu Ito
IPC分类号： H03M1/36
CPC分类号： H03M1/182 , H03M1/002 , H03M1/004 , H03M1/361 , H03M1/367
摘要： An ADC circuit includes multiple comparators and a controller coupled to the comparators. Each of the comparators is operative to generate an output indicative of a difference between a first signal representative of an input signal applied to the ADC circuit and a corresponding reference signal. The controller is operative to perform at least one of: (i) activating a subset of the comparators during a given sample period being; and (ii) controlling levels of the corresponding reference signals of the comparators as a function of a level of the input signal. A number of active comparators during the given sample period is no greater than one less than a number of regions into which the input signal is quantized.
摘要翻译： ADC电路包括多个比较器和耦合到比较器的控制器。每个比较器可操作以产生指示表示施加到ADC电路的输入信号的第一信号与对应的参考信号之间的差的输出。控制器可操作以执行以下至少之一：（i）在给定的采样周期期间激活比较器的子集; 和（ii）根据输入信号的电平来控制比较器的相应参考信号的电平。给定采样周期内的多个有源比较器不小于输入信号被量化的区域数量的一个。

10. 发明申请

US20090296292A1 Electrostatic Discharge Protection Circuit Employing a Micro Electro-Mechanical Systems (MEMS) Structure 有权
标题翻译：采用微机电系统（MEMS）结构的静电放电保护电路
公开(公告)号：US20090296292A1
公开(公告)日：2009-12-03
申请号：US12128108
申请日：2008-05-28
申请人： Tze Wee Chen , William Loh , Choshu Ito
发明人： Tze Wee Chen , William Loh , Choshu Ito
IPC分类号： H02H9/00 , H01H59/00
CPC分类号： H01H59/0009 , H02H9/046
摘要： An ESD protection circuit for protecting a host circuit coupled to a signal pad from an ESD event occurring at the signal pad includes at least one MEMS switch which is electrically connected to the signal pad. The MEMS switch includes a first contact structure adapted for connection to the signal pad, and a second contact structure adapted for connection to a voltage supply source. The first and second contact structures are coupled together during the ESD event for shunting an ESD current from the signal pad to the voltage supply source. The first and second contact structures are electrically isolated from one another in the absence of the ESD event. At least one of the first and second contact structures includes a passivation layer for reducing contact adhesion between the first and second contact structures.
摘要翻译：用于保护耦合到信号垫的主机电路与在信号焊盘处发生的ESD事件的ESD保护电路包括至少一个电连接到信号焊盘的MEMS开关。 MEMS开关包括适于连接到信号焊盘的第一接触结构和适于连接到电压源的第二接触结构。在ESD事件期间，第一和第二接触结构耦合在一起，用于将ESD电流从信号焊盘分流到电压源。在没有ESD事件的情况下，第一和第二接触结构彼此电隔离。第一和第二接触结构中的至少一个包括用于减小第一和第二接触结构之间的接触粘附的钝化层。

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