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1. 发明授权

US08012821B2 Semiconductor embedded resistor generation 有权
标题翻译：半导体嵌入式电阻器生成
公开(公告)号：US08012821B2
公开(公告)日：2011-09-06
申请号：US12364764
申请日：2009-02-03
申请人： Choongryul Ryou , Seunghwan Lee , Jun Yuan , Victor Chan , Manfred Eller , Nam Sung Kim , Narasimhulu Kanike , Srikanth Balaji Samavedam
发明人： Choongryul Ryou , Seunghwan Lee , Jun Yuan , Victor Chan , Manfred Eller , Nam Sung Kim , Narasimhulu Kanike , Srikanth Balaji Samavedam
IPC分类号： H01L21/8238
CPC分类号： H01L27/0629 , H01L23/5256 , H01L28/20 , H01L2924/0002 , H01L2924/00
摘要： Generating an embedded resistor in a semiconductor device includes forming a shallow trench isolation (STI) region in a substrate; forming a pad oxide on the STI region and substrate; depositing a silicon layer on the pad oxide; forming a photo-resist mask on a portion of the silicon layer disposed above the STI region; etching the silicon layer to yield a polyconductor above the STI region; oxidizing the polyconductor; depositing an oxide material or a metal gate material on the oxidized surface; depositing a silicon layer on the oxide material or metal gate material; depositing additional silicon on a portion of the silicon layer above the STI region; patterning a transistor gate with a photo-resist mask on another portion of the silicon layer away from the STI region; and etching the silicon layer to yield a transistor structure away from the STI region and a resistor structure above the STI region.
摘要翻译：在半导体器件中产生嵌入式电阻器包括在衬底中形成浅沟槽隔离（STI）区域; 在STI区和衬底上形成衬垫氧化物; 在衬垫氧化物上沉积硅层; 在设置在STI区域上方的硅层的一部分上形成光刻胶掩模; 蚀刻硅层以在STI区域上方产生多导体; 氧化多导体; 在氧化表面上沉积氧化物材料或金属栅极材料; 在氧化物材料或金属栅极材料上沉积硅层; 在STI区域上方的硅层的一部分上沉积附加的硅; 在硅层的远离STI区域的另一部分上形成具有光致抗蚀剂掩模的晶体管栅极; 并蚀刻硅层以产生远离STI区域的晶体管结构和在STI区域上方的电阻器结构。

2. 发明申请

US20100197106A1 SEMICONDUCTOR EMBEDDED RESISTOR GENERATION 有权
标题翻译：半导体嵌入式电阻发生器
公开(公告)号：US20100197106A1
公开(公告)日：2010-08-05
申请号：US12364764
申请日：2009-02-03
申请人： Choongryul Ryou , Seunghwan Lee , Jun Yuan , Victor Chan , Manfred Eller , Nam Sung Kim , Narasimhulu Kanike , Srikanth Balaji Samavedam
发明人： Choongryul Ryou , Seunghwan Lee , Jun Yuan , Victor Chan , Manfred Eller , Nam Sung Kim , Narasimhulu Kanike , Srikanth Balaji Samavedam
IPC分类号： H01L21/76 , G06F17/50
CPC分类号： H01L27/0629 , H01L23/5256 , H01L28/20 , H01L2924/0002 , H01L2924/00
摘要： A method for generating an embedded resistor in a semiconductor device and related computer-readable storage medium are provided, the method and program steps of the medium including forming a shallow trench isolation (STI) region in a substrate; forming a pad oxide on the STI region and substrate; depositing a silicon layer on the pad oxide; forming a photo-resist mask on a portion of the silicon layer disposed substantially above the STI region.; etching the silicon layer to yield a polyconductor (PC) disposed substantially above the STI region; oxidizing the PC; depositing at least one of an oxide material or a metal gate material on the oxidized surface; depositing a silicon layer on the at least one oxide material or metal gate material; depositing additional silicon on a portion of the silicon layer disposed substantially above the STI region; patterning a transistor gate with a photo-resist mask disposed on another portion of the silicon layer disposed substantially away from the STI region; and etching the silicon layer to yield at least one transistor structure disposed substantially away from the STI region and at least one resistor structure disposed substantially above the STI region.
摘要翻译：提供了一种用于在半导体器件和相关的计算机可读存储介质中产生嵌入式电阻器的方法，所述介质的方法和程序步骤包括在衬底中形成浅沟槽隔离（STI）区域; 在STI区和衬底上形成衬垫氧化物; 在衬垫氧化物上沉积硅层; 在基本上位于STI区域上方的硅层的一部分上形成光刻胶掩模; 蚀刻硅层以产生基本上位于STI区域上方的多导体（PC）; 氧化PC; 在氧化表面上沉积氧化物材料或金属栅极材料中的至少一种; 在所述至少一种氧化物材料或金属栅极材料上沉积硅层; 在基本上位于STI区域上方的硅层的一部分上沉积附加的硅; 图案化具有设置在基本上远离STI区域设置在硅层的另一部分上的光致抗蚀剂掩模的晶体管栅极; 并且蚀刻所述硅层以产生基本上远离所述STI区域布置的至少一个晶体管结构以及基本上设置在所述STI区域上的至少一个电阻器结构。

3. 发明申请

US20100237425A1 High Threshold Voltage NMOS Transistors For Low Power IC Technology 有权
标题翻译：用于低功率IC技术的高阈值电压NMOS晶体管
公开(公告)号：US20100237425A1
公开(公告)日：2010-09-23
申请号：US12727312
申请日：2010-03-19
申请人： Victor W.C. Chan , Narasimhulu Kanike , Huiling Shang , Varadarajan Vidya , Jun Yuan , Roger Allen Booth, JR.
发明人： Victor W.C. Chan , Narasimhulu Kanike , Huiling Shang , Varadarajan Vidya , Jun Yuan , Roger Allen Booth, JR.
IPC分类号： H01L27/092 , H01L21/8238
CPC分类号： H01L21/823807 , H01L21/823412
摘要： Transistors exhibiting different electrical characteristics such as different switching threshold voltage or different leakage characteristics are formed on the same chip or wafer by selectively removing a film or layer which can serve as an out-diffusion sink for an impurity region such as a halo implant and out-diffusing an impurity such as boron into the out-diffusion sink, leaving the impurity region substantially intact where the out-diffusion sink has been removed. In forming CMOS integrated circuits, such a process allows substantially optimal design for both low-leakage and low threshold transistors and allows a mask and additional associated processes to be eliminated, particularly where a tensile film is employed to increase electron mobility since the tensile film can be removed from selected NMOS transistors concurrently with removal of the tensile film from PMOS transistors.
摘要翻译：通过选择性地去除可以用作杂质区域的外扩散阱的膜或层，形成具有不同电特性的晶体管，例如不同的开关阈值电压或不同的泄漏特性在相同的芯片或晶片上，将诸如硼之类的杂质引入扩散槽中，使外扩散槽已经被去除时留下杂质区域基本完整。在形成CMOS集成电路中，这种工艺允许低泄漏和低阈值晶体管的基本上最佳设计，并允许消除掩模和附加的相关工艺，特别是在使用拉伸膜来增加电子迁移率的情况下，因为拉伸膜可以从PMOS晶体管去除拉伸膜同时从选定的NMOS晶体管中去除。

4. 发明授权

US08969969B2 High threshold voltage NMOS transistors for low power IC technology 有权
公开(公告)号：US08969969B2
公开(公告)日：2015-03-03
申请号：US12727312
申请日：2010-03-19
申请人： Victor W. C. Chan , Narasimhulu Kanike , Huiling Shang , Varadarajan Vidya , Jun Yuan , Roger Allen Booth, Jr.
发明人： Victor W. C. Chan , Narasimhulu Kanike , Huiling Shang , Varadarajan Vidya , Jun Yuan , Roger Allen Booth, Jr.
IPC分类号： H01L27/092 , H01L21/8234 , H01L21/8238
CPC分类号： H01L21/823807 , H01L21/823412
摘要： Transistors exhibiting different electrical characteristics such as different switching threshold voltage or different leakage characteristics are formed on the same chip or wafer by selectively removing a film or layer which can serve as an out-diffusion sink for an impurity region such as a halo implant and out-diffusing an impurity such as boron into the out-diffusion sink, leaving the impurity region substantially intact where the out-diffusion sink has been removed. In forming CMOS integrated circuits, such a process allows substantially optimal design for both low-leakage and low threshold transistors and allows a mask and additional associated processes to be eliminated, particularly where a tensile film is employed to increase electron mobility since the tensile film can be removed from selected NMOS transistors concurrently with removal of the tensile film from PMOS transistors.

5. 发明授权

US08377763B2 Poly resistor and metal gate fabrication and structure 有权
标题翻译：聚电阻和金属栅极的制造和结构
公开(公告)号：US08377763B2
公开(公告)日：2013-02-19
申请号：US12960593
申请日：2010-12-06
申请人： Narasimhulu Kanike
发明人： Narasimhulu Kanike
IPC分类号： H01L21/00 , H01L21/84 , H01L27/01 , H01L21/12 , H01L31/0392
CPC分类号： H01L27/0629 , H01L28/20
摘要： A method is provided for fabricating a microelectronic device and a resistor on a substrate. The method can include forming device regions in a monocrystalline semiconductor region of a substrate, in which the device regions have edges defined according to a first semiconductor feature overlying a major surface of the semiconductor region. A dielectric region is formed having a planarized surface overlying the semiconductor region and overlying a second semiconductor feature disposed above a surface of an isolation region in the substrate. The surface of the isolation region can be disposed below the major surface. The method can further include removing at least a portion of the first semiconductor feature exposed at the planarized surface of the dielectric region to form an opening and forming a gate at least partially within the opening. Thereafter, further processing can include forming electrically conductive contacts extending through apertures in the dielectric region to the second semiconductor feature and the device regions, respectively. The step of forming electrically conductive contacts may include forming silicide regions contacting portions of the second semiconductor feature and the device regions, respectively. In such way, the method can define a resistor having a current path through the second semiconductor feature, and a microelectronic device including the gate and the device regions.
摘要翻译：提供了一种在衬底上制造微电子器件和电阻器的方法。该方法可以包括在衬底的单晶半导体区域中形成器件区域，其中器件区域具有根据覆盖半导体区域的主表面的第一半导体特征限定的边缘。形成具有覆盖在半导体区域上的平坦化表面并覆盖设置在衬底中的隔离区域的表面上方的第二半导体特征的电介质区域。隔离区域的表面可以设置在主表面的下方。该方法还可以包括去除暴露在电介质区域的平坦化表面处的第一半导体特征的至少一部分以形成开口并且至少部分地在开口内形成栅极。此后，进一步的处理可以包括分别形成延伸穿过介质区域中的孔的导电触头到第二半导体特征和器件区域。形成导电触点的步骤可以包括分别形成接触第二半导体特征部分和器件区域的硅化物区域。以这种方式，该方法可以限定具有穿过第二半导体特征的电流路径的电阻器，以及包括栅极和器件区域的微电子器件。

6. 发明授权

US08779511B2 Integration of fin-based devices and ETSOI devices 有权
标题翻译：集成了鳍式设备和ETSOI设备
公开(公告)号：US08779511B2
公开(公告)日：2014-07-15
申请号：US13530887
申请日：2012-06-22
申请人： Narasimhulu Kanike , Kangguo Cheng , Ramachandra Divakaruni , Carl J. Radens
发明人： Narasimhulu Kanike , Kangguo Cheng , Ramachandra Divakaruni , Carl J. Radens
IPC分类号： H01L27/088
CPC分类号： H01L27/1211 , H01L21/845
摘要： Thin semiconductor regions and thick semiconductor regions are formed oven an insulator layer. Thick semiconductor regions include at least one semiconductor fin. A gate conductor layer is patterned to form disposable planar gate electrodes over ETSOI regions and disposable side gate electrodes on sidewalls of semiconductor fins. End portions of the semiconductor fins are vertically recessed to provide thinned fin portions adjacent to an unthinned fin center portion. After appropriate masking by dielectric layers, selective epitaxy is performed on planar source and drain regions of ETSOI field effect transistors (FETs) to form raised source and drain regions. Further, fin source and drain regions are grown on the thinned fin portions. Source and drain regions, fins, and the disposable gate electrodes are planarized. The disposable gate electrodes are replaced with metal gate electrodes. FinFETs and ETSOI FETs are provided on the same semiconductor substrate.
摘要翻译：薄半导体区域和厚半导体区域被形成为绝缘体层。厚半导体区域包括至少一个半导体鳍片。图案化栅极导体层以在半导体鳍片的侧壁上的ETSOI区域和一次侧栅电极上形成一次性平面栅电极。半导体翅片的端部垂直凹入，以提供与未固定的翅片中心部分相邻的变薄的翅片部分。在通过介电层适当掩蔽之后，在ETSOI场效应晶体管（FET）的平面源极和漏极区域上进行选择性外延以形成升高的源极和漏极区域。此外，翅片源极和漏极区域在薄的鳍部上生长。源极和漏极区域，鳍片和一次性栅电极被平坦化。一次性栅电极被金属栅电极代替。 FinFET和ETSOI FET设置在相同的半导体衬底上。

7. 发明授权

US08377790B2 Method of fabricating an embedded polysilicon resistor and an embedded eFuse isolated from a substrate 有权
标题翻译：制造嵌入式多晶硅电阻器和从基板隔离的嵌入式eFuse的方法
公开(公告)号：US08377790B2
公开(公告)日：2013-02-19
申请号：US13014995
申请日：2011-01-27
申请人： Narasimhulu Kanike , Mark R. Visokay , Oh-Jung Kwon
发明人： Narasimhulu Kanike , Mark R. Visokay , Oh-Jung Kwon
IPC分类号： H01L21/20
CPC分类号： H01L28/20 , H01L21/76224 , H01L23/5256 , H01L27/0629 , H01L2924/0002 , H01L2924/00
摘要： A method includes providing a substrate having insulating layers thereon; forming a first trench in a first region of the substrate and a second trench in a second region of the substrate; thermally growing layers of oxide along the sides of the trenches; filling the first trench and the second trench with a polysilicon material, planarizing the polysilicon material, and creating a shallow trench isolation between the first region and the second region, wherein the step f) of creating the shallow trench isolation is performed only after the steps of d) filling and e) planarizing.
摘要翻译：一种方法包括提供其上具有绝缘层的基板; 在所述衬底的第一区域中形成第一沟槽和在所述衬底的第二区域中形成第二沟槽; 沿着沟槽的侧面的氧化物的热生长层; 用多晶硅材料填充第一沟槽和第二沟槽，平坦化多晶硅材料，以及在第一区域和第二区域之间产生浅沟槽隔离，其中仅在步骤之后才执行产生浅沟槽隔离的步骤f）的d）填充和e）平面化。

8. 发明申请

US20150325647A1 INTEGRATED CIRCUIT (IC) CHIP HAVING BOTH METAL AND SILICON GATE FIELD EFFECT TRANSISTORs (FETs) AND METHOD OF MANUFACTURE 审中-公开
标题翻译：具有两个金属和硅栅的集成电路（IC）芯片场效应晶体管（FET）及其制造方法
公开(公告)号：US20150325647A1
公开(公告)日：2015-11-12
申请号：US14663256
申请日：2015-03-19
申请人： Narasimhulu Kanike
发明人： Narasimhulu Kanike
IPC分类号： H01L29/06 , H01L23/525 , H01L29/423 , H01L29/49 , H01L29/161 , H01L29/45 , H01L27/12 , H01L29/51
CPC分类号： H01L29/0653 , H01L21/82345 , H01L21/823842 , H01L21/84 , H01L23/5256 , H01L27/0629 , H01L27/0922 , H01L27/1203 , H01L29/161 , H01L29/42364 , H01L29/458 , H01L29/4941 , H01L29/517 , H01L2924/0002 , H01L2924/00
摘要： Field Effect Transistors (FETs), Integrated Circuit (IC) chips including the FETs, and a method of forming the FETs on ICs. FET locations are defined on a layered semiconductor wafer, preferably a Silicon On Insulator (SOI) wafer. One or more FET locations are defined as silicon gate locations and remaining as Replacement Metal Gate (RMG) FET locations with at least one of each on the IC. Polysilicon gates are formed in all FET locations. Gates in silicon gate locations are tailored, e.g., doped and silicided. Remaining polysilicon gates are replaced with metal in RMG FET locations. FETs are connected together into circuits with RMG FETs being connected to silicon gate FETs.
摘要翻译：场效应晶体管（FET），包括FET的集成电路（IC）芯片，以及在IC上形成FET的方法。 FET位置限定在分层半导体晶片，优选绝缘体上硅（SOI）晶片上。一个或多个FET位置被定义为硅栅极位置，并且作为替换金属栅极（RMG）FET位置保留，其中IC至少有一个FET位置。多晶硅栅极形成在所有FET位置。硅栅极位置的栅极被定制，例如掺杂和硅化。剩余的多晶硅栅极被RMG FET位置中的金属所取代。 FET连接在一起成为电路，其中RMG FET连接到硅栅极FET。

9. 发明申请

US20140048881A1 Method of Manufacturing a Body-Contacted SOI FINFET 有权
标题翻译：制造体接触SOI FINFET的方法
公开(公告)号：US20140048881A1
公开(公告)日：2014-02-20
申请号：US13587288
申请日：2012-08-16
申请人： Narasimhulu Kanike , Deleep R. Nair
发明人： Narasimhulu Kanike , Deleep R. Nair
IPC分类号： H01L27/12 , H01L21/20
CPC分类号： H01L29/785 , H01L29/66545 , H01L29/66795 , H01L29/78615
摘要： A semiconductor structure including a body-contacted finFET device and methods form manufacturing the same. The method may include forming one or more semiconductor fins on a SOI substrate, forming a semiconductive body contact region connected to the bottom of the fin(s) in the buried insulator region, forming a sacrificial gate structure over the body region of the fin(s), forming a source region on one end of the fin(s), forming a drain region on the opposite end of the fin(s), replacing the sacrificial gate structure with a metal gate, and forming electrical contacts to the source, drain, metal gate, and body contact region. The method may further include forming a body contact fin contemporaneously with the finFET fins that is in contact with the body contact region, through which electrical contact to the body contact region is made.
摘要翻译：包括体接触finFET器件的半导体结构及其制造方法。该方法可以包括在SOI衬底上形成一个或多个半导体鳍片，形成连接到掩埋绝缘体区域中的鳍状物的底部的半导体本体接触区域，在鳍片的身体区域上形成牺牲栅极结构在鳍的一端形成源区，在鳍的相对端形成漏极区，用金属栅取代牺牲栅结构，并形成与源的电接触，漏极，金属栅极和身体接触区域。该方法还可以包括与与主体接触区域接触的finFET翅片同时形成身体接触鳍片，通过该鳍片与身体接触区域进行电接触。

10. 发明授权

US08236634B1 Integration of fin-based devices and ETSOI devices 有权
标题翻译：集成了鳍式设备和ETSOI设备
公开(公告)号：US08236634B1
公开(公告)日：2012-08-07
申请号：US13050023
申请日：2011-03-17
申请人： Narasimhulu Kanike , Kangguo Cheng , Ramachandra Divakaruni , Carl J. Radens
发明人： Narasimhulu Kanike , Kangguo Cheng , Ramachandra Divakaruni , Carl J. Radens
IPC分类号： H01L27/088
CPC分类号： H01L27/1211 , H01L21/845
摘要： Thin semiconductor regions and thick semiconductor regions are formed oven an insulator layer. Thick semiconductor regions include at least one semiconductor fin. A gate conductor layer is patterned to form disposable planar gate electrodes over ETSOI regions and disposable side gate electrodes on sidewalls of semiconductor fins. End portions of the semiconductor fins are vertically recessed to provide thinned fin portions adjacent to an unthinned fin center portion. After appropriate masking by dielectric layers, selective epitaxy is performed on planar source and drain regions of ETSOI field effect transistors (FETs) to form raised source and drain regions. Further, fin source and drain regions are grown on the thinned fin portions. Source and drain regions, fins, and the disposable gate electrodes are planarized. The disposable gate electrodes are replaced with metal gate electrodes. FinFETs and ETSOI FETs are provided on the same semiconductor substrate.
摘要翻译：薄半导体区域和厚半导体区域被形成为绝缘体层。厚半导体区域包括至少一个半导体鳍片。图案化栅极导体层以在半导体鳍片的侧壁上的ETSOI区域和一次侧栅电极上形成一次性平面栅电极。半导体翅片的端部垂直凹入，以提供与未固定的翅片中心部分相邻的变薄的翅片部分。在通过介电层适当掩蔽之后，在ETSOI场效应晶体管（FET）的平面源极和漏极区域上进行选择性外延以形成升高的源极和漏极区域。此外，翅片源极和漏极区域在薄的鳍部上生长。源极和漏极区域，鳍片和一次性栅电极被平坦化。一次性栅电极被金属栅电极代替。 FinFET和ETSOI FET设置在相同的半导体衬底上。

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