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1. 发明授权

US6117748A Dishing free process for shallow trench isolation 失效
标题翻译：用于浅沟槽隔离的免洗工艺
公开(公告)号：US6117748A
公开(公告)日：2000-09-12
申请号：US60771
申请日：1998-04-15
申请人： Chine-Gie Lou , Yeur-Luen Tu , Ko-Hsing Chang
发明人： Chine-Gie Lou , Yeur-Luen Tu , Ko-Hsing Chang
IPC分类号： H01L21/762 , H01L21/76
CPC分类号： H01L21/76224
摘要： A thin silicon dioxide layer is formed on a substrate to act as a pad oxide layer. Subsequently, a Si.sub.3 N.sub.4 or BN layer is deposited on the pad oxide layer. An in situ doped polysilicon layer is deposited on the Si.sub.3 N.sub.4 or BN layer. A trench is formed in the substrate. An oxide liner is formed along the walls of the trench and on the surface of the in situ doped polysilicon layer. A CVD oxide layer is formed on the oxide liner and refilled into the trench. A two-step chemical mechanical polishing (CMP) removes the layers to the surface of the Si.sub.3 N.sub.4 or BN layer. The first step of the two-step CMP is an oxide slurry CMP that is stopped at about 100 to 500 angstroms from the in situ doped polysilicon layer. The second step of the two-step CMP is a poly slurry CMP that is controlled to stop at the surface of the Si.sub.3 N.sub.4 or BN layer.
摘要翻译：在基板上形成薄的二氧化硅层，作为衬垫氧化物层。随后，在衬垫氧化物层上沉积Si 3 N 4或BN层。在Si 3 N 4或BN层上沉积原位掺杂多晶硅层。在衬底中形成沟槽。沿着沟槽的壁和原位掺杂的多晶硅层的表面上形成氧化物衬垫。在氧化物衬垫上形成CVD氧化层，并重新填充到沟槽中。两步化学机械抛光（CMP）去除层到Si3N4或BN层的表面。两步CMP的第一步是从原位掺杂的多晶硅层停止在约100至500埃处的氧化物浆料CMP。两步CMP的第二步是控制在Si3N4或BN层表面停止的聚浆料CMP。

2. 发明授权

US6107139A Method for making a mushroom shaped DRAM capacitor 失效
标题翻译：制造蘑菇状DRAM电容器的方法
公开(公告)号：US6107139A
公开(公告)日：2000-08-22
申请号：US118170
申请日：1998-07-17
申请人： Yeur-Luen Tu , Chine-Gie Lou
发明人： Yeur-Luen Tu , Chine-Gie Lou
IPC分类号： H01L21/02 , H01L21/8242 , H01L21/44 , H01L27/108
CPC分类号： H01L28/82 , H01L27/10852 , H01L28/87 , H01L28/91
摘要： A method of forming a capacitor for a DRAM memory cell is disclosed. The method comprises the steps of forming a crown shaped capacitor being partially filled with oxide. Next, nitride spacers and polysilicon spacers are formed on the sides of crown capacitor. The remaining oxide is removed and then the oxide spacers are removed to leave a mushroom shaped bottom storage node. A dielectric is deposited and a top conductive node is deposited to complete the capacitor.
摘要翻译：公开了一种形成用于DRAM存储单元的电容器的方法。该方法包括形成部分填充有氧化物的冠状电容器的步骤。接下来，在冠电容器的侧面上形成氮化物间隔物和多晶硅间隔物。除去剩余的氧化物，然后除去氧化物间隔物以留下蘑菇状底部储存节点。沉积电介质并沉积顶部导电节点以完成电容器。

3. 发明授权

US06187486B1 Method of multi-exposure for improving photolithography resolution 有权
标题翻译：用于提高光刻分辨率的多曝光方法
公开(公告)号：US06187486B1
公开(公告)日：2001-02-13
申请号：US09250766
申请日：1999-02-16
申请人： Jun-Cheng Lai , Yeur-Luen Tu , Chine-Gie Lou
发明人： Jun-Cheng Lai , Yeur-Luen Tu , Chine-Gie Lou
IPC分类号： G03F900
CPC分类号： G03F7/70466 , G03F7/2022 , G03F7/203
摘要： A multi-exposure process. By performing the multi-exposure process, the size of the line width can be enlarged or shrunk by the precondition of the fixed pitch. Moreover, the line width can be shrunk to a level even smaller than the resolving power of the stepper or the scanner. Additionally, by using the invention, the exposure energy, the exposure time and the exposure DOF can be fixed while the exposure process is performed. Therefore, the process window is increased and the yield is enhanced. Furthermore, the processing sequence according to the invention is simpler than the conventional photolithography processing sequence, so that the throughput can be increased.
摘要翻译：多曝光过程。通过进行多次曝光处理，可以通过固定间距的前提来扩大或缩小线宽的尺寸。此外，线宽可以缩小到甚至小于步进器或扫描仪的分辨率的水平。此外，通过使用本发明，可以在执行曝光处理时固定曝光能量，曝光时间和曝光DOF。因此，处理窗口增加，产量提高。此外，根据本发明的处理顺序比常规的光刻处理顺序更简单，从而可以提高吞吐量。

4. 发明授权

US5916823A Method for making dual damascene contact 失效
标题翻译：双镶嵌接触方法
公开(公告)号：US5916823A
公开(公告)日：1999-06-29
申请号：US170859
申请日：1998-10-13
申请人： Chine-Gie Lou , Yeur-Luen Tu
发明人： Chine-Gie Lou , Yeur-Luen Tu
IPC分类号： H01L21/768 , H01L21/32 , C25D11/04
CPC分类号： H01L21/76831 , H01L21/7681 , H01L21/76832
摘要： A method for forming a dual damascene structure on a substrate is disclosed. The method comprises the steps of: forming a liner oxide layer onto the substrate; forming a first low k dielectric layer atop the liner oxide layer; forming a cap oxide layer atop the first low k dielectric layer; forming a first nitride layer atop the cap oxide layer; patterning and etching the first nitride layer to form a contact opening; forming a second low k dielectric layer into the contact opening and atop the first nitride layer; forming a second nitride layer atop the second low k dielectric layer; forming a photoresist layer atop the second nitride layer; patterning and developing the photoresist layer to expose a trench opening, wherein the trench opening is of different dimension than the contact opening; forming a dual damascene opening by etching the second nitride layer and the second low k dielectric layer, using the photoresist layer as a mask, and by etching the cap oxide layer, the first low k dielectric layer and the liner oxide layer, using the first nitride layer as a mask; stripping the photoresist layer; forming oxide sidewall spacers into the dual damascene opening; and depositing a conductive layer into the dual damascene opening.
摘要翻译：公开了一种在衬底上形成双镶嵌结构的方法。该方法包括以下步骤：在衬底上形成衬垫氧化物层; 在衬垫氧化物层的上方形成第一低k电介质层; 在第一低k电介质层的顶部形成帽氧化物层; 在所述盖氧化物层顶上形成第一氮化物层; 图案化和蚀刻第一氮化物层以形成接触开口; 在所述接触开口中和所述第一氮化物层的顶上形成第二低k电介质层; 在所述第二低k电介质层的顶部形成第二氮化物层; 在所述第二氮化物层的顶部形成光致抗蚀剂层; 图案化和显影光致抗蚀剂层以露出沟槽开口，其中沟槽开口的尺寸与接触开口不同; 通过使用所述光致抗蚀剂层作为掩模蚀刻所述第二氮化物层和所述第二低k电介质层，并且通过使用所述第一低k介电层和所述衬底氧化物层蚀刻所述第一低k电介质层和所述衬里氧化物层来形成双镶嵌开口氮化物层作为掩模; 剥离光致抗蚀剂层; 在所述双镶嵌开口中形成氧化物侧壁间隔物; 以及将导电层沉积到双镶嵌开口中。

5. 发明授权

US6100129A Method for making fin-trench structured DRAM capacitor 有权
标题翻译：制造鳍沟结构DRAM电容的方法
公开(公告)号：US6100129A
公开(公告)日：2000-08-08
申请号：US189353
申请日：1998-11-09
申请人： Yeur-Luen Tu , Chine-Gie Lou
发明人： Yeur-Luen Tu , Chine-Gie Lou
IPC分类号： H01L21/02 , H01L21/8242 , H01L21/8244
CPC分类号： H01L28/82 , H01L27/10852 , H01L28/87 , H01L28/91
摘要： A method for manufacturing a fin-trench capacitor is disclosed. The method comprises the steps of: forming a plurality of alternating oxide and nitride layers including a top oxide layer, wherein said nitride layers are sandwiched between said oxide layers; forming a storage node contact opening in said plurality of alternating oxide and nitride layers, stopping at said landing pad; removing a portion of said nitride layers along sidewalls of said contract opening; forming a polysilicon layer over said top oxide layer and conformally along said sidewalls of said contact opening; depositing a photoresist layer into said contact opening; removing a portion of said polysilicon layer on top of said top oxide layer; forming a dielectric layer over said top oxide layer and conformally on top of said polysilicon layer along said sidewalls of said contact opening; forming a top conductive layer over said dielectric layer and in said contact opening.
摘要翻译：公开了一种用于制造鳍状沟槽电容器的方法。该方法包括以下步骤：形成包括顶部氧化物层的多个交替的氧化物和氮化物层，其中所述氮化物层夹在所述氧化物层之间; 在所述多个交替的氧化物和氮化物层中形成存储节点接触开口，在所述着陆焊盘处停止; 沿着所述合约开口的侧壁去除所述氮化物层的一部分; 在所述顶部氧化物层上形成多晶硅层，并沿着所述接触开口的所述侧壁共形地形成多晶硅层; 将光致抗蚀剂层沉积到所述接触开口中; 在所述顶部氧化物层的顶部上去除所述多晶硅层的一部分; 在所述顶部氧化物层上形成电介质层，并沿着所述接触开口的所述侧壁保形地位于所述多晶硅层的顶部上; 在所述介电层上和所述接触开口中形成顶部导电层。

6. 发明授权

US06074913A Method for forming a DRAM capacitor 失效
标题翻译：用于形成DRAM电容器的方法
公开(公告)号：US06074913A
公开(公告)日：2000-06-13
申请号：US108901
申请日：1998-07-01
申请人： Chine-Gie Lou , Yeur-Luen Tu
发明人： Chine-Gie Lou , Yeur-Luen Tu
IPC分类号： H01L21/02 , H01L21/285 , H01L21/8242
CPC分类号： H01L28/92 , H01L21/28568 , H01L27/10852 , H01L28/84
摘要： A method for manufacturing a metal-insulator-metal capacitor on a substrate is disclosed. The method comprises the steps of: forming a first dielectric layer onto said substrate; patterning and etching said first dielectric layer to form a contact opening; forming a first metal layer onto said first dielectric layer and into said contact opening; forming a barrier layer onto said first metal layer; forming a second dielectric layer onto said barrier layer; forming a discrete HSG layer onto said second dielectric layer; etching said second dielectric layer by using said HSG layer as a mask; stripping said HSG layer; etching said barrier layer and said first metal layer by using a remaining portion of said second dielectric layer as a mask; stripping said remaining portion of said second dielectric layer; patterning and etching a remaining portion of said barrier layer and a remaining portion of said first metal layer; forming a third dielectric layer over said barrier layer, said first metal layer and said first dielectric layer; and forming a second metal layer over said third dielectric layer.
摘要翻译：公开了一种在衬底上制造金属 - 绝缘体 - 金属电容器的方法。该方法包括以下步骤：在所述衬底上形成第一电介质层; 图案化和蚀刻所述第一介电层以形成接触开口; 在所述第一介电层上形成第一金属层并进入所述接触开口; 在所述第一金属层上形成势垒层; 在所述阻挡层上形成第二电介质层; 在所述第二介电层上形成离散的HSG层; 通过使用所述HSG层作为掩模蚀刻所述第二介质层; 剥离HSG层; 通过使用所述第二介电层的剩余部分作为掩模蚀刻所述阻挡层和所述第一金属层; 剥离所述第二电介质层的剩余部分; 图案化和蚀刻所述阻挡层的剩余部分和所述第一金属层的剩余部分; 在所述阻挡层上形成第三电介质层，所述第一金属层和所述第一介电层; 以及在所述第三介电层上形成第二金属层。

7. 发明授权

US5932487A Method for forming a planar intermetal dielectric layer 失效
标题翻译：形成平坦的金属间介电层的方法
公开(公告)号：US5932487A
公开(公告)日：1999-08-03
申请号：US41864
申请日：1998-03-12
申请人： Chine-Gie Lou , Yeur-Luen Tu
发明人： Chine-Gie Lou , Yeur-Luen Tu
IPC分类号： H01L21/3105 , H01L21/316 , H01L21/768 , H01L21/283
CPC分类号： H01L21/31604 , H01L21/31053 , H01L21/76819
摘要： A method of forming a planar intermetal dielectric over conductive metal structures is disclosed. The method comprises the steps of: (1) forming a liner oxide layer over the conductive metal structures; (2) forming a spin on glass layer over the liner oxide layer; (3) forming a cap oxide layer over the spin on glass layer; (4) forming a TiN layer over the cap oxide layer; (5) patterning and etching a contact hole through the TiN layer using the cap oxide layer as an etching stop; and (6) etching the cap oxide, the spin on glass, and the liner oxide down to the conductive metal structures using the TiN layer as a mask.
摘要翻译：公开了一种在导电金属结构上形成平坦的金属间电介质的方法。该方法包括以下步骤：（1）在导电金属结构之上形成衬垫氧化层; （2）在衬里氧化物层上形成在玻璃层上的自旋; （3）在玻璃层上的旋涂上形成帽氧化层; （4）在所述盖氧化物层上形成TiN层; （5）使用帽氧化物层作为蚀刻停止层，图案化蚀刻通过TiN层的接触孔; 和（6）使用TiN层作为掩模，将盖氧化物，玻璃上的旋涂和衬垫氧化物刻蚀成导电金属结构。

8. 发明申请

US20070145596A1 Interconnect structure and method of fabricating same 有权
标题翻译：互连结构及其制造方法
公开(公告)号：US20070145596A1
公开(公告)日：2007-06-28
申请号：US11317652
申请日：2005-12-22
申请人： Hsueh-Chung Chen , Chine-Gie Lou , Ping-Liang Liu , Su-Chen Fan
发明人： Hsueh-Chung Chen , Chine-Gie Lou , Ping-Liang Liu , Su-Chen Fan
IPC分类号： H01L23/48
CPC分类号： H01L23/485 , H01L2924/0002 , H01L2924/00
摘要： An improved interconnect structure and method of making such a device The improved interconnect electrically connects two otherwise separate areas on a semiconductor wafer. The interconnect preferably uses a copper conductor disposed within a trench and via structure formed in a low-k hybrid dielectric layer using a dual damascene process. Each contact region is served by a plurality of vias, each in communication with the trench conductor portion. The entry from the trench to the via is rounded for at least one and preferably all of the via structures.
摘要翻译：改进的互连结构和制造这种器件的方法改进的互连电路连接半导体晶片上的另外两个分开的区域。互连优选地使用布置在沟槽内的铜导体和使用双镶嵌工艺在低k混合电介质层中形成的通孔结构。每个接触区域由多个通孔提供，每个通孔与沟槽导体部分连通。从沟槽到通孔的入口对于至少一个并且优选地所有通孔结构是圆形的。

9. 发明申请

US20070020871A1 Three dimensional IC device and alignment methods of IC device substrates 有权
标题翻译： IC器件基板的三维IC器件和对准方法
公开(公告)号：US20070020871A1
公开(公告)日：2007-01-25
申请号：US11174511
申请日：2005-07-06
申请人： Hsueh-Chung Chen , Chine-Gie Lou , Su-Chen Fan
发明人： Hsueh-Chung Chen , Chine-Gie Lou , Su-Chen Fan
IPC分类号： H01L21/76
CPC分类号： H01L21/681
摘要： Alignment methods of IC device substrates. A first IC device substrate has a first front side for defining a plurality of first IC features, a first backside opposite the first front side, and a first alignment pattern formed on the first front side or the first backside. A second IC device substrate has a second front side for defining a plurality of second IC features, a second backside opposite the second front side, and a second alignment pattern formed on the second front side or the second backside. A first optical detector and a second optical detector are applied to detect the first and second alignment patterns, so as to align the first and second IC device substrates. Specifically, the first and second alignment patterns face toward the first and second optical detectors in opposite directions.
摘要翻译： IC器件基板的对准方法。第一IC器件衬底具有用于限定多个第一IC特征的第一前侧，与第一前侧相对的第一背面，以及形成在第一前侧或第一背面上的第一对准图案。第二IC器件衬底具有用于限定多个第二IC特征的第二前侧，与第二前侧相对的第二后侧和形成在第二前侧或第二后侧上的第二对准图案。应用第一光学检测器和第二光学检测器来检测第一和第二对准图案，以对准第一和第二IC器件基板。具体地，第一和第二对准图案朝向相反方向的第一和第二光学检测器。

10. 发明申请

US20050269666A1 Electrical fuses as programmable data storage 审中-公开
标题翻译：电气保险丝作为可编程数据存储
公开(公告)号：US20050269666A1
公开(公告)日：2005-12-08
申请号：US11056041
申请日：2005-02-11
申请人： Shine Chung , Chine-Gie Lou
发明人： Shine Chung , Chine-Gie Lou
IPC分类号： H01L21/82 , H01L23/525 , H01L23/62 , H01L27/10 , H01L29/00
CPC分类号： H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： An electrical fuse is disclosed. It is formed by a silicide layer on a polysilicon layer, with a first dielectric section separating the electrical fuse from a semiconductor substrate and a second dielectric section separating the electrical fuse from at least one electrical conductor directly above the fuse. The polysilicon layer is at least 2000 Angstroms in thickness and no more than 0.14 um in width and the second dielectric section contains substantially low-K materials.
摘要翻译：公开了一种电熔丝。其由多晶硅层上的硅化物层形成，其中第一介电部分将电熔丝与半导体衬底分开，以及第二介电部分将电熔丝与直接在熔丝上方的至少一个电导体分开。多晶硅层的厚度至少为2000埃，宽度不大于0.14微米，第二介质部分含有基本上低的K材料。

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