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1. 发明申请

US20070145596A1 Interconnect structure and method of fabricating same 有权
标题翻译：互连结构及其制造方法
公开(公告)号：US20070145596A1
公开(公告)日：2007-06-28
申请号：US11317652
申请日：2005-12-22
申请人： Hsueh-Chung Chen , Chine-Gie Lou , Ping-Liang Liu , Su-Chen Fan
发明人： Hsueh-Chung Chen , Chine-Gie Lou , Ping-Liang Liu , Su-Chen Fan
IPC分类号： H01L23/48
CPC分类号： H01L23/485 , H01L2924/0002 , H01L2924/00
摘要： An improved interconnect structure and method of making such a device The improved interconnect electrically connects two otherwise separate areas on a semiconductor wafer. The interconnect preferably uses a copper conductor disposed within a trench and via structure formed in a low-k hybrid dielectric layer using a dual damascene process. Each contact region is served by a plurality of vias, each in communication with the trench conductor portion. The entry from the trench to the via is rounded for at least one and preferably all of the via structures.
摘要翻译：改进的互连结构和制造这种器件的方法改进的互连电路连接半导体晶片上的另外两个分开的区域。互连优选地使用布置在沟槽内的铜导体和使用双镶嵌工艺在低k混合电介质层中形成的通孔结构。每个接触区域由多个通孔提供，每个通孔与沟槽导体部分连通。从沟槽到通孔的入口对于至少一个并且优选地所有通孔结构是圆形的。

2. 发明授权

US07781892B2 Interconnect structure and method of fabricating same 有权
标题翻译：互连结构及其制造方法
公开(公告)号：US07781892B2
公开(公告)日：2010-08-24
申请号：US11317652
申请日：2005-12-22
申请人： Hsueh-Chung Chen , Chine-Gie Lou , Ping-Liang Liu , Su-Chen Fan
发明人： Hsueh-Chung Chen , Chine-Gie Lou , Ping-Liang Liu , Su-Chen Fan
IPC分类号： H01L29/41
CPC分类号： H01L23/485 , H01L2924/0002 , H01L2924/00
摘要： An improved interconnect structure and method of making such a device. The improved interconnect electrically connects two otherwise separate areas on a semiconductor wafer. The interconnect preferably uses a copper conductor disposed within a trench and via structure formed in a low-k hybrid dielectric layer using a dual damascene process. Each contact region is served by a plurality of vias, each in communication with the trench conductor portion. The entry from the trench to the via is rounded for at least one and preferably all of the via structures.
摘要翻译：改进的互连结构和制造这种装置的方法。改进的互连电路连接半导体晶片上的另外两个分开的区域。互连优选地使用布置在沟槽内的铜导体和使用双镶嵌工艺在低k混合电介质层中形成的通孔结构。每个接触区域由多个通孔提供，每个通孔与沟槽导体部分连通。从沟槽到通孔的入口对于至少一个并且优选地所有通孔结构是圆形的。

3. 发明申请

US20070020871A1 Three dimensional IC device and alignment methods of IC device substrates 有权
标题翻译： IC器件基板的三维IC器件和对准方法
公开(公告)号：US20070020871A1
公开(公告)日：2007-01-25
申请号：US11174511
申请日：2005-07-06
申请人： Hsueh-Chung Chen , Chine-Gie Lou , Su-Chen Fan
发明人： Hsueh-Chung Chen , Chine-Gie Lou , Su-Chen Fan
IPC分类号： H01L21/76
CPC分类号： H01L21/681
摘要： Alignment methods of IC device substrates. A first IC device substrate has a first front side for defining a plurality of first IC features, a first backside opposite the first front side, and a first alignment pattern formed on the first front side or the first backside. A second IC device substrate has a second front side for defining a plurality of second IC features, a second backside opposite the second front side, and a second alignment pattern formed on the second front side or the second backside. A first optical detector and a second optical detector are applied to detect the first and second alignment patterns, so as to align the first and second IC device substrates. Specifically, the first and second alignment patterns face toward the first and second optical detectors in opposite directions.
摘要翻译： IC器件基板的对准方法。第一IC器件衬底具有用于限定多个第一IC特征的第一前侧，与第一前侧相对的第一背面，以及形成在第一前侧或第一背面上的第一对准图案。第二IC器件衬底具有用于限定多个第二IC特征的第二前侧，与第二前侧相对的第二后侧和形成在第二前侧或第二后侧上的第二对准图案。应用第一光学检测器和第二光学检测器来检测第一和第二对准图案，以对准第一和第二IC器件基板。具体地，第一和第二对准图案朝向相反方向的第一和第二光学检测器。

4. 发明授权

US08232659B2 Three dimensional IC device and alignment methods of IC device substrates 有权
标题翻译： IC器件基板的三维IC器件和对准方法
公开(公告)号：US08232659B2
公开(公告)日：2012-07-31
申请号：US12048015
申请日：2008-03-13
申请人： Hsueh-Chung Chen , Chine-Gie Lou , Su-Chen Fan
发明人： Hsueh-Chung Chen , Chine-Gie Lou , Su-Chen Fan
IPC分类号： H01L23/544 , H01L23/34
CPC分类号： H01L21/681
摘要： Alignment methods of IC device substrates. A first IC device substrate has a first front side for defining a plurality of first IC features, a first backside opposite the first front side, and a first alignment pattern formed on the first front side or the first backside. A second IC device substrate has a second front side for defining a plurality of second IC features, a second backside opposite the second front side, and a second alignment pattern formed on the second front side or the second backside. A first optical detector and a second optical detector are applied to detect the first and second alignment patterns, so as to align the first and second IC device substrates. Specifically, the first and second alignment patterns face toward the first and second optical detectors in opposite directions.
摘要翻译： IC器件基板的对准方法。第一IC器件衬底具有用于限定多个第一IC特征的第一前侧，与第一前侧相对的第一背面，以及形成在第一前侧或第一背面上的第一对准图案。第二IC器件衬底具有用于限定多个第二IC特征的第二前侧，与第二前侧相对的第二后侧和形成在第二前侧或第二后侧上的第二对准图案。应用第一光学检测器和第二光学检测器来检测第一和第二对准图案，以对准第一和第二IC器件基板。具体地，第一和第二对准图案朝向相反方向的第一和第二光学检测器。

5. 发明授权

US07371663B2 Three dimensional IC device and alignment methods of IC device substrates 有权
标题翻译： IC器件基板的三维IC器件和对准方法
公开(公告)号：US07371663B2
公开(公告)日：2008-05-13
申请号：US11174511
申请日：2005-07-06
申请人： Hsueh-Chung Chen , Chine-Gie Lou , Su-Chen Fan
发明人： Hsueh-Chung Chen , Chine-Gie Lou , Su-Chen Fan
IPC分类号： H01L21/00
CPC分类号： H01L21/681
摘要： Alignment methods of IC device substrates. A first IC device substrate has a first front side for defining a plurality of first IC features, a first backside opposite the first front side, and a first alignment pattern formed on the first front side or the first backside. A second IC device substrate has a second front side for defining a plurality of second IC features, a second backside opposite the second front side, and a second alignment pattern formed on the second front side or the second backside. A first optical detector and a second optical detector are applied to detect the first and second alignment patterns, so as to align the first and second IC device substrates. Specifically, the first and second alignment patterns face toward the first and second optical detectors in opposite directions.
摘要翻译： IC器件基板的对准方法。第一IC器件衬底具有用于限定多个第一IC特征的第一前侧，与第一前侧相对的第一背面，以及形成在第一前侧或第一背面上的第一对准图案。第二IC器件衬底具有用于限定多个第二IC特征的第二前侧，与第二前侧相对的第二后侧和形成在第二前侧或第二后侧上的第二对准图案。应用第一光学检测器和第二光学检测器来检测第一和第二对准图案，以对准第一和第二IC器件基板。具体地，第一和第二对准图案朝向相反方向的第一和第二光学检测器。

6. 发明授权

US6048794A Selective W CVD plug process with a RTA self-aligned W-silicide barrier layer 失效
标题翻译：具有RTA自对准W硅化物阻挡层的选择性W CVD插塞工艺
公开(公告)号：US6048794A
公开(公告)日：2000-04-11
申请号：US954048
申请日：1997-10-20
申请人： Hsueh-Chung Chen , Chine-Gie Lou
发明人： Hsueh-Chung Chen , Chine-Gie Lou
IPC分类号： H01L21/285 , H01L21/768 , H01L21/44
CPC分类号： H01L21/28518 , H01L21/76879
摘要： The present invention provides a method of fabricating a tungsten (W) plug 36 contact to a substrate using a selective W CVD Process with a self-aligned W-Silicide Barrier layer 34. The method comprises the steps of: forming first insulating layer 20 over a silicon semiconductor substrate 10; forming a first (contact) opening 24 in the first insulating layer 20 exposing the surface of the substrate; selectively growing a thin first tungsten layer 30 over the exposed substrate surface; rapidly thermally annealing the substrate forming a thin first tungsten silicide layer 34 from the thin first tungsten layer 30; selectively depositing a tungsten plug 36 over the first thin tungsten silicide layer 34 substantially filling the first opening 36 thereby forming a W plug contact. The RTA/W silicide layer 34 lowers the contact resistance, increases the adhesion and facilitates the selective deposition of the W plug 36.
摘要翻译：本发明提供一种使用具有自对准的W-硅化物阻挡层34的选择性W CVD工艺制造与衬底接触的钨（W）插头36的方法。该方法包括以下步骤：将第一绝缘层20形成在硅半导体衬底10; 在第一绝缘层20中形成暴露基板表面的第一（接触）开口24; 在暴露的衬底表面上选择性地生长薄的第一钨层30; 从薄的第一钨层30快速热退火形成薄的第一硅化钨层34; 在基本上填充第一开口36的第一薄钨硅酸盐层34上选择性地沉积钨塞36，从而形成W插头接触。 RTA / W硅化物层34降低了接触电阻，增加了粘附性，并且有助于W插塞36的选择性沉积。

7. 发明授权

US5872045A Method for making an improved global planarization surface by using a gradient-doped polysilicon trench--fill in shallow trench isolation 失效
标题翻译：通过在浅沟槽隔离中使用梯度掺杂多晶硅沟槽填充来制造改进的全局平坦化表面的方法
公开(公告)号：US5872045A
公开(公告)日：1999-02-16
申请号：US892215
申请日：1997-07-14
申请人： Chine-Gie Lou , Hsueh-Chung Chen
发明人： Chine-Gie Lou , Hsueh-Chung Chen
IPC分类号： H01L21/762 , H01L21/763 , H01L21/76
CPC分类号： H01L21/763 , H01L21/76202
摘要： A method for fabricating shallow trench isolation using a gradient-doped polysilicon trench-fill and a chemical/mechanical polishing that improves substrate planarity was achieved. The method involves forming shallow trenches in a silicon substrate having a silicon nitride layer on the surface. After selectively oxidizing silicon exposed in the trenches, a second silicon nitride layer is deposited, and a composite polysilicon layer consisting of an undoped polysilicon layer and a gradient-doped polysilicon layer is deposited filling the trenches. The composite polysilicon layer is then chemical/mechanically polished back. The gradient-doped polysilicon layer improves the removal rate uniformity across the substrate (wafer) by removing the heavily doped regions at a faster rate than undoped or lightly doped regions. This results in improved global planarity which improves the polysilicon dishing in the trenches near the edge of the substrate. A step-wise doping gradient was found to achieve the best removal rate uniformity across the substrate. The undoped polysilicon remaining in the trenches is then thermally oxidized to eliminate dishing in wide trenches, and the silicon nitride layers are removed by selectively etching to complete the shallow trench isolation.
摘要翻译：实现了使用梯度掺杂多晶硅沟槽填充制造浅沟槽隔离和改善衬底平面度的化学/机械抛光的方法。该方法包括在表面上具有氮化硅层的硅衬底中形成浅沟槽。在选择性地氧化在沟槽中暴露的硅之后，沉积第二氮化硅层，并沉积由未掺杂多晶硅层和梯度掺杂多晶硅层组成的复合多晶硅层填充沟槽。然后将复合多晶硅层化学/机械抛光。通过以比未掺杂的或轻掺杂的区域更快的速率去除重掺杂区域，斜面掺杂多晶硅层提高了衬底（晶片）上的去除率均匀性。这导致改进的全局平面度，其改善了衬底边缘附近的沟槽中的多晶硅凹陷。发现逐步的掺杂梯度可以实现基板上最佳的去除率均匀性。然后将残留在沟槽中的未掺杂多晶硅热氧化以消除宽沟槽中的凹陷，并且通过选择性蚀刻去除氮化硅层以完成浅沟槽隔离。

8. 发明授权

US06239017B1 Dual damascene CMP process with BPSG reflowed contact hole 有权
标题翻译：双镶嵌CMP工艺与BPSG回流接触孔
公开(公告)号：US06239017B1
公开(公告)日：2001-05-29
申请号：US09156357
申请日：1998-09-18
申请人： Chine-Gie Lou , Hsueh-Chung Chen
发明人： Chine-Gie Lou , Hsueh-Chung Chen
IPC分类号： H01L214763
CPC分类号： H01L21/76828 , H01L21/31612 , H01L21/31625 , H01L21/76804 , H01L21/76807 , H01L2221/1036
摘要： An improved and new process for fabricating a planarized dual damascene contact hole and trench structure, wherein the contact holes have tapered sidewalls, has been developed. The dual damascene contact hole and trench are formed in a three layer insulator structure, in which the middle layer is a doped silicon oxide having a lower reflow temperature than the undoped silicon oxide layers forming the top and bottom layers. The contact holes are etched through the doped silicon oxide layer and the bottom undoped silicon oxide layer. The trenches are etched through the top undoped silicon oxide layer. After etching tapered sidewalls are formed at the contact holes by reflow of the doped silicon oxide through which the holes are etched.
摘要翻译：已经开发了一种用于制造平面化双镶嵌接触孔和沟槽结构的改进和新工艺，其中接触孔具有锥形侧壁。双镶嵌接触孔和沟槽形成为三层绝缘体结构，其中中间层是具有比形成顶层和底层的未掺杂氧化硅层低的回流温度的掺杂氧化硅。通过掺杂氧化硅层和底部未掺杂的氧化硅层蚀刻接触孔。通过顶部未掺杂的氧化硅层蚀刻沟槽。蚀刻之后，通过掺杂氧化硅的回流在接触孔处形成锥形侧壁，通过该掺杂氧化硅蚀刻孔。

9. 发明授权

US06184130B2 Silicide glue layer for W-CVD plug application 失效
公开(公告)号：US06184130B2
公开(公告)日：2001-02-06
申请号：US08965313
申请日：1997-11-06
申请人： Tzu-Kun Ku , Hsueh-Chung Chen , Chine-Gie Lou
发明人： Tzu-Kun Ku , Hsueh-Chung Chen , Chine-Gie Lou
IPC分类号： H01L2144
CPC分类号： H01L21/76876 , H01L21/76843 , H01L23/5226 , H01L2924/0002 , H01L2924/00
摘要： A new method of tungsten plug metallization using a silicide glue layer is described. Semiconductor device structures are provided in and on a semiconductor substrate. An insulating layer is provided covering the semiconductor device structures wherein a contact opening is made through the insulating layer to one of the semiconductor device structures. A silicide layer is deposited conformally over the surface of the insulating layer and within the contact opening as a combined ohmic contact and glue layer. In a first embodiment, a tungsten layer is deposited overlying the silicide layer. The tungsten layer not within the contact opening is removed to complete the formation of the tungsten plug metallization. In a second embodiment, the silicide layer not within the contact opening is selectively removed and a tungsten layer is selectively deposited overlying the silicide layer within the contact opening to complete formation of the tungsten plug metallization in the fabrication of an integrated circuit.

10. 发明授权

US06110826A Dual damascene process using selective W CVD 失效
标题翻译：使用选择性W CVD的双镶嵌工艺
公开(公告)号：US06110826A
公开(公告)日：2000-08-29
申请号：US092816
申请日：1998-06-08
申请人： Chine-Gie Lou , Hsueh-Chung Chen
发明人： Chine-Gie Lou , Hsueh-Chung Chen
IPC分类号： H01L21/44 , H01L21/768
CPC分类号： H01L21/76876 , H01L21/76844 , H01L21/76879
摘要： A dual damascene process using selective tungsten chemical vapor deposition is provided for forming composite structures for local interconnects comprising line trenches with contact holes, and composite structures for intermetal interconnects comprising line trenches with via holes. It is shown that by forming a seed layer in judiciously selected portions of the dual damascene structure and depositing tungsten selectively in one step, contact holes and via holes can be formed free of voids and key-holes.
摘要翻译：提供了使用选择性钨化学气相沉积的双镶嵌工艺，用于形成包括具有接触孔的线沟槽的局部互连的复合结构，以及用于金属间互连的复合结构，其包括具有通孔的线沟槽。示出了通过在双镶嵌结构的明智选择的部分中形成种子层并且在一个步骤中选择性地沉积钨，可以形成没有空隙和键孔的接触孔和通孔。

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