专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20060091566A1 Bond pad structure for integrated circuit chip 审中-公开
标题翻译：用于集成电路芯片的焊盘结构
公开(公告)号：US20060091566A1
公开(公告)日：2006-05-04
申请号：US10989481
申请日：2004-11-16
申请人： Chin-Tien Yang , Shou Chang , Min Cao , Yuh-Jier Mii
发明人： Chin-Tien Yang , Shou Chang , Min Cao , Yuh-Jier Mii
IPC分类号： H01L23/48
CPC分类号： H01L24/05 , H01L24/45 , H01L2224/04042 , H01L2224/05093 , H01L2224/05552 , H01L2224/05624 , H01L2224/05639 , H01L2224/05644 , H01L2224/05647 , H01L2224/05655 , H01L2224/05666 , H01L2224/05681 , H01L2224/05684 , H01L2224/45124 , H01L2224/45144 , H01L2224/48624 , H01L2224/48639 , H01L2224/48644 , H01L2224/48647 , H01L2224/48655 , H01L2224/48666 , H01L2224/48681 , H01L2224/48684 , H01L2224/48724 , H01L2224/48739 , H01L2224/48744 , H01L2224/48747 , H01L2224/48755 , H01L2224/48766 , H01L2224/48781 , H01L2224/48784 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01019 , H01L2924/01022 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01073 , H01L2924/01074 , H01L2924/01079 , H01L2924/01327 , H01L2924/014 , H01L2924/14 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/30105 , H01L2924/00014 , H01L2924/00012 , H01L2924/00
摘要： An integrated circuit chip is provided, which includes a bond pad structure, a low-k dielectric layer, and active circuits. The bond pad structure includes a conductive bond pad, an Mtop solid conductive plate, and an Mtop−1 solid conductive plate. The Mtop solid conductive plate is located under the bond pad. The Mtop plate is electrically coupled to the bond pad. The Mtop−1 solid conductive plate is located under the Mtop plate. A low-k dielectric layer is located under the bond pad of the bond pad structure. At least part of an active circuit is located under the bond pad of the bond pad structure.
摘要翻译：提供了一种集成电路芯片，其包括接合焊盘结构，低k电介质层和有源电路。接合焊盘结构包括导电接合焊盘，M＆lt;顶部＆lt;固体导电板和M＆lt;顶1实心导电板。 M＆lt;＆gt;顶部<！ - SIPO - >固体导电板位于接合焊盘下方。 M＆lt;顶部板电连接到接合焊盘。 M＆lt; 1＆gt;顶部实体导电板位于M＆lt;顶部板下方。低k电介质层位于接合焊盘结构的接合焊盘下方。有源电路的至少一部分位于接合焊盘结构的接合焊盘的下方。

2. 发明申请

US20050116281A1 Multilayered dual bit memory device with improved write/erase characteristics and method of manufacturing 失效
公开(公告)号：US20050116281A1
公开(公告)日：2005-06-02
申请号：US10725234
申请日：2003-12-01
申请人： Chin-Tien Yang , Mu-Yi Lin , Yu-Wei Tseng , Min Cao , Yu-Hua Lee
发明人： Chin-Tien Yang , Mu-Yi Lin , Yu-Wei Tseng , Min Cao , Yu-Hua Lee
IPC分类号： G11C16/04 , H01L21/28 , H01L21/8246 , H01L21/8247 , H01L27/115 , H01L29/792 , H01L21/8238
CPC分类号： H01L27/11568 , G11C16/0458 , H01L21/28273 , H01L21/28282 , H01L27/115 , H01L27/11521 , H01L29/7923
摘要： A dual bit ROM multilayered structure with improved write and erase functions and a method of manufacturing is disclosed. The structure includes a pair of floating gates at the middle or nitride layer to better define the two locations of electrons representing the dual data bits collected in the middle layer.

3. 发明授权

US06844626B2 Bond pad scheme for Cu process 有权
公开(公告)号：US06844626B2
公开(公告)日：2005-01-18
申请号：US10444229
申请日：2003-05-23
申请人： Chia-Hung Lai , Jiunn-Jyi Lin , Tzong-Sheng Chang , Min Cao , Huan-Chi Tseng , Yu-Hua Lee , Chin-Tien Yang
发明人： Chia-Hung Lai , Jiunn-Jyi Lin , Tzong-Sheng Chang , Min Cao , Huan-Chi Tseng , Yu-Hua Lee , Chin-Tien Yang
IPC分类号： H01L21/28 , H01L21/44 , H01L21/60 , H01L21/768 , H01L23/48 , H01L23/485 , H01L23/52 , H01L29/40
CPC分类号： H01L24/13 , H01L24/03 , H01L24/05 , H01L24/11 , H01L2224/0401 , H01L2224/05006 , H01L2224/05624 , H01L2224/05647 , H01L2224/13007 , H01L2224/13099 , H01L2924/0001 , H01L2924/01013 , H01L2924/01014 , H01L2924/01019 , H01L2924/01029 , H01L2924/01032 , H01L2924/01033 , H01L2924/01039 , H01L2924/01073 , H01L2924/01082 , H01L2924/01083 , H01L2924/04953 , H01L2924/10329 , H01L2924/14 , H01L2924/19041 , H01L2924/19043
摘要： A novel method of forming a bond pad of a semiconductor device and a novel bond pad structure. Two passivation layers are used to form bond pads of a semiconductor device. A portion of the second passivation layer resides between adjacent bond pads, preventing shorting of the bond pads during subsequent wire bonding processes or flip-chip packaging processes.

4. 发明授权

US07015129B2 Bond pad scheme for Cu process 失效
标题翻译： Cu工艺的焊盘方案
公开(公告)号：US07015129B2
公开(公告)日：2006-03-21
申请号：US10999464
申请日：2004-11-29
申请人： Chia-Hung Lai , Jiunn-Jyi Lin , Tzong-Sheng Chang , Min Cao , Huan-Chi Tseng , Yu-Hua Lee , Chin-Tien Yang
发明人： Chia-Hung Lai , Jiunn-Jyi Lin , Tzong-Sheng Chang , Min Cao , Huan-Chi Tseng , Yu-Hua Lee , Chin-Tien Yang
IPC分类号： H01L21/44
CPC分类号： H01L24/13 , H01L24/03 , H01L24/05 , H01L24/11 , H01L2224/0401 , H01L2224/05006 , H01L2224/05624 , H01L2224/05647 , H01L2224/13007 , H01L2224/13099 , H01L2924/0001 , H01L2924/01013 , H01L2924/01014 , H01L2924/01019 , H01L2924/01029 , H01L2924/01032 , H01L2924/01033 , H01L2924/01039 , H01L2924/01073 , H01L2924/01082 , H01L2924/01083 , H01L2924/04953 , H01L2924/10329 , H01L2924/14 , H01L2924/19041 , H01L2924/19043
摘要： A novel method of forming a bond pad of a semiconductor device and a novel bond pad structure. Two passivation layers are used to form bond pads of a semiconductor device. A portion of the second passivation layer resides between adjacent bond pads, preventing shorting of the bond pads during subsequent wire bonding processes or flip-chip packaging processes.
摘要翻译：一种形成半导体器件的接合焊盘和新的接合焊盘结构的新颖方法。两个钝化层用于形成半导体器件的接合焊盘。第二钝化层的一部分位于相邻的接合焊盘之间，防止在随后的引线接合过程或倒装芯片封装工艺期间接合焊盘短路。

5. 发明申请

US20050173799A1 Interconnect structure and method for its fabricating 审中-公开
标题翻译：互连结构及其制造方法
公开(公告)号：US20050173799A1
公开(公告)日：2005-08-11
申请号：US10772736
申请日：2004-02-05
申请人： Juan-Jann Jou , Yu-Hua Lee , Chin-Tien Yang , Chia-Hung Lai , Connie Hsu , Mu-Yi Lin , Min Cao , Chia-Yu Ku , Yuh-Da Fan
发明人： Juan-Jann Jou , Yu-Hua Lee , Chin-Tien Yang , Chia-Hung Lai , Connie Hsu , Mu-Yi Lin , Min Cao , Chia-Yu Ku , Yuh-Da Fan
IPC分类号： H01L21/31 , H01L21/311 , H01L21/3205 , H01L21/3213 , H01L21/4763 , H01L21/768 , H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L21/76844 , H01L21/31116 , H01L21/32136 , H01L21/76805 , H01L21/76838 , H01L21/76847
摘要： A method of fabricating an interconnect structure, including providing a semiconductor substrate having a first conductive layer thereon, and forming a dielectric layer overlying the semiconductor substrate and the first conductive layer. An opening is formed in the dielectric layer extending to the first conductive layer. A portion of the first conductive layer is removed through the opening to form a recess having a substantially curvilinear profile. The opening and the recess are filled with a second conductive layer.
摘要翻译：一种制造互连结构的方法，包括提供其上具有第一导电层的半导体衬底，以及形成覆盖在半导体衬底和第一导电层上的电介质层。在延伸到第一导电层的电介质层中形成开口。通过开口去除第一导电层的一部分以形成具有基本曲线轮廓的凹部。开口和凹部填充有第二导电层。

6. 发明申请

US20050095836A1 Bond pad scheme for Cu process 失效
标题翻译： Cu工艺的焊盘方案
公开(公告)号：US20050095836A1
公开(公告)日：2005-05-05
申请号：US10999464
申请日：2004-11-29
申请人： Chia-Hung Lai , Jiunn-Jyi Lin , Tzong-Sheng Chang , Min Cao , Huan-Chi Tseng , Yu-Hua Lee , Chin-Tien Yang
发明人： Chia-Hung Lai , Jiunn-Jyi Lin , Tzong-Sheng Chang , Min Cao , Huan-Chi Tseng , Yu-Hua Lee , Chin-Tien Yang
IPC分类号： H01L21/28 , H01L21/44 , H01L21/60 , H01L21/768 , H01L23/48 , H01L23/485 , H01L23/52 , H01L29/40
CPC分类号： H01L24/13 , H01L24/03 , H01L24/05 , H01L24/11 , H01L2224/0401 , H01L2224/05006 , H01L2224/05624 , H01L2224/05647 , H01L2224/13007 , H01L2224/13099 , H01L2924/0001 , H01L2924/01013 , H01L2924/01014 , H01L2924/01019 , H01L2924/01029 , H01L2924/01032 , H01L2924/01033 , H01L2924/01039 , H01L2924/01073 , H01L2924/01082 , H01L2924/01083 , H01L2924/04953 , H01L2924/10329 , H01L2924/14 , H01L2924/19041 , H01L2924/19043
摘要： A novel method of forming a bond pad of a semiconductor device and a novel bond pad structure. Two passivation layers are used to form bond pads of a semiconductor device. A portion of the second passivation layer resides between adjacent bond pads, preventing shorting of the bond pads during subsequent wire bonding processes or flip-chip packaging processes.
摘要翻译：一种形成半导体器件的接合焊盘和新的接合焊盘结构的新颖方法。两个钝化层用于形成半导体器件的接合焊盘。第二钝化层的一部分位于相邻的接合焊盘之间，防止在随后的引线接合过程或倒装芯片封装工艺期间接合焊盘短路。

7. 发明授权

US09312260B2 Integrated circuits and manufacturing methods thereof 有权
标题翻译：集成电路及其制造方法
公开(公告)号：US09312260B2
公开(公告)日：2016-04-12
申请号：US13086186
申请日：2011-04-13
申请人： Ali Keshavarzi , Ta-Pen Guo , Helen Shu-Hui Chang , Hsiang-Jen Tseng , Shyue-Shyh Lin , Lee-Chung Lu , Chung-Cheng Wu , Li-Chun Tien , Jung-Chan Yang , Shu-Min Chen , Min Cao , Yung-Chin Hou
发明人： Ali Keshavarzi , Ta-Pen Guo , Helen Shu-Hui Chang , Hsiang-Jen Tseng , Shyue-Shyh Lin , Lee-Chung Lu , Chung-Cheng Wu , Li-Chun Tien , Jung-Chan Yang , Shu-Min Chen , Min Cao , Yung-Chin Hou
IPC分类号： H01L29/76 , H01L27/092 , H01L21/8238 , H01L23/485 , H01L27/02 , H01L29/423 , H01L29/66 , H01L29/78
CPC分类号： H01L27/092 , H01L21/823871 , H01L23/485 , H01L27/0207 , H01L29/0649 , H01L29/4238 , H01L29/495 , H01L29/66545 , H01L29/7833 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit includes a first diffusion area for a first type transistor. The first type transistor includes a first drain region and a first source region. A second diffusion area for a second type transistor is separated from the first diffusion area. The second type transistor includes a second drain region and a second source region. A gate electrode continuously extends across the first diffusion area and the second diffusion area in a routing direction. A first metallic structure is electrically coupled with the first source region. A second metallic structure is electrically coupled with the second drain region. A third metallic structure is disposed over and electrically coupled with the first and second metallic structures. A width of the first metallic structure is substantially equal to or larger than a width of the third metallic structure.
摘要翻译：集成电路包括用于第一类型晶体管的第一扩散区域。第一类型晶体管包括第一漏极区域和第一源极区域。用于第二类型晶体管的第二扩散区域与第一扩散区域分离。第二类型晶体管包括第二漏极区域和第二源极区域。栅电极在布线方向上连续延伸穿过第一扩散区域和第二扩散区域。第一金属结构与第一源区电耦合。第二金属结构与第二漏区电耦合。第三金属结构设置在第一和第二金属结构之上并与第一和第二金属结构电耦合。第一金属结构体的宽度基本上等于或大于第三金属结构体的宽度。

8. 发明申请

US20130094035A1 MULTIPLE PATTERNING TECHNOLOGY METHOD AND SYSTEM FOR ACHIEVING MINIMAL PATTERN MISMATCH 有权
标题翻译：用于实现最小图案误差的多种格局技术方法和系统
公开(公告)号：US20130094035A1
公开(公告)日：2013-04-18
申请号：US13275899
申请日：2011-10-18
申请人： Feng-Ming Chang , Chang-Ta Yang , Ping-Wei Wang , Min Cao
发明人： Feng-Ming Chang , Chang-Ta Yang , Ping-Wei Wang , Min Cao
IPC分类号： H04N1/60
CPC分类号： G03F1/68 , G03F1/70 , G03F7/0005 , H01L27/0207 , H01L27/1104
摘要： The present disclosure provides for many different embodiments of a multiple patterning technology method and system. An exemplary method includes receiving a pattern layout having a plurality of features; coloring each of the plurality of features one of at least two colors, thereby forming a colored pattern layout, wherein the coloring includes coloring match-sensitive features a same color; and fabricating at least two masks with the features of the colored pattern layout, wherein each mask includes features of a single color.
摘要翻译：本公开提供了多种图案化技术方法和系统的许多不同实施例。一种示例性方法包括接收具有多个特征的图案布局; 将多个特征中的每一个着色为至少两种颜色中的一种，从而形成着色图案布局，其中着色包括对相同颜色的匹配敏感特征进行着色; 以及制造具有着色图案布局的特征的至少两个掩模，其中每个掩模包括单一颜色的特征。

9. 发明授权

US07657856B1 Method and system for parallel processing of IC design layouts 失效
标题翻译： IC设计布局并行处理方法与系统
公开(公告)号：US07657856B1
公开(公告)日：2010-02-02
申请号：US11520487
申请日：2006-09-12
申请人： Mathew Koshy , Roland Ruehl , Min Cao , Li-Ling Ma , Eitan Cadouri , Tianhao Zhang
发明人： Mathew Koshy , Roland Ruehl , Min Cao , Li-Ling Ma , Eitan Cadouri , Tianhao Zhang
IPC分类号： G06F17/50
CPC分类号： G06F17/5081
摘要： Disclosed is a method and system for processing the tasks performed by an IC layout processing tool in parallel. In some approaches, the IC layout is divided into a plurality of layout portions and one or more of the layout portions are processed in parallel, where geometric select operations are performed in which data for different layout portions may be shared between different processing entities. One approach includes the following actions: select phase one operation for performing initial select actions within layout portions; distributed regioning action for local regioning; distributed regioning action for global regioning and binary select; count select aggregation for count-based select operations; and select phase two operations for combining results of selecting of internal shapes and interface shapes.
摘要翻译：公开了一种用于并行处理由IC布局处理工具执行的任务的方法和系统。在一些方法中，IC布局被划分为多个布局部分，并且一个或多个布局部分被并行处理，其中执行几何选择操作，其中用于不同布局部分的数据可以在不同处理实体之间共享。一种方法包括以下操作：选择在布局部分内执行初始选择动作的第一阶段操作; 分布式区域划分行动; 全局分区和二进制选择的分布式分区动作; 对于基于计数的选择操作的计数选择聚合; 并选择第二阶段操作来组合内部形状和界面形状的选择结果。

10. 发明授权

US06674116B1 Variable capacitor using MOS gated diode with multiple segments to limit DC current 有权
公开(公告)号：US06674116B1
公开(公告)日：2004-01-06
申请号：US09683709
申请日：2002-02-05
申请人： Min Cao
发明人： Min Cao
IPC分类号： H01L27108
CPC分类号： H01L29/94
摘要： A voltage-variable capacitor uses the channel-to-substrate junction from a gated diode formed from a metal-oxide-semiconductor transistor. The transistor gate has at least two contacts that are biased to different voltages. The gate acts as a resistor with current flowing from an upper gate contact to a lower gate contact. The gate-to-source voltage varies as a function of the position. A critical voltage is where the gate-to-source voltage is equal to the transistor threshold. A portion of the gate that has gate voltages above the critical voltage has an inversion layer or conducting channel under the gate. Another portion of the gate has gate voltages below the critical voltage, and thus no channel forms. By varying either the gate voltages or the source voltage, the area of the gate that has a channel under it is varied, varying the channel-to-substrate capacitance. Separate gate arms reduce bias current.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式