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1. 发明申请

US20050173799A1 Interconnect structure and method for its fabricating 审中-公开
标题翻译：互连结构及其制造方法
公开(公告)号：US20050173799A1
公开(公告)日：2005-08-11
申请号：US10772736
申请日：2004-02-05
申请人： Juan-Jann Jou , Yu-Hua Lee , Chin-Tien Yang , Chia-Hung Lai , Connie Hsu , Mu-Yi Lin , Min Cao , Chia-Yu Ku , Yuh-Da Fan
发明人： Juan-Jann Jou , Yu-Hua Lee , Chin-Tien Yang , Chia-Hung Lai , Connie Hsu , Mu-Yi Lin , Min Cao , Chia-Yu Ku , Yuh-Da Fan
IPC分类号： H01L21/31 , H01L21/311 , H01L21/3205 , H01L21/3213 , H01L21/4763 , H01L21/768 , H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L21/76844 , H01L21/31116 , H01L21/32136 , H01L21/76805 , H01L21/76838 , H01L21/76847
摘要： A method of fabricating an interconnect structure, including providing a semiconductor substrate having a first conductive layer thereon, and forming a dielectric layer overlying the semiconductor substrate and the first conductive layer. An opening is formed in the dielectric layer extending to the first conductive layer. A portion of the first conductive layer is removed through the opening to form a recess having a substantially curvilinear profile. The opening and the recess are filled with a second conductive layer.
摘要翻译：一种制造互连结构的方法，包括提供其上具有第一导电层的半导体衬底，以及形成覆盖在半导体衬底和第一导电层上的电介质层。在延伸到第一导电层的电介质层中形成开口。通过开口去除第一导电层的一部分以形成具有基本曲线轮廓的凹部。开口和凹部填充有第二导电层。

2. 发明授权

US6124212A High density plasma (HDP) etch method for suppressing micro-loading effects when etching polysilicon layers 失效
标题翻译：用于在蚀刻多晶硅层时抑制微载荷效应的高密度等离子体（HDP）蚀刻方法
公开(公告)号：US6124212A
公开(公告)日：2000-09-26
申请号：US947828
申请日：1997-10-08
申请人： Yuh-Da Fan , Weng-Liang Fang
发明人： Yuh-Da Fan , Weng-Liang Fang
IPC分类号： H01L21/311 , H01L21/3213 , H01L21/302
CPC分类号： H01L21/32137 , H01L21/31138 , H01L21/32139
摘要： A method for forming a patterned polysilicon layer within a microelectronics fabrication. There is first provided a substrate layer employed within a microelectronics fabrication. There is then formed upon the substrate layer a blanket polysilicon layer. There is then formed upon the blanket polysilicon layer a blanket organic polymer layer. There is then formed upon the blanket organic polymer layer a patterned photoresist layer, where the patterned photoresist layer has a high areal density region and a low areal density region. There is then etched through a first plasma etch method while employing the patterned photoresist layer as an etch mask layer the blanket organic polymer layer to form a patterned organic polymer layer while reaching the blanket polysilicon layer. The patterned organic polymer layer has a high areal density region corresponding with the high areal density region of the patterned photoresist layer and a low areal density region corresponding with the low areal density region of the patterned photoresist layer. The blanket polysilicon layer also has formed thereupon an organic polymer residue layer within portions of the low areal density region of the patterned organic polymer layer. The first plasma etch method employs a first etchant gas composition comprising an oxygen containing species, a nitrogen containing species and a bromine containing species. There is then etched through a second plasma etch method while employing at least the patterned organic polymer layer as an etch mask layer the blanket polysilicon layer to form the patterned polysilicon layer, while suppressing a micro-loading effect.
摘要翻译：一种在微电子制造中形成图案化多晶硅层的方法。首先提供了在微电子制造中使用的衬底层。然后在衬底层上形成覆盖多晶硅层。然后在毯状多晶硅层上形成覆盖的有机聚合物层。然后在毯状有机聚合物层上形成图案化的光致抗蚀剂层，其中图案化的光致抗蚀剂层具有高的面密度区域和低的面密度区域。然后通过第一等离子体蚀刻方法蚀刻，同时使用图案化的光致抗蚀剂层作为覆盖有机聚合物层的蚀刻掩模层，以形成图案化的有机聚合物层，同时到达覆盖多晶硅层。图案化有机聚合物层具有对应于图案化光致抗蚀剂层的高面密度区域的高面密度区域和对应于图案化光致抗蚀剂层的低面密度区域的低面密度区域。在图案化的有机聚合物层的低面密度区域的部分内，也在其上形成有机聚合物残余层。第一等离子体蚀刻方法使用包含含氧物质，含氮物质和含溴物质的第一蚀刻剂气体组合物。然后通过第二等离子体蚀刻方法蚀刻，同时至少使图案化的有机聚合物层作为掩模多晶硅层的蚀刻掩模层，以形成图案化多晶硅层，同时抑制微负载效应。

3. 发明授权

US06936544B2 Method of removing metal etching residues following a metal etchback process to improve a CMP process 失效
标题翻译：在金属回蚀工艺之后去除金属蚀刻残留物以改善CMP工艺的方法
公开(公告)号：US06936544B2
公开(公告)日：2005-08-30
申请号：US10385767
申请日：2003-03-11
申请人： Yai-Yei Huang , Yuh-Da Fan
发明人： Yai-Yei Huang , Yuh-Da Fan
IPC分类号： H01L21/02 , H01L21/3105 , H01L21/321 , H01L21/3213 , H01L21/768 , H01L21/302
CPC分类号： H01L21/32115 , H01L21/02074 , H01L21/31053 , H01L21/3212 , H01L21/76877
摘要： A method for reducing wafer surface scratching in a metal CMP process including providing a semiconductor wafer having a process surface comprising a blanket deposited metal layer; dry etching in an etchback process comprising a fluorine containing etching chemistry to remove at least a portion of the metal layer forming a metal and fluorine containing etching residue at the process surface; cleaning the process surface with a hydrofluoric acid (HF) containing cleaning solution; and carrying out a subsequent metal chemical mechanical polishing (CMP) process.
摘要翻译：一种用于减少金属CMP工艺中的晶片表面划伤的方法，包括提供具有包括覆盖沉积金属层的工艺表面的半导体晶片; 在包括含氟蚀刻化学品的回蚀工艺中进行干法蚀刻以去除在工艺表面形成金属和含氟蚀刻残渣的金属层的至少一部分; 用含有清洗液的氢氟酸（HF）清洗工艺表面; 并进行后续的金属化学机械抛光（CMP）工艺。

4. 发明授权

US6022809A Composite shadow ring for an etch chamber and method of using 有权
标题翻译：用于蚀刻室的复合阴影环和使用方法
公开(公告)号：US6022809A
公开(公告)日：2000-02-08
申请号：US205040
申请日：1998-12-03
申请人： Yuh-Da Fan
发明人： Yuh-Da Fan
IPC分类号： B28B1/02 , G03F9/00 , H01L21/302
CPC分类号： H01J37/32642 , H01J37/32091 , H01L21/31116 , H01L21/76802 , Y10S438/944
摘要： A composite shadow ring for use in an etch chamber that does not generate contaminating oxygen gas when bombarded by a gas plasma and a method for using such composite shadow ring are presented. The composite shadow ring may have a structure of a body portion of a ring shape that is made of a material that is substantially of silicon dioxide and an insert portion which is intimately joined to the body portion and is adjacent to a plasma cloud in the etch chamber when the shadow ring is positioned juxtaposed to the wafer, the insert portion of the shadow ring may also have a ring shape and is eccentric with the body portion, it generally has a diameter smaller than a diameter of the body portion, the insert portion may be fabricated of a material that does not generate oxygen when bombarded by a fluorine-containing gas plasma. The body portion may have a crosssection of a rectangle which has an upper inner corner of the rectangle missing to form a cavity for receiving an insert member intimately therein. The insert portion may further have a cross-section of a rectangle. The insert portion may be advantageously made of a material that is substantially silicon.
摘要翻译：本发明提供了一种用于在气体等离子体轰击时不产生污染氧气的蚀刻室中的复合阴影环和使用这种复合阴影环的方法。复合阴影环可以具有环形体的主体部分的结构，其由基本上由二氧化硅构成的材料和在蚀刻中与等离子体云紧密接合的插入部分构成。当阴影环与晶片并置放置时，阴影环的插入部分也可以具有环形并且与主体部分偏心，其通常具有小于主体部分的直径的直径，插入部分可以由用含氟气体等离子体轰击时不产生氧的材料制成。身体部分可以具有矩形的横截面，该矩形具有矩形的上内角缺失以形成用于在其中密切接纳插入构件的空腔。插入部分还可以具有矩形的横截面。插入部分可以有利地由基本上是硅的材料制成。

5. 发明授权

US06531326B2 Method to calibrate the wafer transfer for oxide etcher (with clamp) 有权
公开(公告)号：US06531326B2
公开(公告)日：2003-03-11
申请号：US09956354
申请日：2001-09-20
申请人： Ching-Ming Chen , Yuh-Da Fan , Pao-Ling Kuo
发明人： Ching-Ming Chen , Yuh-Da Fan , Pao-Ling Kuo
IPC分类号： H01L2100
CPC分类号： H01L22/34
摘要： A method for calibrating the wafer transfer system by using an inspection control wafer after plasma etching is described. An inspection control wafer is provided comprising a polysilicon layer overlying an oxide layer on the surface of a semiconductor substrate wherein the polysilicon layer does not cover the oxide layer for a first distance from the edge of the wafer. The inspection control wafer is entered into the wafer transfer system wherein the wafer is transferred to a spin-on-glass etchback chamber wherein the wafer is held by clamps which extend a second distance from the edge of the wafer and wherein there is designed an overlap difference between the first and second distances. The wafer is subjected to a spin-on-glass etchback step and then inspected for damage to the oxide layer. Oxide layer damage occurs if the second distance is less than the first distance by more than the overlap difference. Oxide layer damage indicates the need to recalibrate the wafer transfer system.

6. 发明申请

US20100099252A1 Methods to completely eliminate or significantly reduce defects in copper metallization in IC manufacturing 审中-公开
标题翻译：完全消除或显着减少IC制造中铜金属化缺陷的方法
公开(公告)号：US20100099252A1
公开(公告)日：2010-04-22
申请号：US12653440
申请日：2009-12-14
申请人： Chun-Hung Lin , Huang-Yi Huang , Yuh-Da Fan
发明人： Chun-Hung Lin , Huang-Yi Huang , Yuh-Da Fan
IPC分类号： H01L21/768
CPC分类号： H01L21/76843 , H01L21/76861 , H01L21/76862 , H01L21/76864 , H01L21/76865 , H01L21/76873
摘要： A method for the improved electroplating of copper onto a copper seed layer provides burnishing the surface of the copper seed layer. The burnishing treatment is used to enhance the platability of the copper seed layer. The burnishing may be a reverse electroplating or a sputter etching process. Following the burnishing of the seed layer, the copper layer that is electroplated onto the seed layer exhibits improved quality.
摘要翻译：用于改进铜在铜种子层上的电镀的方法提供抛光铜籽晶层的表面。抛光处理用于提高铜种子层的可镀性。抛光可以是反向电镀或溅射蚀刻工艺。在晶种层的抛光之后，电镀在籽晶层上的铜层表现出提高的质量。

7. 发明申请

US20080176397A1 Methods to completely eliminate or significantly reduce defects in copper metallization in IC manufacturing 审中-公开
标题翻译：完全消除或显着减少IC制造中铜金属化缺陷的方法
公开(公告)号：US20080176397A1
公开(公告)日：2008-07-24
申请号：US11827468
申请日：2007-07-12
申请人： Chun-Hung Lin , Huang-Yi Huang , Yuh-Da Fan
发明人： Chun-Hung Lin , Huang-Yi Huang , Yuh-Da Fan
IPC分类号： H01L21/768
CPC分类号： H01L21/76843 , H01L21/76861 , H01L21/76862 , H01L21/76864 , H01L21/76865 , H01L21/76873
摘要： A method for the improved electroplating of copper onto a copper seed layer provides treating the surface of a copper seed layer with nitrogen or another anaerobic gas. In another aspect, a burnishing treatment is used to enhance the platability of the copper seed layer. According to another aspect, the seed layer is annealed either at an elevated temperature or for an extended time at room temperature. According to another aspect, the seed layer surface is exposed to a chemical solution that includes a surfactant, chemicals that dissolve contaminants, or both. In another aspect, the deposition of the copper seed layer may be tailored to produce a surface morphology more suited to electroplating. Following the treatment of the seed layer, the copper layer that is electroplated onto the seed layer exhibits improved quality.
摘要翻译：用于将铜电镀改进到铜种子层上的方法提供用氮气或另一种无氧气体处理铜籽晶层的表面。另一方面，使用抛光处理来提高铜种子层的可镀性。根据另一方面，种子层在升高的温度下或在室温下延长时间退火。根据另一方面，种子层表面暴露于包含表面活性剂，溶解污染物的化学品或两者的化学溶液。在另一方面，可以调整铜籽晶层的沉积以产生更适合于电镀的表面形态。在种子层的处理之后，电镀在籽晶层上的铜层表现出提高的质量。

8. 发明申请

US20060094237A1 Methods to completely eliminate or significantly reduce defects in copper metallization in IC manufacturing 审中-公开
标题翻译：完全消除或显着减少IC制造中铜金属化缺陷的方法
公开(公告)号：US20060094237A1
公开(公告)日：2006-05-04
申请号：US10976376
申请日：2004-10-29
申请人： Chun-Hung Lin , Huang-Yi Huang , Yuh-Da Fan
发明人： Chun-Hung Lin , Huang-Yi Huang , Yuh-Da Fan
IPC分类号： H01L21/44
CPC分类号： H01L21/76843 , H01L21/76861 , H01L21/76862 , H01L21/76864 , H01L21/76865 , H01L21/76873
摘要： A method for the improved electroplating of copper on to a copper seed layer provides treating the surface of a copper seed layer with nitrogen or another anaerobic gas. In another aspect, a burnishing treatment is used to enhance the platability of the copper seed layer. According to another aspect, the seed layer is annealed either at an elevated temperature or for an extended time at room temperature. According to another aspect, the seed layer surface is exposed to a chemical solution that includes a surfactant, chemicals that dissolve contaminants, or both. In another aspect, the deposition of the copper seed layer may be tailored to produce a surface morphology more suited to electroplating. Following the treatment of the seed layer, the copper layer that is electroplated onto the seed layer exhibits improved quality.
摘要翻译：用于改进铜对铜籽晶层的电镀的方法提供用氮或另一种厌氧气体处理铜籽晶层的表面。另一方面，使用抛光处理来提高铜种子层的可镀性。根据另一方面，种子层在升高的温度下或在室温下延长时间退火。根据另一方面，种子层表面暴露于包含表面活性剂，溶解污染物的化学品或两者的化学溶液。在另一方面，可以调整铜籽晶层的沉积以产生更适合于电镀的表面形态。在种子层的处理之后，电镀在籽晶层上的铜层表现出提高的质量。

9. 发明授权

US07262067B2 Method for conductive film quality evaluation 有权
标题翻译：导电膜质量评价方法
公开(公告)号：US07262067B2
公开(公告)日：2007-08-28
申请号：US10830577
申请日：2004-04-23
申请人： Hsien-Ping Feng , Min-Yuan Cheng , Hsi-Kuei Cheng , Steven Lin , Huang-Yi Huang , Yuh-Da Fan
发明人： Hsien-Ping Feng , Min-Yuan Cheng , Hsi-Kuei Cheng , Steven Lin , Huang-Yi Huang , Yuh-Da Fan
IPC分类号： H01L21/66
CPC分类号： H01L22/20 , H01L21/76838
摘要： A method for monitoring copper film quality and for evaluating the annealing efficiency of a copper annealing process includes measuring hardness of a copper film formed on a substrate before and after annealing and comparing the hardness measurement results. The measurements can be correlated to grain boundary saturation levels, copper grain sizes and therefore conductivity. Hardness measurements may be taken at a plurality of locations throughout the substrate to account for variations in the copper film grain structure.
摘要翻译：用于监测铜膜质量和评价铜退火处理的退火效率的方法包括测量退火前后在基板上形成的铜膜的硬度，并比较硬度测量结果。测量可以与晶界饱和度，铜晶粒尺寸和导电性相关。可以在整个基板的多个位置处进行硬度测量，以考虑铜膜晶粒结构的变化。

10. 发明申请

US20050239221A1 Method for conductive film quality evaluation 有权
标题翻译：导电膜质量评价方法
公开(公告)号：US20050239221A1
公开(公告)日：2005-10-27
申请号：US10830577
申请日：2004-04-23
申请人： Hsien-Ping Feng , Min-Yuan Cheng , Hsi-Kuei Cheng , Steven Lin , Huang-Yi Huang , Yuh-Da Fan
发明人： Hsien-Ping Feng , Min-Yuan Cheng , Hsi-Kuei Cheng , Steven Lin , Huang-Yi Huang , Yuh-Da Fan
IPC分类号： H01L21/44 , H01L21/66 , H01L21/768
CPC分类号： H01L22/20 , H01L21/76838
摘要： A method for monitoring copper film quality and for evaluating the annealing efficiency of a copper annealing process includes measuring hardness of a copper film formed on a substrate before and after annealing and comparing the hardness measurement results. The measurements can be correlated to grain boundary saturation levels, copper grain sizes and therefore conductivity. Hardness measurements may be taken at a plurality of locations throughout the substrate to account for variations in the copper film grain structure.
摘要翻译：用于监测铜膜质量和评价铜退火处理的退火效率的方法包括测量退火前后在基板上形成的铜膜的硬度，并比较硬度测量结果。测量可以与晶界饱和度，铜晶粒尺寸和导电性相关。可以在整个基板的多个位置处进行硬度测量，以考虑铜膜晶粒结构的变化。

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