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1. 发明授权

US07657856B1 Method and system for parallel processing of IC design layouts 失效
标题翻译： IC设计布局并行处理方法与系统
公开(公告)号：US07657856B1
公开(公告)日：2010-02-02
申请号：US11520487
申请日：2006-09-12
申请人： Mathew Koshy , Roland Ruehl , Min Cao , Li-Ling Ma , Eitan Cadouri , Tianhao Zhang
发明人： Mathew Koshy , Roland Ruehl , Min Cao , Li-Ling Ma , Eitan Cadouri , Tianhao Zhang
IPC分类号： G06F17/50
CPC分类号： G06F17/5081
摘要： Disclosed is a method and system for processing the tasks performed by an IC layout processing tool in parallel. In some approaches, the IC layout is divided into a plurality of layout portions and one or more of the layout portions are processed in parallel, where geometric select operations are performed in which data for different layout portions may be shared between different processing entities. One approach includes the following actions: select phase one operation for performing initial select actions within layout portions; distributed regioning action for local regioning; distributed regioning action for global regioning and binary select; count select aggregation for count-based select operations; and select phase two operations for combining results of selecting of internal shapes and interface shapes.
摘要翻译：公开了一种用于并行处理由IC布局处理工具执行的任务的方法和系统。在一些方法中，IC布局被划分为多个布局部分，并且一个或多个布局部分被并行处理，其中执行几何选择操作，其中用于不同布局部分的数据可以在不同处理实体之间共享。一种方法包括以下操作：选择在布局部分内执行初始选择动作的第一阶段操作; 分布式区域划分行动; 全局分区和二进制选择的分布式分区动作; 对于基于计数的选择操作的计数选择聚合; 并选择第二阶段操作来组合内部形状和界面形状的选择结果。

2. 发明授权

US08739095B2 Method, system, and program product for interactive checking for double pattern lithography violations 有权
标题翻译：方法，系统和程序产品，用于双模式光刻违规的互动检查
公开(公告)号：US08739095B2
公开(公告)日：2014-05-27
申请号：US12719710
申请日：2010-03-08
申请人： Min Cao , Roland Ruehl
发明人： Min Cao , Roland Ruehl
IPC分类号： G06F9/455 , G06F17/50
CPC分类号： G06F17/50
摘要： Disclosed are a method, apparatus, and computer program product for performing interactive layout editing to address double patterning approaches to implement lithography of electronic designs. A spatial query is performed around the shape(s) being created during editing with the distance of allowed spacing in a single mask. If a design error is encountered, corrective editing may occur to correct the error. Checking may occur to make sure that the error detection and corrective actions can be performed interactively.
摘要翻译：公开了一种用于执行交互式布局编辑以解决实现电子设计的光刻的双重图案化方法的方法，装置和计算机程序产品。在编辑期间创建的形状周围执行空间查询，其中单个掩码中允许的间距距离。如果遇到设计错误，可能会进行纠正编辑，以纠正错误。可能会发生检查，以确保可以交互式执行错误检测和纠正措施。

3. 发明授权

US08516404B1 Methods, systems, and articles of manufacture for implementing constraint checking windows for an electronic design for multiple-patterning lithography processes 有权
标题翻译：用于实现用于多图案化光刻工艺的电子设计的约束检查窗口的方法，系统和制品
公开(公告)号：US08516404B1
公开(公告)日：2013-08-20
申请号：US13341849
申请日：2011-12-30
申请人： Min Cao , Roland Ruehl , Gilles S. C. Lamant
发明人： Min Cao , Roland Ruehl , Gilles S. C. Lamant
IPC分类号： G06F17/50
CPC分类号： G03F1/70 , G03F7/70433 , G03F7/70466
摘要： Disclosed are method(s), system(s), and article(s) of manufacture for implementing a layout of an electronic circuit using one or more constraint checking windows. The method identifies some constraints on multiple-patterning lithography and multiple constraint checking windows for the layout. The method determines one or more metrics for a constraint checking window or for a layout and assigns one or more shapes in the one or more constraint checking windows to their respective mask designs based on the one or more metrics. The method traverses through the one or more constraint checking windows until all shapes in the layout are assigned to their respective mask designs. The method may also determine a processing order for the one or more constraint checking windows based on the distribution of a type of shapes in the layout.
摘要翻译：公开了用于实现使用一个或多个约束检查窗口的电子电路布局的方法，系统和制品。该方法识别了对于多图案化光刻和布局的多个约束检查窗口的一些限制。该方法确定用于约束检查窗口或布局的一个或多个度量，并且基于一个或多个度量将一个或多个约束检查窗口中的一个或多个形状分配给它们各自的掩模设计。该方法遍历一个或多个约束检查窗口，直到布局中的所有形状分配给它们各自的掩模设计。该方法还可以基于布局中的形状类型的分布来确定一个或多个约束检查窗口的处理顺序。

4. 发明授权

US08473874B1 Method and apparatus for automatically fixing double patterning loop violations 有权
标题翻译：自动固定双重图案化环路违规的方法和装置
公开(公告)号：US08473874B1
公开(公告)日：2013-06-25
申请号：US13215113
申请日：2011-08-22
申请人： Karun Sharma , Min Cao , Roland Ruehl
发明人： Karun Sharma , Min Cao , Roland Ruehl
IPC分类号： G06F17/50 , G03F1/00 , G21K5/00
CPC分类号： G06F17/5081 , G03F1/00 , G03F7/70433 , G03F7/70466 , G21K5/00
摘要： A method for automatically generating and prioritizing several design solutions that resolve a double patterning (DP) loop violation in an IC design layout. The method of some embodiments receives a DP loop violation marker and identifies pairs of edges of shapes that form a double patterning loop based on the DP loop violation marker. For each pair of edges that violates the design rule, the method generates one or more design solutions. Each design solution moves a single edge or both edges to resolve the violation. The method of some embodiments computes the cost of applying each design solution to the IC design layout and prioritizes the generated solutions for all the identified pairs of edges based on the computed cost for each solution. The method in some embodiments then selects a solution from the prioritized solutions and applies the selected solution to the design layout.
摘要翻译：一种用于自动生成和优先排列多个设计解决方案的方法，以解决IC设计布局中的双重图案化（DP）循环违规。一些实施例的方法接收DP循环违规标记，并基于DP循环违规标记识别形成双重图案化环路的形状边缘对。对于违反设计规则的每对边缘，该方法生成一个或多个设计解决方案。每个设计解决方案都会移动单个边缘或两个边缘来解决违规。一些实施例的方法计算将每个设计解决方案应用于IC设计布局的成本，并且基于每个解决方案的计算成本来为所有所识别的边对对应生成的解决方案的优先级。一些实施例中的方法随后从优先解决的解决方案中选择解决方案，并将所选择的解决方案应用于设计布局。

5. 发明授权

US08645902B1 Methods, systems, and computer program products for implementing interactive coloring of physical design components in a physical electronic design with multiple-patterning techniques awareness 有权
标题翻译：方法，系统和计算机程序产品，用于实现具有多种图案化技术意识的物理电子设计中物理设计组件的交互式着色
公开(公告)号：US08645902B1
公开(公告)日：2014-02-04
申请号：US13445847
申请日：2012-04-12
申请人： Henry Yu , Jeffrey Markham , Min Cao , Roland Ruehl
发明人： Henry Yu , Jeffrey Markham , Min Cao , Roland Ruehl
IPC分类号： G06F17/50 , G06F15/04
CPC分类号： G06F17/5081
摘要： Various embodiments provide a constraint-driven environment to interactively determine coloring of layout components when the layout components are being modified or created and to provide feedback with visual aids to users in nearly real-time. Layout components are thus appropriately assigned to respective mask designs upon their creation. Various embodiments check or verify various constraints during creation or modification of layout components, and the layout thus remains design rule clean as constructed. Some embodiments use data structure(s) including information associated with mask identifications of objects of a cluster to change some mask identifications without considering any of the constraints governing these mask identifications. Some embodiments further determine the mask identification for an object based at least in part on whether object splitting and stitching is permitted.
摘要翻译：各种实施例提供约束驱动的环境，以在布局组件被修改或创建时交互地确定布局组件的着色，并且几乎实时地向用户提供具有视觉辅助的反馈。因此，布局组件在其创建时被适当地分配给相应的掩模设计。各种实施例在布局组件的创建或修改期间检查或验证各种约束，并且布局因此保持如构造的设计规则清洁。一些实施例使用包括与簇的对象的掩码标识相关联的信息的数据结构来改变一些掩码标识，而不考虑管理这些掩码标识的任何约束。一些实施例至少部分地基于是否允许对象分割和拼接来确定对象的掩模标识。

6. 发明授权

US09312260B2 Integrated circuits and manufacturing methods thereof 有权
标题翻译：集成电路及其制造方法
公开(公告)号：US09312260B2
公开(公告)日：2016-04-12
申请号：US13086186
申请日：2011-04-13
申请人： Ali Keshavarzi , Ta-Pen Guo , Helen Shu-Hui Chang , Hsiang-Jen Tseng , Shyue-Shyh Lin , Lee-Chung Lu , Chung-Cheng Wu , Li-Chun Tien , Jung-Chan Yang , Shu-Min Chen , Min Cao , Yung-Chin Hou
发明人： Ali Keshavarzi , Ta-Pen Guo , Helen Shu-Hui Chang , Hsiang-Jen Tseng , Shyue-Shyh Lin , Lee-Chung Lu , Chung-Cheng Wu , Li-Chun Tien , Jung-Chan Yang , Shu-Min Chen , Min Cao , Yung-Chin Hou
IPC分类号： H01L29/76 , H01L27/092 , H01L21/8238 , H01L23/485 , H01L27/02 , H01L29/423 , H01L29/66 , H01L29/78
CPC分类号： H01L27/092 , H01L21/823871 , H01L23/485 , H01L27/0207 , H01L29/0649 , H01L29/4238 , H01L29/495 , H01L29/66545 , H01L29/7833 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit includes a first diffusion area for a first type transistor. The first type transistor includes a first drain region and a first source region. A second diffusion area for a second type transistor is separated from the first diffusion area. The second type transistor includes a second drain region and a second source region. A gate electrode continuously extends across the first diffusion area and the second diffusion area in a routing direction. A first metallic structure is electrically coupled with the first source region. A second metallic structure is electrically coupled with the second drain region. A third metallic structure is disposed over and electrically coupled with the first and second metallic structures. A width of the first metallic structure is substantially equal to or larger than a width of the third metallic structure.
摘要翻译：集成电路包括用于第一类型晶体管的第一扩散区域。第一类型晶体管包括第一漏极区域和第一源极区域。用于第二类型晶体管的第二扩散区域与第一扩散区域分离。第二类型晶体管包括第二漏极区域和第二源极区域。栅电极在布线方向上连续延伸穿过第一扩散区域和第二扩散区域。第一金属结构与第一源区电耦合。第二金属结构与第二漏区电耦合。第三金属结构设置在第一和第二金属结构之上并与第一和第二金属结构电耦合。第一金属结构体的宽度基本上等于或大于第三金属结构体的宽度。

7. 发明申请

US20130094035A1 MULTIPLE PATTERNING TECHNOLOGY METHOD AND SYSTEM FOR ACHIEVING MINIMAL PATTERN MISMATCH 有权
标题翻译：用于实现最小图案误差的多种格局技术方法和系统
公开(公告)号：US20130094035A1
公开(公告)日：2013-04-18
申请号：US13275899
申请日：2011-10-18
申请人： Feng-Ming Chang , Chang-Ta Yang , Ping-Wei Wang , Min Cao
发明人： Feng-Ming Chang , Chang-Ta Yang , Ping-Wei Wang , Min Cao
IPC分类号： H04N1/60
CPC分类号： G03F1/68 , G03F1/70 , G03F7/0005 , H01L27/0207 , H01L27/1104
摘要： The present disclosure provides for many different embodiments of a multiple patterning technology method and system. An exemplary method includes receiving a pattern layout having a plurality of features; coloring each of the plurality of features one of at least two colors, thereby forming a colored pattern layout, wherein the coloring includes coloring match-sensitive features a same color; and fabricating at least two masks with the features of the colored pattern layout, wherein each mask includes features of a single color.
摘要翻译：本公开提供了多种图案化技术方法和系统的许多不同实施例。一种示例性方法包括接收具有多个特征的图案布局; 将多个特征中的每一个着色为至少两种颜色中的一种，从而形成着色图案布局，其中着色包括对相同颜色的匹配敏感特征进行着色; 以及制造具有着色图案布局的特征的至少两个掩模，其中每个掩模包括单一颜色的特征。

8. 发明申请

US20050116281A1 Multilayered dual bit memory device with improved write/erase characteristics and method of manufacturing 失效
公开(公告)号：US20050116281A1
公开(公告)日：2005-06-02
申请号：US10725234
申请日：2003-12-01
申请人： Chin-Tien Yang , Mu-Yi Lin , Yu-Wei Tseng , Min Cao , Yu-Hua Lee
发明人： Chin-Tien Yang , Mu-Yi Lin , Yu-Wei Tseng , Min Cao , Yu-Hua Lee
IPC分类号： G11C16/04 , H01L21/28 , H01L21/8246 , H01L21/8247 , H01L27/115 , H01L29/792 , H01L21/8238
CPC分类号： H01L27/11568 , G11C16/0458 , H01L21/28273 , H01L21/28282 , H01L27/115 , H01L27/11521 , H01L29/7923
摘要： A dual bit ROM multilayered structure with improved write and erase functions and a method of manufacturing is disclosed. The structure includes a pair of floating gates at the middle or nitride layer to better define the two locations of electrons representing the dual data bits collected in the middle layer.

9. 发明授权

US06844626B2 Bond pad scheme for Cu process 有权
公开(公告)号：US06844626B2
公开(公告)日：2005-01-18
申请号：US10444229
申请日：2003-05-23
申请人： Chia-Hung Lai , Jiunn-Jyi Lin , Tzong-Sheng Chang , Min Cao , Huan-Chi Tseng , Yu-Hua Lee , Chin-Tien Yang
发明人： Chia-Hung Lai , Jiunn-Jyi Lin , Tzong-Sheng Chang , Min Cao , Huan-Chi Tseng , Yu-Hua Lee , Chin-Tien Yang
IPC分类号： H01L21/28 , H01L21/44 , H01L21/60 , H01L21/768 , H01L23/48 , H01L23/485 , H01L23/52 , H01L29/40
CPC分类号： H01L24/13 , H01L24/03 , H01L24/05 , H01L24/11 , H01L2224/0401 , H01L2224/05006 , H01L2224/05624 , H01L2224/05647 , H01L2224/13007 , H01L2224/13099 , H01L2924/0001 , H01L2924/01013 , H01L2924/01014 , H01L2924/01019 , H01L2924/01029 , H01L2924/01032 , H01L2924/01033 , H01L2924/01039 , H01L2924/01073 , H01L2924/01082 , H01L2924/01083 , H01L2924/04953 , H01L2924/10329 , H01L2924/14 , H01L2924/19041 , H01L2924/19043
摘要： A novel method of forming a bond pad of a semiconductor device and a novel bond pad structure. Two passivation layers are used to form bond pads of a semiconductor device. A portion of the second passivation layer resides between adjacent bond pads, preventing shorting of the bond pads during subsequent wire bonding processes or flip-chip packaging processes.

10. 发明授权

US06674116B1 Variable capacitor using MOS gated diode with multiple segments to limit DC current 有权
公开(公告)号：US06674116B1
公开(公告)日：2004-01-06
申请号：US09683709
申请日：2002-02-05
申请人： Min Cao
发明人： Min Cao
IPC分类号： H01L27108
CPC分类号： H01L29/94
摘要： A voltage-variable capacitor uses the channel-to-substrate junction from a gated diode formed from a metal-oxide-semiconductor transistor. The transistor gate has at least two contacts that are biased to different voltages. The gate acts as a resistor with current flowing from an upper gate contact to a lower gate contact. The gate-to-source voltage varies as a function of the position. A critical voltage is where the gate-to-source voltage is equal to the transistor threshold. A portion of the gate that has gate voltages above the critical voltage has an inversion layer or conducting channel under the gate. Another portion of the gate has gate voltages below the critical voltage, and thus no channel forms. By varying either the gate voltages or the source voltage, the area of the gate that has a channel under it is varied, varying the channel-to-substrate capacitance. Separate gate arms reduce bias current.

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