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1. 发明申请

US20110007066A1 DATA TRANSMITTING METHOD FOR TRANSMITTING DATA BETWEEN TIMING CONTROLLER AND SOURCE DRIVER OF DISPLAY AND DISPLAY USING THE SAME 审中-公开
标题翻译：用于发送定时控制器和显示器的源驱动器之间的数据的数据传输方法
公开(公告)号：US20110007066A1
公开(公告)日：2011-01-13
申请号：US12501211
申请日：2009-07-10
申请人： Chin-Tien Chang , Ying-Lieh Chen
发明人： Chin-Tien Chang , Ying-Lieh Chen
IPC分类号： G09G5/00
CPC分类号： G09G3/3611 , G09G2310/08 , G09G2370/08
摘要： A data transmission method for transmitting data between a timing controller and a source driver of a display and a display using the same are disclosed. The transmission method includes recognizing a start of a blank period of a frame period; sampling de-skew data on a data bus during the blank period based on a data clock; performing a de-skew function by comparing the sampled de-skew data with a predetermined de-skew code and adjusting the data clock; recognizing a start of a data input period of the frame period; and sampling pixel data on the data bus during the data input period based on the adjusted data clock. The display includes a timing controller, a data bus, and a source driver. The source driver is connected to the timing controller via the data bus for performing the data transmission method.
摘要翻译：公开了一种用于在定时控制器和显示器的源驱动器和使用其的显示器之间传送数据的数据传输方法。发送方法包括：识别帧周期的空白期间的开始; 基于数据时钟在空白时段期间在数据总线上采样去偏移数据; 通过将采样的去偏移数据与预定的去偏移码进行比较并调整数据时钟来执行去偏移功能; 识别帧周期的数据输入周期的开始; 并且在数据输入周期期间，基于经调整的数据时钟在数据总线上采样像素数据。显示器包括定时控制器，数据总线和源驱动器。源驱动器经由用于执行数据传输方法的数据总线连接到定时控制器。

2. 发明申请

US20100045319A1 WAFER AND TEST METHOD THEREOF 有权
标题翻译：其方法及其测试方法
公开(公告)号：US20100045319A1
公开(公告)日：2010-02-25
申请号：US12609365
申请日：2009-10-30
申请人： Tzong-Yau Ku , Chien-Ru Chen , Chin-Tien Chang , Ying-Lieh Chen , Lin-Kai Bu
发明人： Tzong-Yau Ku , Chien-Ru Chen , Chin-Tien Chang , Ying-Lieh Chen , Lin-Kai Bu
IPC分类号： G01R1/06 , G01R31/02 , G01R31/26
CPC分类号： G01R31/2851 , G01R31/2831 , G01R31/2884
摘要： A wafer and a test method thereof are provided. The invention utilizes a first group of probes to perform a high voltage stress (HVS) test on a first chip, and utilizes a second group of probes to perform a function test on a second chip, where a period of the high voltage stress test overlaps a period of the function test, thereby greatly decreasing the test time of the wafer.
摘要翻译：提供晶片及其测试方法。本发明利用第一组探针在第一芯片上执行高电压应力（HVS）测试，并且利用第二组探针在第二芯片上进行功能测试，其中高压应力测试的周期重叠功能测试的一段时间，从而大大降低了晶片的测试时间。

3. 发明申请

US20090251174A1 OUTPUT BUFFER OF A SOURCE DRIVER APPLIED IN A DISPLAY 有权
标题翻译：显示器中使用的源驱动器的输出缓冲器
公开(公告)号：US20090251174A1
公开(公告)日：2009-10-08
申请号：US12061255
申请日：2008-04-02
申请人： Ying-Lieh Chen , Chin-Tien Chang , Hsu-Yu Hsiao
发明人： Ying-Lieh Chen , Chin-Tien Chang , Hsu-Yu Hsiao
IPC分类号： H03K3/00
CPC分类号： G09G3/3688 , G09G2310/0291 , G09G2330/021
摘要： An output buffer and a controlling method are disclosed. The output buffer comprises an upper buffer and a lower buffer. In the controlling method, at first, a first voltage (V1) and a second voltage (V2) are applied on the upper buffer, and a third voltage (V3) and a fourth voltage (V4) are applied on the lower buffer, wherein V1>V2, V1>V4, V3>V2, and V3>V4. Then, the upper buffer is operated to output data to a plurality of pixels thereby operating the liquid crystals of the pixels over an upper supply range, wherein the upper supply range is from V1 to V2. Thereafter, the lower buffer is operated to output data to the pixels thereby operating the liquid crystals of the pixels over a lower supply range, wherein the lower supply range is from V3 to V4.
摘要翻译：公开了一种输出缓冲器和控制方法。输出缓冲器包括上缓冲器和下缓冲器。在控制方法中，首先，在上缓冲器上施加第一电压（V1）和第二电压（V2），在下缓冲器上施加第三电压（V3）和第四电压（V4），其中 V1> V2，V1> V4，V3> V2，V3> V4。然后，操作上缓冲器以将数据输出到多个像素，从而在上电源范围上操作像素的液晶，其中上电源范围为V1至V2。此后，操作下缓冲器以向像素输出数据，从而在较低的供给范围上操作像素的液晶，其中较低的供给范围为V3至V4。

4. 发明申请

US20080062111A1 Apparatus for Driving a Display 审中-公开
标题翻译：用于驾驶显示器的装置
公开(公告)号：US20080062111A1
公开(公告)日：2008-03-13
申请号：US11531350
申请日：2006-09-13
申请人： Chin-Tien Chang , Ying-Lieh Chen , Lin-Kai Bu
发明人： Chin-Tien Chang , Ying-Lieh Chen , Lin-Kai Bu
IPC分类号： G09G3/36
CPC分类号： G09G3/3655 , G09G2320/0276
摘要： The present invention discloses an apparatus for driving a display in which each pixels of the display receives a driving voltage and a common voltage, and a luminance of each pixel is determined by a difference between the received driving voltage and the common voltage. The apparatus comprises a plurality of source driver chips, each of which receives a pixel value and generates the driving voltage corresponding to the pixel value according to a plurality of Gamma voltages. The common voltage is generated by at least one of the source driver chips.
摘要翻译：本发明公开了一种用于驱动显示器的装置，其中显示器的每个像素接收驱动电压和公共电压，并且每个像素的亮度由接收到的驱动电压和公共电压之间的差确定。该装置包括多个源极驱动器芯片，每个源极驱动器芯片接收像素值，并根据多个伽马电压产生与像素值对应的驱动电压。公共电压由至少一个源极驱动器芯片产生。

5. 发明申请

US20070159501A1 A DATA DRIVER 审中-公开
标题翻译：数据驱动器
公开(公告)号：US20070159501A1
公开(公告)日：2007-07-12
申请号：US11279670
申请日：2006-04-13
申请人： Ying-Lieh Chen , Chin-Tien Chang
发明人： Ying-Lieh Chen , Chin-Tien Chang
IPC分类号： G09G5/10
CPC分类号： G09G3/2011 , G09G2310/027 , G09G2320/0242 , G09G2320/0276
摘要： A data driver has several gamma-voltage generating circuits and several driving channels. The gamma-voltage generating circuits are used to process gamma-voltages of different colors. Each two groups of the driving channels are correspondingly coupled with the gamma-voltage generating circuit that generates a single color and is separately disposed at either side of the corresponding gamma generating circuit for outputting the gamma-voltages of the same color to a display panel.
摘要翻译：一个数据驱动器有几个伽玛电压发生电路和几个驱动通道。 γ电压发生电路用于处理不同颜色的伽马电压。每两组驱动通道相应地与产生单一颜色的伽玛电压发生电路耦合，并且分别设置在相应伽马发生电路的任一侧，以将相同颜色的伽马电压输出到显示面板。

6. 发明授权

US08717349B2 Source driver 有权
标题翻译：源驱动程序
公开(公告)号：US08717349B2
公开(公告)日：2014-05-06
申请号：US12549636
申请日：2009-08-28
申请人： Chien-Hung Tsai , Jia-Hui Wang , Chin-Tien Chang , Ying-Lieh Chen
发明人： Chien-Hung Tsai , Jia-Hui Wang , Chin-Tien Chang , Ying-Lieh Chen
IPC分类号： G06F3/038
CPC分类号： G09G3/3688 , G09G2320/0223
摘要： A source driver adapted to drive a display panel is provided herein. The source driver includes a first output buffer, a detection module and a conversion module. The first output buffer enhances a first pixel signal and thereby outputs a first enhanced pixel signal. The detection module detects a rise time of the first enhanced pixel signal. The conversion module adjusts a driving capability of the first output buffer in response to the rise time for adjusting a slew rate of the first output buffer. Therefore, the first output buffer in the source driver can dynamically and automatically adjusts the slew rate of the first output buffer through a feedback mechanism composed of the detection module and the conversion module.
摘要翻译：本文提供了适于驱动显示面板的源驱动器。源驱动器包括第一输出缓冲器，检测模块和转换模块。第一输出缓冲器增强第一像素信号，从而输出第一增强像素信号。检测模块检测第一增强像素信号的上升时间。转换模块响应于用于调整第一输出缓冲器的转换速率的上升时间来调整第一输出缓冲器的驱动能力。因此，源驱动器中的第一个输出缓冲器可以通过由检测模块和转换模块组成的反馈机制来动态和自动地调整第一输出缓冲器的转换速率。

7. 发明申请

US20090058438A1 WAFER, TEST SYSTEM THEREOF, TEST METHOD THEREOF AND TEST DEVICE THEREOF 有权
标题翻译： WAFER，测试系统及其测试方法及其测试设备
公开(公告)号：US20090058438A1
公开(公告)日：2009-03-05
申请号：US11848954
申请日：2007-08-31
申请人： Tzong-Yau Ku , Chien-Ru Chen , Chin-Tien Chang , Ying-Lieh Chen , Lin-Kai Bu
发明人： Tzong-Yau Ku , Chien-Ru Chen , Chin-Tien Chang , Ying-Lieh Chen , Lin-Kai Bu
IPC分类号： G01R31/26
CPC分类号： G01R31/2851 , G01R31/2831 , G01R31/2884
摘要： A wafer, a test system thereof, a test method thereof and a test device thereof are provided. The present invention utilizes a first group of probes to perform a high voltage stress (HVS) test on a first chip, and utilizes a second group of probes to perform a function test on a second chip, where a period of the high voltage stress test overlaps a period of the function test, thereby greatly decreasing the test time of the wafer.
摘要翻译：提供晶片，其测试系统，其测试方法和测试装置。本发明利用第一组探针在第一芯片上执行高压应力（HVS）测试，并利用第二组探针在第二芯片上执行功能测试，其中高压应力测试与功能测试的周期重叠，从而大大降低了晶片的测试时间。

8. 发明授权

US07446568B2 Receiver start-up compensation circuit 有权
标题翻译：接收机启动补偿电路
公开(公告)号：US07446568B2
公开(公告)日：2008-11-04
申请号：US11420771
申请日：2006-05-29
申请人： Chin-Tien Chang , Chien-Ru Chen , Ying-Lieh Chen
发明人： Chin-Tien Chang , Chien-Ru Chen , Ying-Lieh Chen
IPC分类号： H03K19/0175 , H03K19/094
CPC分类号： G05F3/262
摘要： An integrated circuit includes a current mirror circuit for providing a current at an output end, a power-down switch coupled to the output end of the current mirror circuit for controlling access of the current generated by the current mirror circuit based on signals received at a control end of the power-down switch, and a compensating unit coupled to a bias end of the current mirror circuit and the power-down switch for stabilizing voltages at the bias end of the current mirror circuit.
摘要翻译：一种集成电路包括用于在输出端提供电流的电流镜电路，耦合到电流镜电路的输出端的掉电开关，用于根据在电流镜电路中接收的信号控制由电流镜电路产生的电流的存取掉电开关的控制端，以及耦合到电流镜电路的偏置端的补偿单元和用于稳定电流镜电路的偏置端的电压的掉电开关。

9. 发明授权

US08009155B2 Output buffer of a source driver applied in a display 有权
标题翻译：显示屏中应用的源驱动程序的输出缓冲区
公开(公告)号：US08009155B2
公开(公告)日：2011-08-30
申请号：US12061255
申请日：2008-04-02
申请人： Ying-Lieh Chen , Chin-Tien Chang , Hsu-Yu Hsiao
发明人： Ying-Lieh Chen , Chin-Tien Chang , Hsu-Yu Hsiao
IPC分类号： G06F3/038 , G09G5/00
CPC分类号： G09G3/3688 , G09G2310/0291 , G09G2330/021
摘要： An output buffer and a controlling method are disclosed. The output buffer comprises an upper buffer and a lower buffer. In the controlling method, at first, a first voltage (V1) and a second voltage (V2) are applied on the upper buffer, and a third voltage (V3) and a fourth voltage (V4) are applied on the lower buffer, wherein V1>V2, V1>V4, V3>V2, and V3>V4. Then, the upper buffer is operated to output data to a plurality of pixels thereby operating the liquid crystals of the pixels over an upper supply range, wherein the upper supply range is from V1 to V2. Thereafter, the lower buffer is operated to output data to the pixels thereby operating the liquid crystals of the pixels over a lower supply range, wherein the lower supply range is from V3 to V4.
摘要翻译：公开了一种输出缓冲器和控制方法。输出缓冲器包括上缓冲器和下缓冲器。在控制方法中，首先，在上缓冲器上施加第一电压（V1）和第二电压（V2），在下缓冲器上施加第三电压（V3）和第四电压（V4），其中 V1> V2，V1> V4，V3> V2，V3> V4。然后，操作上缓冲器以将数据输出到多个像素，从而在上电源范围上操作像素的液晶，其中上电源范围为V1至V2。此后，操作下缓冲器以向像素输出数据，从而在较低的供给范围上操作像素的液晶，其中较低的供给范围为V3至V4。

10. 发明申请

US20110032240A1 BUFFERING CIRCUIT WITH REDUCED DYNAMIC POWER CONSUMPTION 有权
标题翻译：减少动态电力消耗电路
公开(公告)号：US20110032240A1
公开(公告)日：2011-02-10
申请号：US12536050
申请日：2009-08-05
申请人： Jia-Hui Wang , Chien-Hung Tsai , Ying-Lieh Chen , Chin-Tien Chang
发明人： Jia-Hui Wang , Chien-Hung Tsai , Ying-Lieh Chen , Chin-Tien Chang
IPC分类号： G09G5/00 , H03F3/16 , H03L5/00
CPC分类号： H03F3/3022 , G09G3/2092 , G09G2300/0426 , G09G2330/021 , G09G2360/18 , H03F1/0205
摘要： A buffering circuit with reduced power consumption is provided. The output buffering circuit includes first and second amplifier circuits. The first amplifier circuit includes a first input stage and a first output stage both coupled between a first power voltage and a second power voltage lower than the first power voltage, and an assistant discharging unit configured to provide a discharging current flowing from a first output node to a first intermediate power voltage during a discharging operation of the first amplifier circuit. The second amplifier circuit includes a second input stage and a second output stage both coupled between the first power voltage and the second power voltage, and an assistant charging unit configured to provide a charging current flowing from a second intermediate power voltage to a second output node during a charging operation of the second amplifier circuit. The first and second amplifier circuits can have reduced output voltage ranges and hence reduced total power consumption.
摘要翻译：提供了具有降低功耗的缓冲电路。输出缓冲电路包括第一和第二放大器电路。第一放大器电路包括耦合在第一电源电压和低于第一电源电压的第二电源电压之间的第一输入级和第一输出级，以及辅助放电单元，被配置为提供从第一输出节点在第一放大器电路的放电操作期间到第一中间电源电压。第二放大器电路包括耦合在第一电源电压和第二电源电压之间的第二输入级和第二输出级，以及辅助充电单元，被配置为提供从第二中间电源电压流向第二输出节点的充电电流在第二放大器电路的充电操作期间。第一和第二放大器电路可以具有降低的输出电压范围，从而降低总功耗。

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