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1. 发明授权

US09671685B2 Lithographic plane check for mask processing 有权
公开(公告)号：US09671685B2
公开(公告)日：2017-06-06
申请号：US12976646
申请日：2010-12-22
申请人： Chin-Hsiang Lin , Heng-Jen Lee , I-Hsiung Huang , Chih-Chiang Tu , Chun-Jen Chen , Rick Lai
发明人： Chin-Hsiang Lin , Heng-Jen Lee , I-Hsiung Huang , Chih-Chiang Tu , Chun-Jen Chen , Rick Lai
IPC分类号： G06F17/50 , G03F1/72 , G03F1/86
CPC分类号： G03F1/72 , G03F1/86
摘要： The present disclosure provides for many different embodiments. An exemplary method can include providing a mask fabricated according to a design pattern; extracting a mask pattern from the mask; converting the mask pattern into a rendered mask pattern, wherein the simulated design pattern includes the design pattern and any defects in the mask; simulating a lithography process using the rendered mask pattern to create a virtual wafer pattern; and determining whether any defects in the mask are critical based on the virtual wafer pattern. The critical defects in the mask can be repaired.

2. 发明申请

US20110159410A1 COST-EFFECTIVE METHOD FOR EXTREME ULTRAVIOLET (EUV) MASK PRODUCTION 有权
标题翻译：用于极端超紫外线（EUV）掩蔽生产的成本有效的方法
公开(公告)号：US20110159410A1
公开(公告)日：2011-06-30
申请号：US12650985
申请日：2009-12-31
申请人： Chin-Hsiang Lin , Heng-Jen Lee , I-Hsiung Huang , Chih-Chiang Tu , Chun-Jen Chen , Rick Lai
发明人： Chin-Hsiang Lin , Heng-Jen Lee , I-Hsiung Huang , Chih-Chiang Tu , Chun-Jen Chen , Rick Lai
IPC分类号： G03F1/00 , G06F17/50
CPC分类号： G03F1/24 , G03F1/72 , G03F1/84
摘要： The present disclosure provides for many different embodiments. An exemplary method can include providing a blank mask and a design layout to be patterned on the blank mask, the design layout including a critical area; inspecting the blank mask for defects and generating a defect distribution map associated with the blank mask; mapping the defect distribution map to the design layout; performing a mask making process; and performing a mask defect repair process based on the mapping.
摘要翻译：本公开提供了许多不同的实施例。示例性方法可以包括提供空白掩模和要在空白掩模上图案化的设计布局，所述设计布局包括临界区域; 检查空白掩模的缺陷并产生与空白掩模相关联的缺陷分布图; 将缺陷分布图映射到设计布局; 进行面膜制作过程; 以及基于所述映射执行掩模缺陷修复处理。

3. 发明授权

US08592102B2 Cost-effective method for extreme ultraviolet (EUV) mask production 有权
标题翻译：用于极紫外（EUV）掩模生产的成本效益高的方法
公开(公告)号：US08592102B2
公开(公告)日：2013-11-26
申请号：US12650985
申请日：2009-12-31
申请人： Chin-Hsiang Lin , Heng-Jen Lee , I-Hsiung Huang , Chih-Chiang Tu , Chun-Jen Chen , Rick Lai
发明人： Chin-Hsiang Lin , Heng-Jen Lee , I-Hsiung Huang , Chih-Chiang Tu , Chun-Jen Chen , Rick Lai
IPC分类号： G03F1/24 , G03F1/72 , G03F1/84
CPC分类号： G03F1/24 , G03F1/72 , G03F1/84
摘要： The present disclosure provides for many different embodiments. An exemplary method can include providing a blank mask and a design layout to be patterned on the blank mask, the design layout including a critical area; inspecting the blank mask for defects and generating a defect distribution map associated with the blank mask; mapping the defect distribution map to the design layout; performing a mask making process; and performing a mask defect repair process based on the mapping.
摘要翻译：本公开提供了许多不同的实施例。示例性方法可以包括提供空白掩模和要在空白掩模上图案化的设计布局，所述设计布局包括临界区域; 检查空白掩模的缺陷并产生与空白掩模相关联的缺陷分布图; 将缺陷分布图映射到设计布局; 进行面膜制作过程; 以及基于所述映射执行掩模缺陷修复处理。

4. 发明申请

US20110161893A1 LITHOGRAPHIC PLANE CHECK FOR MASK PROCESSING 有权
标题翻译：用于掩模加工的平版印刷机检查
公开(公告)号：US20110161893A1
公开(公告)日：2011-06-30
申请号：US12976646
申请日：2010-12-22
申请人： CHIN-HSIANG LIN , Heng-Jen Lee , I-Hsiung Huang , Chih-Chiang Tu , Chun-Jen Chen , Rick Lai
发明人： CHIN-HSIANG LIN , Heng-Jen Lee , I-Hsiung Huang , Chih-Chiang Tu , Chun-Jen Chen , Rick Lai
IPC分类号： G06F17/50
CPC分类号： G03F1/72 , G03F1/86
摘要： The present disclosure provides for many different embodiments. An exemplary method can include providing a mask fabricated according to a design pattern; extracting a mask pattern from the mask; converting the mask pattern into a rendered mask pattern, wherein the simulated design pattern includes the design pattern and any defects in the mask; simulating a lithography process using the rendered mask pattern to create a virtual wafer pattern; and determining whether any defects in the mask are critical based on the virtual wafer pattern. The critical defects in the mask can be repaired.
摘要翻译：本公开提供了许多不同的实施例。示例性方法可以包括提供根据设计图案制造的掩模; 从掩模中提取掩模图案; 将掩模图案转换成渲染的掩模图案，其中模拟设计图案包括设计图案和掩模中的任何缺陷; 使用所渲染的掩模图案来模拟光刻工艺以产生虚拟晶片图案; 以及基于所述虚拟晶片图案确定所述掩模中的任何缺陷是否是关键的。面罩中的关键缺陷可以修复。

5. 发明授权

US08336020B2 Computing device and method for inspecting layout of printed circuit board 失效
标题翻译：用于检查印刷电路板布局的计算装置和方法
公开(公告)号：US08336020B2
公开(公告)日：2012-12-18
申请号：US13213072
申请日：2011-08-18
申请人： Dan-Chen Wu , Shou-Kuo Hsu , Cheng-Hsien Lee , Chun-Jen Chen
发明人： Dan-Chen Wu , Shou-Kuo Hsu , Cheng-Hsien Lee , Chun-Jen Chen
IPC分类号： G06F17/50
CPC分类号： G06F17/5081
摘要： In a method for inspecting the layout of a printed circuit board (PCB), a component to be checked is determined from an electronic layout diagram of the PCB, and a power transmission line which may be serving that component is selected. The layout diagram is checked to determine whether the component is connected to the power transmission line, and further checked to determine whether more than one ground pins of the component is connected to the power transmission line. Vias that are shared by two or more ground pins of the component are determined if more than one ground pin is connected to the power transmission line. Shared vias are marked on the layout diagram.
摘要翻译：在用于检查印刷电路板（PCB）的布局的方法中，从PCB的电子布局图确定要检查的部件，并且可以选择可用于该部件的输电线。检查布局图以确定组件是否连接到电力传输线，并进一步检查以确定组件的多个接地引脚是否连接到电力传输线。如果多个接地引脚连接到电力传输线，则确定由组件的两个或更多个接地引脚共享的通孔。共享通孔在布局图上标出。

6. 发明授权

US08261230B2 System and method for optimizing current overload protection circuit 失效
标题翻译：优化电流过载保护电路的系统和方法
公开(公告)号：US08261230B2
公开(公告)日：2012-09-04
申请号：US12774685
申请日：2010-05-05
申请人： Tsung-Sheng Huang , Chun-Jen Chen , Duen-Yi Ho , Wei-Chieh Chou
发明人： Tsung-Sheng Huang , Chun-Jen Chen , Duen-Yi Ho , Wei-Chieh Chou
IPC分类号： G06F17/50 , G06F9/455 , G05D17/00
CPC分类号： G06F17/5063
摘要： A system for optimizing a current overload protection circuit includes an input device, a data storage device, a central processing device, and a display. The central processing device includes a storage module, a control module, and a calculation module. The storage module stores a VI application therein. The control module receives instructions from the input device and selects virtual electronic components of the current overload protection circuit from the data storage device and connection of the selected electronic components. The current overload protection circuit is completed and run in the VI application; electronic components significantly affecting the maximum protection current are labeled. The calculation module calculates normal distribution samples of the current overload protection circuit based on the labeled electronic components. The display shows whether the current overload protection circuit meets a process capability standard.
摘要翻译：用于优化电流过载保护电路的系统包括输入装置，数据存储装置，中央处理装置和显示器。中央处理装置包括存储模块，控制模块和计算模块。存储模块在其中存储VI应用。控制模块从输入设备接收指令，并从数据存储设备中选择电流过载保护电路的虚拟电子部件，并选择电子部件的连接。电流过载保护电路在VI应用中完成并运行; 显着影响最大保护电流的电子元件被标记。计算模块基于标记的电子元件计算电流过载保护电路的正态分布样本。显示屏显示电流过载保护电路是否符合过程能力标准。

7. 发明授权

US08237499B2 Feedforward controlled envelope modulator and feedforward control circuit thereof 有权
标题翻译：前馈控制包络调制器及其前馈控制电路
公开(公告)号：US08237499B2
公开(公告)日：2012-08-07
申请号：US12775486
申请日：2010-05-07
申请人： Chun-Jen Chen , Chih-Chang Lee
发明人： Chun-Jen Chen , Chih-Chang Lee
IPC分类号： H03G3/20
CPC分类号： H03F3/24 , H03F1/0266 , H03F3/195 , H03F2200/336 , H03F2200/451 , H03F2200/555
摘要： The present disclosure illustrates a feedforward controlled envelope modulator and a feedforward control circuit thereof. The feedforward controlled envelope modulator comprises a linear amplifier circuit, a switching amplifier, and a feedforward control circuit. The linear amplifier circuit amplifies an input voltage signal, so as to output an output voltage signal to a load node. The switching amplifier receives a comparison signal, and outputs a switching current to the load node according to the comparison signal. The feedforward control circuit comprises a duplicate linear amplifier circuit and a hysteresis comparator. The duplicate linear amplifier circuit amplifies the input voltage signal, so as to output a reference voltage signal, wherein an amplifying gain of the duplicate linear amplifier circuit is identical to an amplifying gain of the linear amplifier circuit. The hysteresis comparator compares the output voltage signal and the reference voltage signal, so as to output the comparison signal.
摘要翻译：本公开示出了前馈控制包络调制器及其前馈控制电路。前馈控制包络调制器包括线性放大器电路，开关放大器和前馈控制电路。线性放大器电路放大输入电压信号，以将输出电压信号输出到负载节点。开关放大器接收比较信号，并根据比较信号将负载节点输出开关电流。前馈控制电路包括一个重复的线性放大器电路和一个滞后比较器。重复的线性放大器电路放大输入电压信号，以便输出参考电压信号，其中重复线性放大器电路的放大增益与线性放大器电路的放大增益相同。迟滞比较器比较输出电压信号和参考电压信号，以输出比较信号。

8. 发明授权

US08036611B2 Polar transmitter, method and apparatus for phase modulation 有权
标题翻译：极性发射机，相位调制方法和装置
公开(公告)号：US08036611B2
公开(公告)日：2011-10-11
申请号：US12436016
申请日：2009-05-05
申请人： Huan-Ke Chiu , Chun-Jen Chen
发明人： Huan-Ke Chiu , Chun-Jen Chen
IPC分类号： H04B1/04
CPC分类号： H03C5/00
摘要： A phase modulation method with a polar transmitter. A target frequency is first designated by comparing the RF signal with a reference frequency and the phase sample. An oscillator control word is generated based on the target frequency. A digital oscillator can modulate from a first phase to a second phase to synthesize a preliminary RF signal based on the oscillator control word. When the target frequency exceeds the modulation capability of the digital oscillator, the oscillator control word is generated based on the target frequency minus 180 degrees, and the preliminary RF signal is shifted by 180 degrees to be the RF signal having the target frequency. When the target frequency does not exceed the modulation capability of the digital oscillator, the oscillator control word is generated solely based on the target frequency to output the preliminary RF signal to be the RF signal having the target frequency.
摘要翻译：一种带极性发射机的相位调制方法。首先通过将RF信号与参考频率和相位采样进行比较来指定目标频率。基于目标频率产生振荡器控制字。数字振荡器可以从第一相位调制到第二相位，以基于振荡器控制字来合成初步RF信号。当目标频率超过数字振荡器的调制能力时，基于目标频率减去180度产生振荡器控制字，并将初步RF信号偏移180度作为具有目标频率的RF信号。当目标频率不超过数字振荡器的调制能力时，仅基于目标频率产生振荡器控制字，以将初步RF信号输出为具有目标频率的RF信号。

9. 发明授权

US07973981B2 Method for selecting and adjusting scanner illuminant 有权
标题翻译：选择和调整扫描仪光源的方法
公开(公告)号：US07973981B2
公开(公告)日：2011-07-05
申请号：US12696232
申请日：2010-01-29
申请人： Chun-Jen Chen
发明人： Chun-Jen Chen
IPC分类号： H04N1/04 , H04N1/46
CPC分类号： H04N1/00885 , H04N1/00901 , H04N1/00904
摘要： A scanner includes a first illuminant device having a first power associated therewith, and a second illuminant device having a second power associated therewith. The first power is greater than the second power, and each of the first illuminant device and the second illuminant device is configured to selectively scan a document. The scanner is configured to select one of the first illuminant device and the second illuminant device based, at least in part on, a level of power supplied to the scanner via a power source, and perform a single scan of the document using only the selected one of the first illuminant device and the second illuminant device.
摘要翻译：扫描仪包括具有与其相关联的第一功率的第一光源装置和具有与其相关联的第二功率的第二光源装置。第一功率大于第二功率，并且第一光源装置和第二光源装置中的每一个被配置为选择性地扫描文件。扫描器被配置为至少部分地基于通过电源提供给扫描仪的电力水平来选择第一照明装置和第二照明装置中的一个，并且仅使用所选择的文件执行对文件的单次扫描第一光源装置和第二光源装置之一。

10. 发明申请

US20100210711A1 Methods and Compositions for the Treatment of Sterile Inflammation 有权
标题翻译：用于治疗无菌性炎症的方法和组合
公开(公告)号：US20100210711A1
公开(公告)日：2010-08-19
申请号：US12769983
申请日：2010-04-29
申请人： Kenneth L. Rock , Chun-Jen Chen
发明人： Kenneth L. Rock , Chun-Jen Chen
IPC分类号： A61K31/713 , A61P29/00
CPC分类号： A61K31/7088 , G01N33/5008 , G01N33/6869 , G01N2333/4703
摘要： Described are methods and compositions that inhibit IL-1 signalling for the treatment of acute inflammatory response to cell necrosis, and the attendant collateral tissue damage.
摘要翻译：描述了抑制IL-1信号传导治疗对细胞坏死的急性炎症反应以及伴随的侧支组织损伤的方法和组合物。

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