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1. 发明申请

US20130061186A1 MULTI-PATTERNING METHOD 有权
公开(公告)号：US20130061186A1
公开(公告)日：2013-03-07
申请号：US13224486
申请日：2011-09-02
申请人： Chin-Chang HSU , Ying-Yu Shen , Wen-Ju Yang , Hsiao-Shu Chao , Yi-Kan Cheng
发明人： Chin-Chang HSU , Ying-Yu Shen , Wen-Ju Yang , Hsiao-Shu Chao , Yi-Kan Cheng
IPC分类号： G06F17/50
CPC分类号： G06F17/50 , G03F1/70
摘要： A method includes receiving data representing a layout of a DPT-layer of an integrated circuit generated by a place and route tool. The layout includes a plurality of polygons to be formed in the DPT-layer by a multi-patterning process. First and second ones of the plurality of polygons to be formed using first and second photomasks, respectively are identified. Any intervening polygons along a first path connecting the first polygon to the second polygon, and separator regions between adjacent polygons along the first path are identified. The separator regions have sizes less than a minimum threshold distance between polygons formed on the first photomask. The separator regions are counted. A multi-patterning conflict is identified, if the count of separator regions is even, prior to assigning all remaining ones of the plurality of polygons to the first or second masks.

2. 发明申请

US20120210279A1 DECOMPOSITION AND MARKING OF SEMICONDUCTOR DEVICE DESIGN LAYOUT IN DOUBLE PATTERNING LITHOGRAPHY 有权
标题翻译：半导体器件的分解和标记设计设计布局在双向图案中
公开(公告)号：US20120210279A1
公开(公告)日：2012-08-16
申请号：US13027520
申请日：2011-02-15
申请人： Chin-Chang HSU , Wen-Ju YANG , Hsiao-Shu CHAO , Yi-Kan CHENG , Lee-Chung LU
发明人： Chin-Chang HSU , Wen-Ju YANG , Hsiao-Shu CHAO , Yi-Kan CHENG , Lee-Chung LU
IPC分类号： G06F17/50
CPC分类号： G03F1/70 , G03F7/70433 , G03F7/70466
摘要： Provided is a system and method for assessing a design layout for a semiconductor device level and for determining and designating different features of the design layout to be formed by different photomasks by decomposing the design layout. The features are designated by markings that associate the various device features with the multiple photomasks upon which they will be formed and then produced on a semiconductor device level using double patterning lithography, DPL, techniques. The markings are done at the device level and are included on the electronic file provided by the design house to the photomask foundry. In addition to overlay and critical dimension considerations for the design layout being decomposed, various other device criteria, design criteria processing criteria and their interrelation are taken into account, as well as device environment and the other device layers, when determining and marking the various device features.
摘要翻译：提供了一种用于评估半导体器件级的设计布局并通过分解设计布局来确定和指定由不同光掩模形成的设计布局的不同特征的系统和方法。这些特征由标记指定，该标记将各种器件特征与将在其上形成的多个光掩模相关联，然后使用双重图案化光刻DPL技术在半导体器件层面上产生。标记是在设备级完成的，并被包括在由设计公司提供给光掩模铸造厂的电子文件中。除了正在分解的设计布局的重叠和关键维度考虑之外，在确定和标记各种设备时，还考虑了各种其他设备标准，设计标准处理标准及其相关性以及设备环境和其他设备层特征。

3. 发明申请

US20130074018A1 MULTI-PATTERNING METHOD 有权
标题翻译：多图案方法
公开(公告)号：US20130074018A1
公开(公告)日：2013-03-21
申请号：US13238127
申请日：2011-09-21
申请人： Chin-Chang HSU , Wen-Ju Yang , Hsiao-Shu Chao , Yi-Kan Cheng
发明人： Chin-Chang HSU , Wen-Ju Yang , Hsiao-Shu Chao , Yi-Kan Cheng
IPC分类号： G06F17/50
CPC分类号： G03F1/70
摘要： A method comprises (a) receiving data representing a layout of a DPT-layer of an integrated circuit generated by a place and route tool, the layout including a plurality of polygons to be formed in the DPT-layer by a multi-patterning process; (b) receiving at least one identification of a subset of the plurality of polygons that are to be formed in the DPT-layer using the same photomask as each other; (c) constructing a graph of the subset of the plurality of polygons and any intervening polygons of the plurality of polygons, where the subset of the plurality of polygons are represented in the graph by a single node, the graph including connections connecting adjacent ones of the polygons in the graph that are positioned within a threshold distance of each other; and (d) identifying a multi-patterning conflict if any subset of the connections form an odd loop.
摘要翻译：一种方法包括（a）接收表示由位置和路线工具生成的集成电路的DPT层的布局的数据，该布局包括通过多图案化工艺在DPT层中形成的多个多边形; （b）使用彼此相同的光掩模来接收要在DPT层中形成的多个多边形的子集的至少一个标识; （c）构造所述多个多边形的子集的图形和所述多个多边形中的任何中间多边形，其中所述多个多边形的所述子集由所述图形中的单个节点表示，所述图包括连接相邻的多边形的连接图中的多边形位于彼此的阈值距离内; 和（d）如果连接的任何子集形成奇数循环，则识别多图案化冲突。

4. 发明申请

US20130132913A1 RECOGNITION OF TEMPLATE PATTERNS WITH MASK INFORMATION 有权
标题翻译：用掩蔽信息识别模板图案
公开(公告)号：US20130132913A1
公开(公告)日：2013-05-23
申请号：US13303374
申请日：2011-11-23
申请人： Chung-Min FU , Yung-Fong LU , Wen-Ju YANG , Chin-Chang HSU
发明人： Chung-Min FU , Yung-Fong LU , Wen-Ju YANG , Chin-Chang HSU
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G03F1/70
摘要： Apparatus includes a machine readable storage medium for storing a template library having at least one template. The template is to include a first layout representation of at least one pattern to be formed by multi-patterning a single layer of an IC. The pattern has a plurality of portions to be formed using a plurality of respectively different photomasks. The first layout representation includes data identifying on which photomask each portion is to be located. An electronic design automation (EDA) tool includes a processor configured to receive a hardware description language representation of at least a part of a circuit and generate a second layout representation of the part of the circuit having a plurality of polygons. The EDA tool has a matching module that identifies and outputs an indication of whether one or more of the plurality of portions matches a subset of the plurality of polygons.
摘要翻译：装置包括用于存储具有至少一个模板的模板库的机器可读存储介质。该模板将包括通过多图案化IC的单层而形成的至少一个图案的第一布局图示。该图案具有使用多个分别不同的光掩模形成的多个部分。第一布局表示包括识别每个部分将要位于哪个光掩模上的数据。电子设计自动化（EDA）工具包括被配置为接收电路的至少一部分的硬件描述语言表示并且生成具有多个多边形的电路的一部分的第二布局表示的处理器。 EDA工具具有匹配模块，其识别并输出多个部分中的一个或多个部分是否匹配多个多边形的子集的指示。

5. 发明申请

US20110233594A1 LIGHT-EMITTING DIODE PACKAGE 有权
标题翻译：发光二极管封装
公开(公告)号：US20110233594A1
公开(公告)日：2011-09-29
申请号：US13154306
申请日：2011-06-06
申请人： Chin-Chang HSU , Wen-Lung SU
发明人： Chin-Chang HSU , Wen-Lung SU
IPC分类号： H01L33/52
CPC分类号： H01L33/60 , H01L25/167 , H01L2224/48095 , H01L2224/48247 , H01L2224/85385 , H01L2924/15724 , H01L2924/15747 , H01L2924/3025 , H01L2933/0091 , H01L2224/48091 , H01L2924/00014 , H01L2924/00
摘要： An LED package including a lead-frame, at least an LED chip and an encapsulant is provided. The lead-frame has a roughened surface, the LED chip is disposed on the lead-frame and electrically connected to the lead-frame, and the roughened surface is suitable to scatter the light emitted from the LED chip. In addition, the encapsulant encapsulates the LED chip and a part of the lead-frame, and the rest part of the lead-frame is exposed out of the encapsulant.
摘要翻译：提供了包括引线框架，至少LED芯片和密封剂的LED封装。引线框架具有粗糙表面，LED芯片设置在引线框架上并电连接到引线框架，并且粗糙表面适于散射从LED芯片发射的光。此外，密封剂封装LED芯片和引线框架的一部分，引线框架的其余部分从密封剂中露出。

6. 发明申请

US20120228659A1 LIGHT-EMITTING DIODE WITH METAL STRUCTURE AND HEAT SINK 有权
标题翻译：具有金属结构和散热的发光二极管
公开(公告)号：US20120228659A1
公开(公告)日：2012-09-13
申请号：US13415434
申请日：2012-03-08
申请人： Feng-Jung HSU , Chin-Chang HSU , Chun-Wei WANG , Jian-Chin LIANG
发明人： Feng-Jung HSU , Chin-Chang HSU , Chun-Wei WANG , Jian-Chin LIANG
IPC分类号： H01L33/60 , F21V7/20
CPC分类号： H01L33/642 , H01L33/60
摘要： A light-emitting diode has a metal structure, a light-emitting chip, and a bowl structure. The metal structure has a platform and a heat sink. The platform has a top face, a first side, and a second side opposite to the first side. A first reflector and a second reflector respectively extend from the first side and the second side. The heat sink extends below the top face and has a drop from the bottom surfaces of the first reflector and the second reflector. The light-emitting chip is disposed on the top face. The bowl structure covers the outer surface of the metal structure and shields the bottom surfaces of the first reflector and the second reflector. A thermal dispassion surface of the heat sink is exposed from the bowl structure. An inner surface of bowl wall has a plurality of reflection structures to promote the light extraction efficiency.
摘要翻译：发光二极管具有金属结构，发光芯片和碗结构。金属结构具有平台和散热器。平台具有顶面，第一侧和与第一侧相对的第二侧。第一反射器和第二反射器分别从第一侧和第二侧延伸。散热器在顶面下方延伸，并且具有从第一反射器和第二反射器的底表面的下降。发光芯片设置在顶面上。碗结构覆盖金属结构的外表面并且屏蔽第一反射器和第二反射器的底表面。散热器的热分散表面从碗结构暴露出来。碗壁的内表面具有多个反射结构，以提高光提取效率。

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