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1. 发明授权

US08222923B1 Method and apparatus for memory control with a programmable device 有权
标题翻译：用可编程器件进行存储器控制的方法和装置
公开(公告)号：US08222923B1
公开(公告)日：2012-07-17
申请号：US12694615
申请日：2010-01-27
申请人： Schuyler E. Shimanek , Wayne E. Wennekamp , Joe E. Leyba , Adam Elkins , Thomas H. Strader , Chidamber R. Kulkarni , Mikhail A. Wolf , Steven E. McNeil
发明人： Schuyler E. Shimanek , Wayne E. Wennekamp , Joe E. Leyba , Adam Elkins , Thomas H. Strader , Chidamber R. Kulkarni , Mikhail A. Wolf , Steven E. McNeil
IPC分类号： H03K19/177
CPC分类号： H03K19/1776 , H03K19/17736 , H03K19/1774
摘要： A technique is provided for memory control in a device having programmable circuitry, including providing a dedicated memory controller circuit in the device before the programmable circuitry is field programmed. Another technique involves fabricating a device, where the fabricating involves forming programmable circuitry that includes a dedicated memory controller circuit before the circuitry is field programmed.
摘要翻译：提供了一种用于具有可编程电路的器件中的存储器控制的技术，包括在可编程电路被现场编程之前在器件中提供专用存储器控制器电路。另一技术涉及制造一种器件，其中制造涉及在电路被现场编程之前形成包括专用存储器控制器电路的可编程电路。

2. 发明授权

US08134878B1 Signal calibration for memory interface 有权
标题翻译：存储器接口的信号校准
公开(公告)号：US08134878B1
公开(公告)日：2012-03-13
申请号：US12695099
申请日：2010-01-27
申请人： Schuyler E. Shimanek , Mikhail A. Wolf , Sanford L. Helton , John G. O'Dwyer
发明人： Schuyler E. Shimanek , Mikhail A. Wolf , Sanford L. Helton , John G. O'Dwyer
IPC分类号： G11C7/00
CPC分类号： H03K19/1776 , H03K19/17736 , H03K19/1774
摘要： A method of calibrating memory controller signals within an integrated circuit (IC) can include determining an internal delay of a clock network of the IC and generating a calibrated clock signal by applying a first delay to an uncalibrated clock signal, wherein the first delay is determined by subtracting the internal delay of the clock network of the IC from a bitperiod of the uncalibrated clock signal. The method can include determining a classification of at least one data signal according to timing of positive and negative edges of the at least one data signal in comparison with edges of the calibrated clock signal and aligning at least one of positive or negative edges of the at least one data signal to occur at midpoints between edges of the calibrated clock signal according to the classification of the at least one data signal.
摘要翻译：校准集成电路（IC）内的存储器控制器信号的方法可以包括：确定IC的时钟网络的内部延迟并通过向未校准的时钟信号施加第一延迟并产生校准时钟信号，其中确定第一延迟通过从未校准的时钟信号的比特周减去IC的时钟网络的内部延迟。该方法可以包括根据校准的时钟信号的边缘与至少一个数据信号的正边缘和负边缘的定时相对应地确定至少一个数据信号的分类，并且对准至少一个数据信号的正或负边缘至少一个数据信号根据至少一个数据信号的分类在校准时钟信号的边缘之间的中点发生。

3. 发明授权

US08742791B1 Method and apparatus for preamble detection for a control signal 有权
标题翻译：用于控制信号的前同步码检测的方法和装置
公开(公告)号：US08742791B1
公开(公告)日：2014-06-03
申请号：US12689585
申请日：2010-01-19
申请人： Schuyler E. Shimanek , Mikhail A. Wolf
发明人： Schuyler E. Shimanek , Mikhail A. Wolf
IPC分类号： H03K19/00 , G11C8/00
CPC分类号： H03K19/1776 , H03K19/17736 , H03K19/1774
摘要： An embodiment of a technique to determine an expected occurrence of a signal is disclosed. The technique includes receiving first and second signals, and storing delay information representing an expected time delay from an occurrence of the first signal to a point in time corresponding approximately to an expected occurrence of the second signal. The technique further includes responding to an occurrence of the first signal by: waiting for a time interval equivalent to the expected time delay, evaluating the second signal at approximately the end of the time interval, and adjusting the stored delay information if the second signal occurred outside a time window associated with the end of the time interval.
摘要翻译：公开了一种用于确定信号的预期发生的技术的实施例。该技术包括接收第一和第二信号，以及将表示预期时间延迟的延迟信息从第一信号的出现存储到大致相当于第二信号的期望出现的时间点。该技术还包括通过以下步骤来响应第一信号的发生：等待与预期时间延迟相当的时间间隔，在大约时间间隔结束时评估第二信号，以及如果发生第二信号则调整存储的延迟信息在与时间间隔结束相关联的时间窗外。

4. 发明授权

US08116162B1 Dynamic signal calibration for a high speed memory controller 有权
标题翻译：高速存储控制器的动态信号校准
公开(公告)号：US08116162B1
公开(公告)日：2012-02-14
申请号：US12693397
申请日：2010-01-25
申请人： Wayne E. Wennekamp , Schuyler E. Shimanek , Mikhail A. Wolf , Adam Elkins
发明人： Wayne E. Wennekamp , Schuyler E. Shimanek , Mikhail A. Wolf , Adam Elkins
IPC分类号： G11C7/00
CPC分类号： H03K19/1776 , H03K19/17736 , H03K19/1774
摘要： Within an integrated circuit comprising a memory controller, a method can include, responsive to determining that the memory controller is performing a refresh operation, calculating a new tap setting according to a new maximum value and an old tap setting of the delay circuit. The new maximum value specifies a number of taps of the delay circuit that approximates a predetermined time span. The method can include dynamically adjusting a delay applied to a signal by a delay circuit according to the new tap setting. The delay circuit generates a delayed signal that is provided to the memory controller.
摘要翻译：在包括存储器控制器的集成电路中，方法可以响应于确定存储器控制器正在执行刷新操作，根据延迟电路的新的最大值和旧抽头设置来计算新的抽头设置。新的最大值指定接近预定时间跨度的延迟电路的抽头数。该方法可以包括根据新的分接头设置动态地调整由延迟电路施加到信号上的延迟。延迟电路产生提供给存储器控制器的延迟信号。

5. 发明授权

US07188043B1 Boundary scan analysis 有权
标题翻译：边界扫描分析
公开(公告)号：US07188043B1
公开(公告)日：2007-03-06
申请号：US10769241
申请日：2004-01-30
申请人： Mikhail A. Wolf
发明人： Mikhail A. Wolf
IPC分类号： G01R31/14
CPC分类号： G01R31/318536 , G01R31/318378 , G01R31/318544
摘要： A circuit testing approach involves the generation of boundary scan information using test vectors to identify characteristics of a circuit design and a boundary scan implementation therefor. According to an example embodiment of the present invention, test vectors are used in simulation to identify circuit design characteristics for establishing a boundary scan test program. The test vectors are generated using a netlist of the circuit design. The test vectors are used to simulate operation of the circuit, and responses to the simulation are detected and used to identify design-specific circuit characteristics and a boundary scan test program is generated using the design-specific circuit characteristics.
摘要翻译：电路测试方法涉及使用测试向量生成边界扫描信息，以识别电路设计的特性和用于其的边界扫描实现。根据本发明的示例性实施例，在仿真中使用测试向量来识别用于建立边界扫描测试程序的电路设计特性。使用电路设计的网表生成测试向量。测试矢量用于模拟电路的运行，并检测对仿真的响应，并用于识别设计特定的电路特性，并使用设计特定的电路特性生成边界扫描测试程序。

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