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1. 发明授权

US08201037B2 Semiconductor integrated circuit and method for controlling semiconductor integrated circuit 失效
标题翻译：半导体集成电路及半导体集成电路控制方法
公开(公告)号：US08201037B2
公开(公告)日：2012-06-12
申请号：US12563515
申请日：2009-09-21
申请人： Kenichi Anzou , Chikako Tokunaga
发明人： Kenichi Anzou , Chikako Tokunaga
IPC分类号： G01R31/28 , G06F11/00
CPC分类号： G06F11/27 , G11C29/14 , G11C29/38 , G11C29/44 , G11C29/4401 , G11C29/72 , G11C2029/0401 , G11C2029/1208 , G11C2029/3602
摘要： A semiconductor integrated circuit includes memories, a BIST circuit, and an analyzer. The BIST circuit includes a test controller performing the test and generating a memory selection signal selecting a memory to be tested, an address generator generating write and read addresses, a data generator generating write data and an expected output value, and a control signal generator generating a control signal. The analyzer includes a memory output selector selecting output data, a bit comparator comparing the output data with the expected output value, an error detection unit determining whether there is an error in the memory, a plurality of pass/fail flag registers capable of storing a pass/fail flag, a repair analyzer analyzing a memory error and generating a repair analysis result, a plurality of repair analysis result registers capable of storing the repair analysis result, and an output unit outputting the pass/fail flag and the repair analysis result.
摘要翻译：半导体集成电路包括存储器，BIST电路和分析器。 BIST电路包括执行测试并产生选择要测试的存储器的存储器选择信号的测试控制器，产生写入和读取地址的地址生成器，产生写入数据和预期输出值的数据发生器以及产生一个控制信号。分析器包括选择输出数据的存储器输出选择器，将输出数据与预期输出值进行比较的位比较器，确定存储器中是否存在错误的错误检测单元，能够存储通过/失败标志，分析存储器错误并产生修复分析结果的修复分析器，能够存储修复分析结果的多个修复分析结果寄存器，以及输出通过/失败标志和修复分析结果的输出单元。

2. 发明授权

US08037376B2 On-chip failure analysis circuit and on-chip failure analysis method 有权
标题翻译：片上故障分析电路和片上故障分析方法
公开(公告)号：US08037376B2
公开(公告)日：2011-10-11
申请号：US12345298
申请日：2008-12-29
申请人： Kenichi Anzou , Chikako Tokunaga
发明人： Kenichi Anzou , Chikako Tokunaga
IPC分类号： G11C29/00
CPC分类号： G11C29/44 , G11C29/4401 , G11C29/72
摘要： An on-chip failure analysis circuit for analyzing a memory has a memory in which data is stored, a built-in self test unit which tests the memory, a failure detection unit which detects a failure of the output of the memory, a fail data storage unit in which fail data is stored, the fail data including a location of the failure, a failure analysis unit which performs failure analysis using the number of failures detected by the failure detection unit and the location of the failure, the failure analysis unit writing fail data including the analysis result in the fail data storage unit, and an analysis result output unit which outputs the analysis result of the failure analysis unit.
摘要翻译：用于分析存储器的片上故障分析电路具有存储数据的存储器，测试存储器的内置自检单元，检测存储器输出故障的故障检测单元，故障数据存储故障数据的存储单元，包括故障位置的故障数据，使用故障检测单元检测到的故障次数和故障位置进行故障分析的故障分析单元，故障分析单元写入包括故障数据存储单元中的分析结果的故障数据以及输出故障分析单元的分析结果的分析结果输出单元。

3. 发明授权

US07734975B2 Semiconductor integrated circuit having built-n self test circuit of logic circuit and embedded device, and design apparatus thereof 失效
标题翻译：具有逻辑电路和嵌入式装置的内置自检电路的半导体集成电路及其设计装置
公开(公告)号：US07734975B2
公开(公告)日：2010-06-08
申请号：US11683759
申请日：2007-03-08
申请人： Kenichi Anzou , Chikako Tokunaga , Tetsu Hasegawa
发明人： Kenichi Anzou , Chikako Tokunaga , Tetsu Hasegawa
IPC分类号： G01R31/28
CPC分类号： G01R31/31721 , G01R31/318575
摘要： A semiconductor integrated circuit contains a logic circuit which operates upon receiving a clock; a logic built-in self test circuit which executes a built-in self test of said logic circuit, said logic built-in self test circuit having a pattern generator which generates a pattern to be input to said logic circuit, a pattern compactor which receives data output from said logic circuit that has received the pattern, compacts the data, and outputs a result, and a logic built-in self test control unit which controls operations of said pattern generator and said pattern compactor and controls an operation of causing a scan path in said logic circuit to shift upon receiving the pattern; a device circuit which operates upon receiving the clock; and a device circuit built-in self test circuit which executes a built-in self test of said device circuit.
摘要翻译：半导体集成电路包含在接收时钟时工作的逻辑电路; 逻辑内置自检电路，其执行所述逻辑电路的内置自检，所述逻辑内置自检电路具有产生要输入到所述逻辑电路的模式的模式发生器，模式压缩器，其接收从已经接收到图案的所述逻辑电路输出的数据，压缩数据并输出结果;以及逻辑内置自检控制单元，其控制所述图案发生器和所述图案压实机的操作，并控制进行扫描的操作所述逻辑电路中的路径在接收到所述图案时移位; 接收时钟时操作的设备电路; 以及内置自检电路的器件电路，其执行所述器件电路的内置自检。

4. 发明授权

US07653854B2 Semiconductor integrated circuit having a (BIST) built-in self test circuit for fault diagnosing operation of a memory 有权
标题翻译：具有用于存储器的故障诊断操作的（BIST）内置自检电路的半导体集成电路
公开(公告)号：US07653854B2
公开(公告)日：2010-01-26
申请号：US11774075
申请日：2007-07-06
申请人： Kenichi Anzou , Chikako Tokunaga
发明人： Kenichi Anzou , Chikako Tokunaga
IPC分类号： G01R31/28
CPC分类号： G11C29/16 , G11C29/38 , G11C29/44 , G11C2029/0405 , G11C2029/2602 , G11C2029/3602
摘要： According to the present invention, there is provided a semiconductor integrated circuit having: a BIST including a data generator, an address generator, a control signal generator, a result analyzer, a BIST controller, and a diagnostic data storage circuit including a first capture register which captures and outputs, in accordance with a first clock, a latest address signal and the BIST state signal output from said BIST controller while the flag signal is in as state that no fault is detected, and maintains outputs when the flag signal is in a state that a fault is detected. The semiconductor integrated circuit can further include a memory collar having a memory cell, a second capture register, a comparator, and a flag register. The semiconductor integrated circuit can perform a fault diagnosing operation of a memory by using a comparator type BIST circuit.
摘要翻译：根据本发明，提供了一种半导体集成电路，其具有：包括数据发生器，地址发生器，控制信号发生器，结果分析器，BIST控制器和包括第一捕获寄存器的诊断数据存储电路的BIST 其在标志信号处于作为没有检测到故障的状态时，根据第一时钟捕获并输出最新地址信号和从所述BIST控制器输出的BIST状态信号，并且当标志信号处于表示检测到故障。半导体集成电路还可以包括具有存储单元，第二捕获寄存器，比较器和标志寄存器的存储器环。半导体集成电路可以通过使用比较器型BIST电路来执行存储器的故障诊断操作。

5. 发明申请

US20090245000A1 SEMICONDUCTOR INTEGRATED CIRCUIT 有权
标题翻译：半导体集成电路
公开(公告)号：US20090245000A1
公开(公告)日：2009-10-01
申请号：US12404178
申请日：2009-03-13
申请人： Kenichi Anzou , Chikako Tokunaga
发明人： Kenichi Anzou , Chikako Tokunaga
IPC分类号： G11C29/00
CPC分类号： G11C29/02 , G11C29/025 , G11C29/44 , G11C2029/3602
摘要： A one-hot data generating unit generates one-hot data for the maximum data bit width in which a state of one bit is exclusively inverted with respect to states of other bits while sequentially shifting a bit position to be inverted, and writes the one-hot data in an area of a memory designated by an address. A short defect between wirings connected to the memory is detected by comparing the one-hot data written in the memory with the one-hot data before being written.
摘要翻译：一热数据生成单元生成针对其中一位的状态相对于其他位的状态而被排他性反转的最大数据位宽度的一热数据，同时依次移位要反转的位位置，由地址指定的存储区域中的热数据。通过在写入存储器中写入的单热数据与单热数据进行比较来检测连接到存储器的布线之间的短路缺陷。

6. 发明授权

US08599632B2 Semiconductor integrated circuit 失效
标题翻译：半导体集成电路
公开(公告)号：US08599632B2
公开(公告)日：2013-12-03
申请号：US13411303
申请日：2012-03-02
申请人： Kenichi Anzou , Chikako Tokunaga
发明人： Kenichi Anzou , Chikako Tokunaga
IPC分类号： G11C7/00
CPC分类号： G11C29/26 , G11C29/18 , G11C29/44 , G11C2029/0405 , G11C2029/2602 , G11C2029/3602
摘要： The built-in self-test (BIST) circuit includes an address generating circuit. The BIST circuit includes a data generating circuit. The BIST circuit includes a chip enable signal generating circuit. The BIST circuit includes a control signal generating circuit. The memory block circuit includes the multiple memories. The memory block circuit includes an address converting circuit that generates, based on the address signal, an address input signal corresponding to the address of the memory to be tested out of the multiple memories, and generates a memory selection signal for selecting the memory to be tested from the multiple memories. The memory block circuit includes a memory output selecting circuit that selects and outputs data from the memory to be tested out of the multiple memories, based on the memory selection signal.
摘要翻译：内置的自检（BIST）电路包括地址发生电路。 BIST电路包括数据产生电路。 BIST电路包括芯片使能信号发生电路。 BIST电路包括控制信号发生电路。存储器块电路包括多个存储器。存储器块电路包括一个地址转换电路，该地址转换电路基于该地址信号产生一个地址输入信号，该地址输入信号与该多个存储器中要被测试的存储器的地址对应，并产生用于选择该存储器的存储器选择信号从多个记忆测试。存储器块电路包括存储器输出选择电路，其基于存储器选择信号从多个存储器中的待测试存储器中选择和输出数据。

7. 发明授权

US07962821B2 Built-in self testing circuit with fault diagnostic capability 有权
标题翻译：内置具有故障诊断功能的自检电路
公开(公告)号：US07962821B2
公开(公告)日：2011-06-14
申请号：US12199181
申请日：2008-08-27
申请人： Chikako Tokunaga , Kenichi Anzou
发明人： Chikako Tokunaga , Kenichi Anzou
IPC分类号： G01R31/28
CPC分类号： G11C29/44
摘要： A semiconductor integrated circuit includes: a memory collars including: a memory cell; a fetch register that is configured to fetch data as a first fetch data; a comparing unit that is configured to compare the first fetch data with an expected value; a failure detecting signal output unit that is configured to receive the compared result and output a failure detecting signal; and a BIST circuit including: a BIST control unit that is configured to output an instruction and output a BIST status; a shift controller that is configured to receive a first clock signal, the BIST status signal, and the failure detecting signal and output sift enable signal; a shift counter that counts the number of clock pulses on the first clock signal; a first storage register that is configured to receive the first clock signal and the shift enable signal, and a second storage register that is configured to receive a second clock signal.
摘要翻译：一种半导体集成电路包括：存储器环，包括：存储单元; 被配置为将数据作为第一取出数据提取的取出寄存器; 比较单元，被配置为将所述第一取出数据与期望值进行比较; 故障检测信号输出单元，被配置为接收所述比较结果并输出故障检测信号; 以及BIST电路，包括：BIST控制单元，被配置为输出指令并输出BIST状态; 移位控制器，被配置为接收第一时钟信号，BIST状态信号，以及故障检测信号和输出筛选使能信号; 移位计数器，对第一时钟信号上的时钟脉冲数进行计数; 被配置为接收第一时钟信号和移位使能信号的第一存储寄存器，以及被配置为接收第二时钟信号的第二存储寄存器。

8. 发明申请

US20110058434A1 SEMICONDUCTOR INTEGRATED CIRCUIT 有权
标题翻译：半导体集成电路
公开(公告)号：US20110058434A1
公开(公告)日：2011-03-10
申请号：US12726531
申请日：2010-03-18
申请人： Kenichi Anzou , Chikako Tokunaga
发明人： Kenichi Anzou , Chikako Tokunaga
IPC分类号： G11C29/00
CPC分类号： G11C29/785
摘要： A semiconductor integrated circuit has a plurality of memory devices each comprising a memory cell array which includes a plurality of memory cells to store data, a spare part which includes a redundant cell to avoid a memory cell judged to be defective in the plurality of memory cells and conduct redundancy repair on data, and a switching circuit to avoid the defective memory cell and conduct switching to the redundant cell; and a repair code decoding circuit comprising a storage circuit which stores a repair code, a decoder which outputs a repair decoded signal obtained by decoding the repair code, wherein the switching circuit respectively in the memory devices avoids a memory cell corresponding to the repair decoded signal and conducts switching to the redundant cell of the memory devices in accordance with the repair decoded signal.
摘要翻译：半导体集成电路具有多个存储器件，每个存储器件包括存储单元阵列，该存储器单元阵列包括多个用于存储数据的存储器单元，备用部件包括冗余单元，以避免在多个存储器单元中判断为有缺陷的存储器单元并对数据进行冗余修复，以及切换电路，以避免缺陷存储单元并切换到冗余单元; 以及修复码解码电路，其包括存储修复码的存储电路，输出通过解码修复码而获得的修复解码信号的解码器，其中分别在存储器件中的切换电路避免与修复解码信号相对应的存储单元并且根据修复解码信号进行存储器件的冗余单元的切换。

9. 发明申请

US20100251043A1 SEMICONDUCTOR INTEGRATED CIRCUIT, CIRCUIT FUNCTION VERYFICATION DEVICE AND METHOD OF VERYFYING CIRCUIT FUNCTION 审中-公开
标题翻译：半导体集成电路，电路功能特性装置及其电路功能的方法
公开(公告)号：US20100251043A1
公开(公告)日：2010-09-30
申请号：US12721768
申请日：2010-03-11
申请人： Kenichi Anzou , Chikako Tokunaga
发明人： Kenichi Anzou , Chikako Tokunaga
IPC分类号： G11C29/04 , G06F11/22
CPC分类号： G11C29/02 , G11C29/028 , G11C29/12 , G11C29/1201 , G11C29/44 , G11C29/4401 , G11C29/50012 , G11C29/70 , G11C29/88
摘要： A semiconductor integrated circuit has a data generation circuit configured to generate first data used for function verification of a built-in self test circuit and a built-in redundancy allocation circuit of a memory, a failure data generation circuit configured to generate second data for conducting a built in self test by inverting at least one bit of the first data based on a failure injection indication signal, and a timing circuit configured to adjust timing of at least one of the first and the second data in order to use one of the first and the second data as writing data to the memory and to use the other as an output expected value compared with data read out from the memory.
摘要翻译：半导体集成电路具有数据生成电路，被配置为生成用于内置自检电路的功能验证的第一数据和存储器的内置冗余分配电路，故障数据生成电路被配置为生成用于导通的第二数据基于故障注入指示信号反转第一数据的至少一位的内置自检;以及定时电路，被配置为调整第一和第二数据中的至少一个的定时，以便使用第一和第二数据之一并且将第二数据作为将数据写入存储器，并将另一个作为输出预期值与从存储器读出的数据相比较。

10. 发明申请

US20080022176A1 SEMICONDUCTOR INTEGRATED CIRCUIT 有权
公开(公告)号：US20080022176A1
公开(公告)日：2008-01-24
申请号：US11774075
申请日：2007-07-06
申请人： Kenichi Anzou , Chikako Tokunaga
发明人： Kenichi Anzou , Chikako Tokunaga
IPC分类号： G01R31/28
CPC分类号： G11C29/16 , G11C29/38 , G11C29/44 , G11C2029/0405 , G11C2029/2602 , G11C2029/3602
摘要： According to the present invention, there is provided a semiconductor integrated circuit having: a BIST circuit including, a data generator which generates and outputs write data to be supplied to a memory, an address generator which generates and outputs an address signal to be supplied to the memory, a control signal generator which generates and outputs a control signal for controlling the memory, a result analyzer which receives a flag signal, analyzes a result of a BIST, and outputs a BIST result signal, a BIST controller which controls operations of the data generator, the address generator, the control signal generator, and the result analyzer, and outputs a BIST state signal indicating a state of the BIST, and a diagnostic data storage circuit including a first capture register which captures and outputs, in accordance with a first clock, a latest address signal and the BIST state signal output from the BIST controller while no flag signal is supplied, and maintains outputs when the flag signal is supplied, a storage register which receive and stores the outputs from the first capture register in accordance with a second clock lower in speed than the first clock while no shift enable signal is supplied, thereby storing the address signal and the BIST signal corresponding to the supply timing of the flag signal, and outputs the stored contents outside by shifting them when the shift enable signal is supplied, and flag suppressing means for comparing the outputs from the first capture register with the stored contents of the storage register, and outputting a flag suppression signal, after the flag signal is supplied, until the latest address signal and the BIST state signal output from the first capture register match the address signal and the BIST control signal stored in the storage register; and a memory collar including, a memory cell which performs a write operation by receiving the write data, the address signal, and the control signal, and reads out and outputs the written data, in accordance with the first clock, a second capture register which captures latest data output from the memory cell while neither the shift enable signal nor the flag signal is supplied, maintains held contents when the flag signal is supplied, and outputs held contents outside by shifting the held contents when the shift enable signal is supplied, a comparator which compares the output from the second capture register with an expected value, and outputs a comparison result signal meaning failure detection if the output and the expected value do not match, and a flag register which outputs the flag signal on the basis of the comparison result signal while no flag suppression signal is supplied, and suppresses the output of the flag signal when the flag suppression signal is supplied

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