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1. 发明授权

US08201037B2 Semiconductor integrated circuit and method for controlling semiconductor integrated circuit 失效
标题翻译：半导体集成电路及半导体集成电路控制方法
公开(公告)号：US08201037B2
公开(公告)日：2012-06-12
申请号：US12563515
申请日：2009-09-21
申请人： Kenichi Anzou , Chikako Tokunaga
发明人： Kenichi Anzou , Chikako Tokunaga
IPC分类号： G01R31/28 , G06F11/00
CPC分类号： G06F11/27 , G11C29/14 , G11C29/38 , G11C29/44 , G11C29/4401 , G11C29/72 , G11C2029/0401 , G11C2029/1208 , G11C2029/3602
摘要： A semiconductor integrated circuit includes memories, a BIST circuit, and an analyzer. The BIST circuit includes a test controller performing the test and generating a memory selection signal selecting a memory to be tested, an address generator generating write and read addresses, a data generator generating write data and an expected output value, and a control signal generator generating a control signal. The analyzer includes a memory output selector selecting output data, a bit comparator comparing the output data with the expected output value, an error detection unit determining whether there is an error in the memory, a plurality of pass/fail flag registers capable of storing a pass/fail flag, a repair analyzer analyzing a memory error and generating a repair analysis result, a plurality of repair analysis result registers capable of storing the repair analysis result, and an output unit outputting the pass/fail flag and the repair analysis result.
摘要翻译：半导体集成电路包括存储器，BIST电路和分析器。 BIST电路包括执行测试并产生选择要测试的存储器的存储器选择信号的测试控制器，产生写入和读取地址的地址生成器，产生写入数据和预期输出值的数据发生器以及产生一个控制信号。分析器包括选择输出数据的存储器输出选择器，将输出数据与预期输出值进行比较的位比较器，确定存储器中是否存在错误的错误检测单元，能够存储通过/失败标志，分析存储器错误并产生修复分析结果的修复分析器，能够存储修复分析结果的多个修复分析结果寄存器，以及输出通过/失败标志和修复分析结果的输出单元。

2. 发明授权

US08037376B2 On-chip failure analysis circuit and on-chip failure analysis method 有权
标题翻译：片上故障分析电路和片上故障分析方法
公开(公告)号：US08037376B2
公开(公告)日：2011-10-11
申请号：US12345298
申请日：2008-12-29
申请人： Kenichi Anzou , Chikako Tokunaga
发明人： Kenichi Anzou , Chikako Tokunaga
IPC分类号： G11C29/00
CPC分类号： G11C29/44 , G11C29/4401 , G11C29/72
摘要： An on-chip failure analysis circuit for analyzing a memory has a memory in which data is stored, a built-in self test unit which tests the memory, a failure detection unit which detects a failure of the output of the memory, a fail data storage unit in which fail data is stored, the fail data including a location of the failure, a failure analysis unit which performs failure analysis using the number of failures detected by the failure detection unit and the location of the failure, the failure analysis unit writing fail data including the analysis result in the fail data storage unit, and an analysis result output unit which outputs the analysis result of the failure analysis unit.
摘要翻译：用于分析存储器的片上故障分析电路具有存储数据的存储器，测试存储器的内置自检单元，检测存储器输出故障的故障检测单元，故障数据存储故障数据的存储单元，包括故障位置的故障数据，使用故障检测单元检测到的故障次数和故障位置进行故障分析的故障分析单元，故障分析单元写入包括故障数据存储单元中的分析结果的故障数据以及输出故障分析单元的分析结果的分析结果输出单元。

3. 发明授权

US07734975B2 Semiconductor integrated circuit having built-n self test circuit of logic circuit and embedded device, and design apparatus thereof 失效
标题翻译：具有逻辑电路和嵌入式装置的内置自检电路的半导体集成电路及其设计装置
公开(公告)号：US07734975B2
公开(公告)日：2010-06-08
申请号：US11683759
申请日：2007-03-08
申请人： Kenichi Anzou , Chikako Tokunaga , Tetsu Hasegawa
发明人： Kenichi Anzou , Chikako Tokunaga , Tetsu Hasegawa
IPC分类号： G01R31/28
CPC分类号： G01R31/31721 , G01R31/318575
摘要： A semiconductor integrated circuit contains a logic circuit which operates upon receiving a clock; a logic built-in self test circuit which executes a built-in self test of said logic circuit, said logic built-in self test circuit having a pattern generator which generates a pattern to be input to said logic circuit, a pattern compactor which receives data output from said logic circuit that has received the pattern, compacts the data, and outputs a result, and a logic built-in self test control unit which controls operations of said pattern generator and said pattern compactor and controls an operation of causing a scan path in said logic circuit to shift upon receiving the pattern; a device circuit which operates upon receiving the clock; and a device circuit built-in self test circuit which executes a built-in self test of said device circuit.
摘要翻译：半导体集成电路包含在接收时钟时工作的逻辑电路; 逻辑内置自检电路，其执行所述逻辑电路的内置自检，所述逻辑内置自检电路具有产生要输入到所述逻辑电路的模式的模式发生器，模式压缩器，其接收从已经接收到图案的所述逻辑电路输出的数据，压缩数据并输出结果;以及逻辑内置自检控制单元，其控制所述图案发生器和所述图案压实机的操作，并控制进行扫描的操作所述逻辑电路中的路径在接收到所述图案时移位; 接收时钟时操作的设备电路; 以及内置自检电路的器件电路，其执行所述器件电路的内置自检。

4. 发明授权

US07653854B2 Semiconductor integrated circuit having a (BIST) built-in self test circuit for fault diagnosing operation of a memory 有权
标题翻译：具有用于存储器的故障诊断操作的（BIST）内置自检电路的半导体集成电路
公开(公告)号：US07653854B2
公开(公告)日：2010-01-26
申请号：US11774075
申请日：2007-07-06
申请人： Kenichi Anzou , Chikako Tokunaga
发明人： Kenichi Anzou , Chikako Tokunaga
IPC分类号： G01R31/28
CPC分类号： G11C29/16 , G11C29/38 , G11C29/44 , G11C2029/0405 , G11C2029/2602 , G11C2029/3602
摘要： According to the present invention, there is provided a semiconductor integrated circuit having: a BIST including a data generator, an address generator, a control signal generator, a result analyzer, a BIST controller, and a diagnostic data storage circuit including a first capture register which captures and outputs, in accordance with a first clock, a latest address signal and the BIST state signal output from said BIST controller while the flag signal is in as state that no fault is detected, and maintains outputs when the flag signal is in a state that a fault is detected. The semiconductor integrated circuit can further include a memory collar having a memory cell, a second capture register, a comparator, and a flag register. The semiconductor integrated circuit can perform a fault diagnosing operation of a memory by using a comparator type BIST circuit.
摘要翻译：根据本发明，提供了一种半导体集成电路，其具有：包括数据发生器，地址发生器，控制信号发生器，结果分析器，BIST控制器和包括第一捕获寄存器的诊断数据存储电路的BIST 其在标志信号处于作为没有检测到故障的状态时，根据第一时钟捕获并输出最新地址信号和从所述BIST控制器输出的BIST状态信号，并且当标志信号处于表示检测到故障。半导体集成电路还可以包括具有存储单元，第二捕获寄存器，比较器和标志寄存器的存储器环。半导体集成电路可以通过使用比较器型BIST电路来执行存储器的故障诊断操作。

5. 发明申请

US20090245000A1 SEMICONDUCTOR INTEGRATED CIRCUIT 有权
标题翻译：半导体集成电路
公开(公告)号：US20090245000A1
公开(公告)日：2009-10-01
申请号：US12404178
申请日：2009-03-13
申请人： Kenichi Anzou , Chikako Tokunaga
发明人： Kenichi Anzou , Chikako Tokunaga
IPC分类号： G11C29/00
CPC分类号： G11C29/02 , G11C29/025 , G11C29/44 , G11C2029/3602
摘要： A one-hot data generating unit generates one-hot data for the maximum data bit width in which a state of one bit is exclusively inverted with respect to states of other bits while sequentially shifting a bit position to be inverted, and writes the one-hot data in an area of a memory designated by an address. A short defect between wirings connected to the memory is detected by comparing the one-hot data written in the memory with the one-hot data before being written.
摘要翻译：一热数据生成单元生成针对其中一位的状态相对于其他位的状态而被排他性反转的最大数据位宽度的一热数据，同时依次移位要反转的位位置，由地址指定的存储区域中的热数据。通过在写入存储器中写入的单热数据与单热数据进行比较来检测连接到存储器的布线之间的短路缺陷。

6. 发明授权

US08671317B2 Built-in self test circuit and designing apparatus 有权
标题翻译：内置自检电路及设计仪器
公开(公告)号：US08671317B2
公开(公告)日：2014-03-11
申请号：US13231073
申请日：2011-09-13
申请人： Kenichi Anzou , Chikako Tokunaga
发明人： Kenichi Anzou , Chikako Tokunaga
IPC分类号： G11C29/00
CPC分类号： G11C29/18 , G11C29/10 , G11C2029/0405 , G11C2029/3602
摘要： According to one embodiment, a semiconductor integrated circuit includes at least one memory and at least one built-in self test (BIST) circuit. In the memory, data can be stored. The BIST circuit tests the memory and includes an address generator. The address generator operates in one of a first operating mode and a second operating mode. In the first operating mode, address signals corresponding to all addresses of the memory are generated. In the second operating mode, the address signals are generated such that each bit of an address input of the memory can be one signal state of both 0 and 1 and such that different bits constitute a set of pieces of data in which the bits choose different signal states at least once.
摘要翻译：根据一个实施例，半导体集成电路包括至少一个存储器和至少一个内置自测试（BIST）电路。在内存中，可以存储数据。 BIST电路测试存储器并包括地址发生器。地址发生器以第一操作模式和第二操作模式中的一种操作。在第一操作模式中，生成与存储器的所有地址对应的地址信号。在第二操作模式中，产生地址信号，使得存储器输入的地址的每个位都可以是0和1的一个信号状态，并且使得不同的位构成一组数据，其中位选择不同信号状态至少一次。

7. 发明授权

US08032803B2 Semiconductor integrated circuit and test system thereof 有权
标题翻译：半导体集成电路及其测试系统
公开(公告)号：US08032803B2
公开(公告)日：2011-10-04
申请号：US12164518
申请日：2008-06-30
申请人： Kenichi Anzou , Chikako Tokunaga
发明人： Kenichi Anzou , Chikako Tokunaga
IPC分类号： G11C29/00 , G06F11/00
CPC分类号： G11C29/44 , G11C29/16 , G11C2029/0405 , G11C2029/3602
摘要： A semiconductor integrated circuit has a memory collar including a memory cell configured to store a written data pattern and read and output the data pattern, and a register configured to store a failed data pattern, and a built-in self test circuit configured to write the data pattern in the memory cell, output expected value data, and decide whether to continue a test or suspend the test to output failure information to outside, based on a comparison result of the data pattern outputted from the memory cell and the expected value data and a comparison result of the data pattern and the failed data pattern.
摘要翻译：一种半导体集成电路具有包括存储单元的存储器环，存储单元被配置为存储写入的数据模式并读取和输出数据模式，以及配置为存储故障数据模式的寄存器，以及内置的自测电路，存储单元中的数据模式，输出期望值数据，并且基于从存储器单元输出的数据模式和期望值数据的比较结果，决定是继续测试还是暂停测试以将失败信息输出到外部，以及数据模式和失败的数据模式的比较结果。

8. 发明申请

US20100125766A1 SEMICONDUCTOR INTEGRATED CIRCUIT AND METHOD FOR CONTROLLING SEMICONDUCTOR INTEGRATED CIRCUIT 失效
标题翻译：半导体集成电路和控制半导体集成电路的方法
公开(公告)号：US20100125766A1
公开(公告)日：2010-05-20
申请号：US12563515
申请日：2009-09-21
申请人： Kenichi Anzou , Chikako Tokunaga
发明人： Kenichi Anzou , Chikako Tokunaga
IPC分类号： G11C29/04 , G06F11/22
CPC分类号： G06F11/27 , G11C29/14 , G11C29/38 , G11C29/44 , G11C29/4401 , G11C29/72 , G11C2029/0401 , G11C2029/1208 , G11C2029/3602
摘要： A semiconductor integrated circuit includes memories, a BIST circuit, and an analyzer. The BIST circuit includes a test controller performing the test and generating a memory selection signal selecting a memory to be tested, an address generator generating write and read addresses, a data generator generating write data and an expected output value, and a control signal generator generating a control signal. The analyzer includes a memory output selector selecting output data, a bit comparator comparing the output data with the expected output value, an error detection unit determining whether there is an error in the memory, a plurality of pass/fail flag registers capable of storing a pass/fail flag, a repair analyzer analyzing a memory error and generating a repair analysis result, a plurality of repair analysis result registers capable of storing the repair analysis result, and an output unit outputting the pass/fail flag and the repair analysis result.
摘要翻译：半导体集成电路包括存储器，BIST电路和分析器。 BIST电路包括执行测试并产生选择要测试的存储器的存储器选择信号的测试控制器，产生写入和读取地址的地址生成器，产生写入数据和预期输出值的数据发生器以及产生一个控制信号。分析器包括选择输出数据的存储器输出选择器，将输出数据与预期输出值进行比较的位比较器，确定存储器中是否存在错误的错误检测单元，能够存储通过/失败标志，分析存储器错误并产生修复分析结果的修复分析器，能够存储修复分析结果的多个修复分析结果寄存器，以及输出通过/失败标志和修复分析结果的输出单元。

9. 发明授权

US07120890B2 Apparatus for delay fault testing of integrated circuits 失效
标题翻译：集成电路延迟故障测试装置
公开(公告)号：US07120890B2
公开(公告)日：2006-10-10
申请号：US10695698
申请日：2003-10-28
申请人： Koji Urata , Kenichi Anzou , Tetsu Hasegawa , Chikako Tokunaga
发明人： Koji Urata , Kenichi Anzou , Tetsu Hasegawa , Chikako Tokunaga
IPC分类号： G06F17/50
CPC分类号： G01R31/31919 , G01R31/31813 , G01R31/31917
摘要： A method for generating a test vector of an IC including: designating a retrieval condition to select a path on which a signal can be transmitted in the circuit; executing a timing analysis of the circuit based on a circuit information of the circuit, retrieving the path satisfying the retrieval condition, and generating a path list in which cells composing the retrieved path are put in order of executing the timing analysis; generating a test vector to test a path delay fault of the circuit based on the path list; designating an ending condition to end generation of the test vector when the path in the path list for the test vector is distributed over the circuit; and stopping generation of the path list when the ending condition is satisfied.
摘要翻译：一种用于生成IC测试向量的方法，包括：指定检索条件以选择可在其中发送信号的路径; 根据电路的电路信息执行电路的定时分析，检索满足检索条件的路径，生成构成检索路径的单元的路径列表，按顺序进行定时分析; 生成测试向量，以基于路径列表测试电路的路径延迟故障; 当测试向量的路径列表中的路径分布在电路上时，指定结束条件以终止生成测试向量; 并且当满足结束条件时停止生成路径列表。

10. 发明申请

US20050015693A1 Semiconductor integrated circuit verification system 失效
标题翻译：半导体集成电路验证系统
公开(公告)号：US20050015693A1
公开(公告)日：2005-01-20
申请号：US10884251
申请日：2004-07-01
申请人： Kenichi Anzou , Chikako Tokunaga , Takashi Matsumoto
发明人： Kenichi Anzou , Chikako Tokunaga , Takashi Matsumoto
IPC分类号： G01R31/28 , G06F11/00 , G06F17/50 , G11C29/54
CPC分类号： G11C29/54 , G06F17/5022
摘要： An aspect of the present invention provides a semiconductor integrated circuit verification system that includes a compiler configured to receive circuit descriptions of a semiconductor integrated circuit to be verified and create a circuit database, a circuit analysis unit configured to receive the circuit database to analyze the circuitry inside the semiconductor integrated circuit based on the circuit database, the circuit analysis unit configured to determine the timing at which the abstraction level of the circuit is switched and generate a simulation object, and a simulation execution unit configured to receive the simulation object and conduct a simulation of the semiconductor integrated circuit based on the simulation object.
摘要翻译：本发明的一个方面提供了一种半导体集成电路验证系统，其包括被配置为接收要验证的半导体集成电路的电路描述并创建电路数据库的编译器，被配置为接收电路数据库以分析电路的电路分析单元在基于电路数据库的半导体集成电路内部，电路分析单元被配置为确定电路的抽象电平被切换并产生仿真对象的定时，以及模拟执行单元，被配置为接收模拟对象并进行基于模拟对象的半导体集成电路仿真。

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