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1. 发明授权

US07797591B2 Semiconductor integrated circuit, design support software system, and automatic test pattern generation system 有权
标题翻译：半导体集成电路，设计支持软件系统和自动测试图案生成系统
公开(公告)号：US07797591B2
公开(公告)日：2010-09-14
申请号：US12503336
申请日：2009-07-15
申请人： Tetsu Hasegawa , Chikako Tokunaga
发明人： Tetsu Hasegawa , Chikako Tokunaga
IPC分类号： G11C29/00
CPC分类号： G11C29/54 , G11C2029/0405 , G11C2029/3602
摘要： A semiconductor integrated circuit has a memory circuit having memory cells, a first register, a second register, a register selection circuit having an input to which an output of the first register and an output of the second register are connected, a memory bypass circuit which is located between a first switching circuit and a second switching circuit, and connected to the inputs and the outputs of the memory circuit. The register selection circuit is switched to the output signals of the first register when performing testing by way of the memory circuit, and switched to output signals of the second register when performing testing by way of the memory bypass circuit.
摘要翻译：一种半导体集成电路具有存储单元的存储电路，第一寄存器，第二寄存器，具有第一寄存器的输出和第二寄存器的输出的输入的寄存器选择电路，存储器旁路电路，位于第一开关电路和第二开关电路之间，并连接到存储器电路的输入端和输出端。当通过存储器电路进行测试时，寄存器选择电路切换到第一寄存器的输出信号，并且当通过存储器旁路电路进行测试时，将其切换到第二寄存器的输出信号。

2. 发明授权

US07734975B2 Semiconductor integrated circuit having built-n self test circuit of logic circuit and embedded device, and design apparatus thereof 失效
标题翻译：具有逻辑电路和嵌入式装置的内置自检电路的半导体集成电路及其设计装置
公开(公告)号：US07734975B2
公开(公告)日：2010-06-08
申请号：US11683759
申请日：2007-03-08
申请人： Kenichi Anzou , Chikako Tokunaga , Tetsu Hasegawa
发明人： Kenichi Anzou , Chikako Tokunaga , Tetsu Hasegawa
IPC分类号： G01R31/28
CPC分类号： G01R31/31721 , G01R31/318575
摘要： A semiconductor integrated circuit contains a logic circuit which operates upon receiving a clock; a logic built-in self test circuit which executes a built-in self test of said logic circuit, said logic built-in self test circuit having a pattern generator which generates a pattern to be input to said logic circuit, a pattern compactor which receives data output from said logic circuit that has received the pattern, compacts the data, and outputs a result, and a logic built-in self test control unit which controls operations of said pattern generator and said pattern compactor and controls an operation of causing a scan path in said logic circuit to shift upon receiving the pattern; a device circuit which operates upon receiving the clock; and a device circuit built-in self test circuit which executes a built-in self test of said device circuit.
摘要翻译：半导体集成电路包含在接收时钟时工作的逻辑电路; 逻辑内置自检电路，其执行所述逻辑电路的内置自检，所述逻辑内置自检电路具有产生要输入到所述逻辑电路的模式的模式发生器，模式压缩器，其接收从已经接收到图案的所述逻辑电路输出的数据，压缩数据并输出结果;以及逻辑内置自检控制单元，其控制所述图案发生器和所述图案压实机的操作，并控制进行扫描的操作所述逻辑电路中的路径在接收到所述图案时移位; 接收时钟时操作的设备电路; 以及内置自检电路的器件电路，其执行所述器件电路的内置自检。

3. 发明申请

US20090324158A1 Optical modulation device and manufacturing method thereof 有权
标题翻译：光调制装置及其制造方法
公开(公告)号：US20090324158A1
公开(公告)日：2009-12-31
申请号：US12385001
申请日：2009-03-27
申请人： Takashi Shiraishi , Tetsuya Miyatake , Tetsu Hasegawa
发明人： Takashi Shiraishi , Tetsuya Miyatake , Tetsu Hasegawa
IPC分类号： G02F1/035
CPC分类号： G02B6/13 , G02B6/136 , G02B2006/1204 , G02F1/0305 , G02F1/0356 , G02F1/2255
摘要： An optical modulation device includes: a crystal substrate having an electro-optic effect; an optical waveguide formed in the crystal substrate; an electrode formed on the crystal substrate, to apply an electric field to the optical waveguide; and a buried layer of low dielectric constant buried to avoid the optical waveguide, in at least one portion of a lower region of the electrode inside the crystal substrate, which is spaced from both of a front surface of the crystal substrate on which the electrode is formed and a rear surface thereof opposed to the front surface.
摘要翻译：光调制装置包括：具有电光效应的晶体基板; 形成在晶体基板中的光波导; 形成在所述晶体基板上的电极，用于向所述光波导施加电场; 以及在晶体基板内部的电极的下部区域的至少一部分中埋设有低介电常数的掩埋层，以避免光波导与电极的晶体基板的前表面间隔开形成的后表面与前表面相对。

4. 发明授权

US07551820B2 Optical device 有权
标题翻译：光学装置
公开(公告)号：US07551820B2
公开(公告)日：2009-06-23
申请号：US12035692
申请日：2008-02-22
申请人： Akira Ishii , Takehito Tanaka , Masaharu Doi , Tetsu Hasegawa
发明人： Akira Ishii , Takehito Tanaka , Masaharu Doi , Tetsu Hasegawa
IPC分类号： G02B6/42 , G02F1/035
CPC分类号： G02B6/1228 , G02B6/14 , G02B6/29352 , G02B6/29385 , G02B2006/12142 , G02B2006/12152 , G02F1/0123 , G02F1/225 , G02F1/3132 , G02F2201/58
摘要： An optical device including (a) a substrate having an electro-optic effect; (b) an optical waveguide formed on a surface layer portion of said substrate and including an optical waveguide for performing optical modulation for light inputted to said substrate and an output optical waveguide and a monitoring optical waveguide branched from and connected to a downstream side portion of said modulating optical waveguide, said monitoring optical waveguide guiding light for monitoring optical modulation operation of said modulating optical waveguide; and (c) a reflecting portion being provided on the downstream side of said monitoring optical waveguide for reflecting light propagated along said monitoring optical waveguide, the width of a reflection face of said reflecting portion being substantially equal to the cut-out width of said monitoring optical waveguide.
摘要翻译：一种光学装置，包括（a）具有电光效应的基板; （b）形成在所述基板的表层部分上的光波导，并且包括用于对输入到所述基板的光执行光调制的光波导和从所述基板的下游侧部分分支并连接到所述基板的输出光波导和监视光波导所述调制光波导，所述监测光波导引导光用于监视所述调制光波导的光调制操作; 以及（c）反射部分设置在所述监视光波导的下游侧，用于反射沿所述监视光波导传播的光，所述反射部分的反射面的宽度基本上等于所述监视的切出宽度光波导。

5. 发明申请

US20080317424A1 Optical module and optical switching device 有权
标题翻译：光模块和光交换设备
公开(公告)号：US20080317424A1
公开(公告)日：2008-12-25
申请号：US12125957
申请日：2008-05-23
申请人： Masaharu DOI , Tetsu Hasegawa
发明人： Masaharu DOI , Tetsu Hasegawa
IPC分类号： G02B6/10
CPC分类号： G02B6/4214 , G02B6/4206 , G02B2006/1204 , G02B2006/12142 , G02F1/0123 , G02F1/225
摘要： The invention relates to an optical device which can increase the spread of a beam diameter in the depthwise direction by a simple configuration in comparison with that by prior art devices. The optical device includes a substrate, an optical path formed on the substrate, and a diffraction propagation region, provided between the optical path and an end face of the substrate, for propagating light emitted from the optical path with diffraction. The diffraction propagation region includes a first groove, formed therein, adapted to block part of components of the propagated light in a depthwise direction of the substrate.
摘要翻译：本发明涉及一种光学装置，其可以通过与现有技术装置相比较的简单配置来增加光束直径在深度方向上的扩展。光学器件包括基板，形成在基板上的光路和设置在光路和基板的端面之间的衍射传播区域，用于传播从光路发射的光。衍射传播区域包括形成在其中的第一凹槽，其适于在衬底的深度方向上阻挡传播光的部件的一部分。

6. 发明授权

US08774583B2 Optical device and optical transmitter 有权
标题翻译：光学设备和光发射机
公开(公告)号：US08774583B2
公开(公告)日：2014-07-08
申请号：US12685374
申请日：2010-01-11
申请人： Takashi Shiraishi , Tetsu Hasegawa , Masaharu Doi
发明人： Takashi Shiraishi , Tetsu Hasegawa , Masaharu Doi
IPC分类号： G02B6/10
CPC分类号： G02B6/125 , G02B2006/12097 , G02B2006/12119
摘要： An optical device and an optical transmitter are provided. The optical device includes a substrate, a first optical waveguide that may be formed in the substrate and may have a bending portion, and a second optical waveguide that intersects with the bending portion of the first optical waveguide, wherein a groove may be formed outside the bending portion of the first optical waveguide in the substrate.
摘要翻译：提供光学装置和光发射机。光学装置包括基板，可以形成在基板中并且可以具有弯曲部分的第一光波导和与第一光波导的弯曲部相交的第二光波导，其中，可以在第一光波导的弯曲部分。

7. 发明申请

US20120226953A1 SEMICONDUCTOR INTEGRATED CIRCUIT, DESIGN APPARATUS AND DESIGN METHOD 审中-公开
标题翻译：半导体集成电路，设计器件和设计方法
公开(公告)号：US20120226953A1
公开(公告)日：2012-09-06
申请号：US13235175
申请日：2011-09-16
申请人： Masato NAKAZATO , Kenichi ANZOU , Tetsu HASEGAWA
发明人： Masato NAKAZATO , Kenichi ANZOU , Tetsu HASEGAWA
IPC分类号： G01R31/3177 , G06F11/25
CPC分类号： G06F11/27 , G01R31/318552 , G01R31/318594
摘要： A semiconductor integrated circuit has one or more of scan chains each having series-connected flip-flops that exist in an internal circuit. Each scan chain is divided into a plurality of segments. Each segment is controllable a timing of a clock signal. The semiconductor integrated circuit has a clock gating circuit capable of being shared by the scan chains and configured to generate a plurality of clock signals for driving each segment, the clock gating circuit being provided for each scan chain, and a segment control signal generator configured to generate a control signal to be used when the clock gating circuit generates the clock signals so that an effect of a fault of the internal circuit is transferred through one of the segments and care bits corresponding to a next fault are captured in a corresponding segment.
摘要翻译：半导体集成电路具有一个或多个扫描链，每个扫描链具有存在于内部电路中的串联的触发器。每个扫描链被分成多个段。每个段可控制时钟信号的定时。半导体集成电路具有时钟门控电路，能够由扫描链共享，并且被配置为产生用于驱动每个段的多个时钟信号，为每个扫描链提供时钟选通电路，以及分段控制信号发生器，被配置为当时钟选通电路产生时钟信号时，产生要使用的控制信号，以便内部电路的故障的影响通过其中一个段传送，并且对应于下一个故障的保护位被捕获在相应的段中。

8. 发明申请

US20090282285A1 Semiconductor Integrated Circuit, Design Support Software System, And Automatic Test Pattern Generation System 有权
标题翻译：半导体集成电路，设计支持软件系统和自动测试模式生成系统
公开(公告)号：US20090282285A1
公开(公告)日：2009-11-12
申请号：US12503336
申请日：2009-07-15
申请人： Tetsu HASEGAWA , Chikako TOKUNAGA
发明人： Tetsu HASEGAWA , Chikako TOKUNAGA
IPC分类号： G06F11/20
CPC分类号： G11C29/54 , G11C2029/0405 , G11C2029/3602
摘要： A semiconductor integrated circuit has a memory circuit having memory cells, a first register, a second register, a register selection circuit having an input to which an output of the first register and an output of the second register are connected, a memory bypass circuit which is located between a first switching circuit and a second switching circuit, and connected to the inputs and the outputs of the memory circuit. The register selection circuit is switched to the output signals of the first register when performing testing by way of the memory circuit, and switched to output signals of the second register when performing testing by way of the memory bypass circuit.
摘要翻译：一种半导体集成电路具有存储单元的存储电路，第一寄存器，第二寄存器，具有第一寄存器的输出和第二寄存器的输出的输入的寄存器选择电路，存储器旁路电路，位于第一开关电路和第二开关电路之间，并连接到存储器电路的输入端和输出端。当通过存储器电路进行测试时，寄存器选择电路切换到第一寄存器的输出信号，并且当通过存储器旁路电路进行测试时，将其切换到第二寄存器的输出信号。

9. 发明申请

US20080019632A1 OPTICAL DEVICE 有权
标题翻译：光学装置
公开(公告)号：US20080019632A1
公开(公告)日：2008-01-24
申请号：US11775917
申请日：2007-07-11
申请人： Akira Ishii , Takehito Tanaka , Masaharu Doi , Tetsu Hasegawa
发明人： Akira Ishii , Takehito Tanaka , Masaharu Doi , Tetsu Hasegawa
IPC分类号： G02F1/035
CPC分类号： G02B6/1228 , G02B6/14 , G02B6/29352 , G02B6/29385 , G02B2006/12142 , G02B2006/12152 , G02F1/0123 , G02F1/225 , G02F1/3132 , G02F2201/58
摘要： An optical device is disclosed which suppresses a bias shift which is a deviation of a phase relationship between output signal light and monitoring light. The optical device includes a substrate having an electro-optic effect, a modulating optical waveguide formed on a surface layer portion of the substrate and forming an interference optical modulator for modulating input light, and an output optical waveguide and a monitoring optical waveguide each formed on the surface layer portion of the substrate and branched from and connected to a downstream side portion of the modulating optical waveguide. The monitoring optical waveguide guides light for monitoring optical modulation operation of the modulating optical waveguide. The monitoring optical waveguide has a reduced width region which has a reduced waveguide width.
摘要翻译：公开了抑制作为输出信号光与监视光之间的相位关系的偏差的偏移偏移的光学装置。光学装置包括具有电光效应的基板，形成在基板的表面层部分上并形成用于调制输入光的干涉光调制器的调制光波导，以及形成在其上的输出光波导和监视光波导衬底的表层部分并且分支并连接到调制光波导的下游侧部分。监视光波导引导用于监视调制光波导的光调制操作的光。监控光波导具有减小的波导宽度的减小的宽度区域。

10. 发明申请

US20050010886A1 Apparatus for generating test vector of semiconductor integrated circuit 失效
标题翻译：用于生成半导体集成电路测试矢量的装置
公开(公告)号：US20050010886A1
公开(公告)日：2005-01-13
申请号：US10695698
申请日：2003-10-28
申请人： Koji Urata , Kenichi Anzou , Tetsu Hasegawa , Chikako Tokunaga
发明人： Koji Urata , Kenichi Anzou , Tetsu Hasegawa , Chikako Tokunaga
IPC分类号： G01R31/3183 , G01R31/3181 , G01R31/319 , G06F9/45 , G01R31/28 , G06F11/00
CPC分类号： G01R31/31919 , G01R31/31813 , G01R31/31917
摘要： A method for generating a test vector of a semiconductor integrated circuit including: designating a retrieval condition to select a path on which a signal can be transmitted in the circuit; executing a timing analysis of the circuit based on a circuit information of the circuit, retrieving the path satisfying the retrieval condition, and generating a path list in which cells composing the retrieved path are put in order of executing the timing analysis; generating a test vector to test a path delay fault of the circuit based on the path list; designating an ending condition to end generation of the test vector when the path in the path list for the test vector is distributed over the circuit; and stopping generation of the path list when the ending condition is satisfied.
摘要翻译：一种用于生成半导体集成电路的测试向量的方法，包括：指定检索条件以选择可在其中传输信号的路径; 根据电路的电路信息执行电路的定时分析，检索满足检索条件的路径，生成构成检索路径的单元的路径列表，按顺序执行定时分析; 生成测试向量，以基于路径列表测试电路的路径延迟故障; 当测试向量的路径列表中的路径分布在电路上时，指定结束条件以终止生成测试向量; 并且当满足结束条件时停止生成路径列表。

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