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1. 发明授权

US07449916B2 Voltage level shift circuit 有权
标题翻译：电压电平移位电路
公开(公告)号：US07449916B2
公开(公告)日：2008-11-11
申请号：US11417372
申请日：2006-05-03
申请人： Chien-Ru Chen , Ying-Lieh Chen , Lin-Kai Bu , Yu-Jui Chang
发明人： Chien-Ru Chen , Ying-Lieh Chen , Lin-Kai Bu , Yu-Jui Chang
IPC分类号： H03K19/094 , H03K19/0175 , H03L5/00
CPC分类号： H03K19/018528
摘要： A voltage level shift circuit is provided. The circuit includes an input buffer unit, a level shift unit and a voltage stabilizing capacitor. The input buffer is coupled between a first voltage source and a first ground terminal. The level shift unit is coupled between a second voltage source and a second ground terminal. An input terminal of the level shift unit is coupled to an output terminal of the input buffer unit. The voltage stabilizing capacitor is coupled between the first voltage source and the second ground terminal. When a state transition occurs in the level shift unit, the voltage stabilizing capacitor maintains a voltage difference between the output terminal of the input buffer unit and the second ground terminal.
摘要翻译：提供电压电平移位电路。电路包括输入缓冲单元，电平移位单元和稳压电容器。输入缓冲器耦合在第一电压源和第一接地端子之间。电平移位单元耦合在第二电压源和第二接地端子之间。电平移位单元的输入端子耦合到输入缓冲器单元的输出端子。稳压电容器耦合在第一电压源和第二接地端子之间。当在电平移位单元中发生状态转移时，稳压电容器保持输入缓冲器单元的输出端子与第二接地端子之间的电压差。

2. 发明申请

US20070222478A1 Voltage level shift circuit 有权
标题翻译：电压电平移位电路
公开(公告)号：US20070222478A1
公开(公告)日：2007-09-27
申请号：US11417372
申请日：2006-05-03
申请人： Chien-Ru Chen , Ying-Lieh Chen , Lin-Kai Bu , Yu-Jui Chang
发明人： Chien-Ru Chen , Ying-Lieh Chen , Lin-Kai Bu , Yu-Jui Chang
IPC分类号： H03K19/0175
CPC分类号： H03K19/018528
摘要： A voltage level shift circuit is provided. The circuit includes an input buffer unit, a level shift unit and a voltage stabilizing capacitor. The input buffer is coupled between a first voltage source and a first ground terminal. The level shift unit is coupled between a second voltage source and a second ground terminal. An input terminal of the level shift unit is coupled to an output terminal of the input buffer unit. The voltage stabilizing capacitor is coupled between the first voltage source and the second ground terminal. When a state transition occurs in the level shift unit, the voltage stabilizing capacitor maintains a voltage difference between the output terminal of the input buffer unit and the second ground terminal.
摘要翻译：提供电压电平移位电路。电路包括输入缓冲单元，电平移位单元和稳压电容器。输入缓冲器耦合在第一电压源和第一接地端子之间。电平移位单元耦合在第二电压源和第二接地端子之间。电平移位单元的输入端子耦合到输入缓冲器单元的输出端子。稳压电容器耦合在第一电压源和第二接地端子之间。当在电平移位单元中发生状态转移时，稳压电容器保持输入缓冲器单元的输出端子与第二接地端子之间的电压差。

3. 发明授权

US07642800B2 Wafer test system wherein period of high voltage stress test of one chip overlaps period of function test of other chip 有权
标题翻译：晶片测试系统，其中一个芯片的高压应力测试周期与其他芯片的功能测试周期重叠
公开(公告)号：US07642800B2
公开(公告)日：2010-01-05
申请号：US11848954
申请日：2007-08-31
申请人： Tzong-Yau Ku , Chien-Ru Chen , Chin-Tien Chang , Ying-Lieh Chen , Lin-Kai Bu
发明人： Tzong-Yau Ku , Chien-Ru Chen , Chin-Tien Chang , Ying-Lieh Chen , Lin-Kai Bu
IPC分类号： G01R31/02 , G01R31/26
CPC分类号： G01R31/2851 , G01R31/2831 , G01R31/2884
摘要： A wafer, a test system thereof, a test method thereof and a test device thereof are provided. The present invention utilizes a first group of probes to perform a high voltage stress (HVS) test on a first chip, and utilizes a second group of probes to perform a function test on a second chip, where a period of the high voltage stress test overlaps a period of the function test, thereby greatly decreasing the test time of the wafer.
摘要翻译：提供晶片，其测试系统，其测试方法和测试装置。本发明利用第一组探针在第一芯片上执行高压应力（HVS）测试，并利用第二组探针在第二芯片上执行功能测试，其中高压应力测试与功能测试的周期重叠，从而大大降低了晶片的测试时间。

4. 发明授权

US07843420B2 LCD with source driver and data transmitting method thereof 有权
标题翻译：具有源驱动器的LCD及其数据发送方法
公开(公告)号：US07843420B2
公开(公告)日：2010-11-30
申请号：US11802979
申请日：2007-05-29
申请人： Chien-Ru Chen , Ying-Lieh Chen , Lin-Kai Bu
发明人： Chien-Ru Chen , Ying-Lieh Chen , Lin-Kai Bu
IPC分类号： G09G3/36
CPC分类号： G09G3/3685 , G09G3/2092
摘要： A data transmitting method for inputting a data signal to an electronic device. The data signal includes first and second sets of data, and the electronic device includes first to fourth receiving units and corresponding first to fourth registers. The transmitting method includes the following steps. First, the first and second receiving units are disabled. Then, the first set of data is inputted to the electronic device through the third and fourth receiving units and stored in the third and fourth registers during a first clock cycle of a clock signal. Thereafter, the second set of data is inputted to the electronic device through the third and fourth receiving units and stored in the third and fourth registers while the first set of data stored in the third and fourth registers is inputted to the first and second registers during a second clock cycle of the clock signal.
摘要翻译：一种用于向电子设备输入数据信号的数据发送方法。数据信号包括第一和第二组数据，电子设备包括第一至第四接收单元和对应的第一至第四寄存器。发送方法包括以下步骤。首先，第一和第二接收单元被禁用。然后，第一组数据通过第三和第四接收单元输入到电子设备，并且在时钟信号的第一时钟周期期间被存储在第三和第四寄存器中。此后，第二组数据通过第三和第四接收单元输入到电子装置，并存储在第三和第四寄存器中，而存储在第三和第四寄存器中的第一组数据被输入到第一和第二寄存器时钟信号的第二个时钟周期。

5. 发明申请

US20100045319A1 WAFER AND TEST METHOD THEREOF 有权
标题翻译：其方法及其测试方法
公开(公告)号：US20100045319A1
公开(公告)日：2010-02-25
申请号：US12609365
申请日：2009-10-30
申请人： Tzong-Yau Ku , Chien-Ru Chen , Chin-Tien Chang , Ying-Lieh Chen , Lin-Kai Bu
发明人： Tzong-Yau Ku , Chien-Ru Chen , Chin-Tien Chang , Ying-Lieh Chen , Lin-Kai Bu
IPC分类号： G01R1/06 , G01R31/02 , G01R31/26
CPC分类号： G01R31/2851 , G01R31/2831 , G01R31/2884
摘要： A wafer and a test method thereof are provided. The invention utilizes a first group of probes to perform a high voltage stress (HVS) test on a first chip, and utilizes a second group of probes to perform a function test on a second chip, where a period of the high voltage stress test overlaps a period of the function test, thereby greatly decreasing the test time of the wafer.
摘要翻译：提供晶片及其测试方法。本发明利用第一组探针在第一芯片上执行高电压应力（HVS）测试，并且利用第二组探针在第二芯片上进行功能测试，其中高压应力测试的周期重叠功能测试的一段时间，从而大大降低了晶片的测试时间。

6. 发明申请

US20090058438A1 WAFER, TEST SYSTEM THEREOF, TEST METHOD THEREOF AND TEST DEVICE THEREOF 有权
标题翻译： WAFER，测试系统及其测试方法及其测试设备
公开(公告)号：US20090058438A1
公开(公告)日：2009-03-05
申请号：US11848954
申请日：2007-08-31
申请人： Tzong-Yau Ku , Chien-Ru Chen , Chin-Tien Chang , Ying-Lieh Chen , Lin-Kai Bu
发明人： Tzong-Yau Ku , Chien-Ru Chen , Chin-Tien Chang , Ying-Lieh Chen , Lin-Kai Bu
IPC分类号： G01R31/26
CPC分类号： G01R31/2851 , G01R31/2831 , G01R31/2884
摘要： A wafer, a test system thereof, a test method thereof and a test device thereof are provided. The present invention utilizes a first group of probes to perform a high voltage stress (HVS) test on a first chip, and utilizes a second group of probes to perform a function test on a second chip, where a period of the high voltage stress test overlaps a period of the function test, thereby greatly decreasing the test time of the wafer.
摘要翻译：提供晶片，其测试系统，其测试方法和测试装置。本发明利用第一组探针在第一芯片上执行高压应力（HVS）测试，并利用第二组探针在第二芯片上执行功能测试，其中高压应力测试与功能测试的周期重叠，从而大大降低了晶片的测试时间。

7. 发明申请

US20080117190A1 METHOD AND DRIVER FOR DRIVING A DISPLAY 审中-公开
标题翻译：用于驱动显示器的方法和驱动器
公开(公告)号：US20080117190A1
公开(公告)日：2008-05-22
申请号：US11562504
申请日：2006-11-22
申请人： Chien-Ru Chen , Ying-Lieh Chen , Lin-Kai Bu
发明人： Chien-Ru Chen , Ying-Lieh Chen , Lin-Kai Bu
IPC分类号： G06F3/038
CPC分类号： G09G3/3685 , G09G2310/027 , G09G2310/08 , G09G2320/0209
摘要： First and second bits of pixel values of the display are received, and each of the first and second bits is forwarded through one of data signals. Then, levels of the data signals are shifted, and the forwarded first and second bits are received through the level-shifted data signals to convert the pixel values into analog voltages driving the display. The level-shifted data signals through which the forwarded first and second bits are received are generated in a first and second phase, respectively.
摘要翻译：接收显示器的第一和第二位像素值，并且通过数据信号之一转发第一和第二位中的每一个。然后，数据信号的电平被移位，并且通过电平移位的数据信号接收转发的第一和第二位，以将像素值转换成驱动显示器的模拟电压。在第一和第二阶段分别产生经过转发的第一和第二比特被接收的电平移位数据信号。

8. 发明申请

US20080030452A1 METHOD AND CIRCUIT FOR CONTROLLING THE VOLTAGE POLARITY OF PIXEL STRUCTURE 审中-公开
标题翻译：用于控制像素结构电压极性的方法和电路
公开(公告)号：US20080030452A1
公开(公告)日：2008-02-07
申请号：US11462003
申请日：2006-08-02
申请人： Chien-Ru Chen , Ying-Lieh Chen , Lin-Kai Bu
发明人： Chien-Ru Chen , Ying-Lieh Chen , Lin-Kai Bu
IPC分类号： G09G3/36
CPC分类号： G09G3/3614 , G09G3/3655
摘要： In a pixel array, each column of the pixel array is coupled to one of a plurality of first and second channels of a driver. A first and second control signals are generated. Polarities of the first channels are inversed when a logic level of the first control signal changes and polarities of the second channels are inversed when a logic level of the second control signal changes. Only the logic level of one of the first and second control signals changes in response to each transition of scan periods.
摘要翻译：在像素阵列中，像素阵列的每列耦合到驱动器的多个第一和第二通道中的一个。产生第一和第二控制信号。当第二控制信号的逻辑电平改变时，第一通道的极性反转，当第二控制信号的逻辑电平改变时，第二通道的极性反转。只有第一和第二控制信号之一的逻辑电平响应于扫描周期的每个转换而改变。

9. 发明授权

US08274302B2 Wafer and test method thereof 有权
标题翻译：晶圆及其测试方法
公开(公告)号：US08274302B2
公开(公告)日：2012-09-25
申请号：US12609365
申请日：2009-10-30
申请人： Tzong-Yau Ku , Chien-Ru Chen , Chin-Tien Chang , Ying-Lieh Chen , Lin-Kai Bu
发明人： Tzong-Yau Ku , Chien-Ru Chen , Chin-Tien Chang , Ying-Lieh Chen , Lin-Kai Bu
IPC分类号： G01R31/02 , G01R31/26
CPC分类号： G01R31/2851 , G01R31/2831 , G01R31/2884
摘要： A wafer and a test method thereof are provided. The invention utilizes a first group of probes to perform a high voltage stress (HVS) test on a first chip, and utilizes a second group of probes to perform a function test on a second chip, where a period of the high voltage stress test overlaps a period of the function test, thereby greatly decreasing the test time of the wafer.
摘要翻译：提供晶片及其测试方法。本发明利用第一组探针在第一芯片上执行高电压应力（HVS）测试，并且利用第二组探针在第二芯片上进行功能测试，其中高压应力测试的周期重叠功能测试的一段时间，从而大大降低了晶片的测试时间。

10. 发明申请

US20080303771A1 DISPLAY AND TWO STEP DRIVING METHOD THEREOF 审中-公开
标题翻译：显示和两步驱动方法
公开(公告)号：US20080303771A1
公开(公告)日：2008-12-11
申请号：US11839297
申请日：2007-08-15
申请人： Ying-Lieh Chen , Lin-Kai Bu , Chien-Ru Chen , Chih-Hsing Chang , Wen-Tsung Lin , Yung-Yu Tsai , Yung-Li Huang
发明人： Ying-Lieh Chen , Lin-Kai Bu , Chien-Ru Chen , Chih-Hsing Chang , Wen-Tsung Lin , Yung-Yu Tsai , Yung-Li Huang
IPC分类号： G09G3/36
CPC分类号： G09G3/3688 , G09G3/3614 , G09G2310/0251 , G09G2310/027
摘要： A display and a two step driving method thereof are provided. The method includes: converting an image signal to a corresponding data driving voltage by using a driver; providing a pre-driving voltage by using a voltage generator; and finally, driving the display panel by using the pre-driving voltage and data driving voltage orderly during a horizontal synchronizing period. A display includes a display panel, a voltage generator, and a driver. The display panel also includes at least one data line. The voltage generator outputs a pre-driving voltage to the data line of the display. The driver outputs a data driving voltage to the data line according to an image signal, in which the data line receives the pre-driving voltage and the data driving voltage orderly during the horizontal synchronizing period.
摘要翻译：提供了一种显示器及其两步驱动方法。该方法包括：通过使用驱动器将图像信号转换成对应的数据驱动电压; 通过使用电压发生器提供预驱动电压; 最后，在水平同步期间，通过使用预驱动电压和数据驱动电压有序地驱动显示面板。显示器包括显示面板，电压发生器和驱动器。显示面板还包括至少一条数据线。电压发生器将预驱动电压输出到显示器的数据线。驱动器根据图像信号向数据线输出数据驱动电压，在图像信号中数据线在水平同步周期期间有序地接收预驱动电压和数据驱动电压。

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