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    • 8. 发明授权
    • Chip level package of light-emitting diode
    • 芯片级封装的发光二极管
    • US08344412B2
    • 2013-01-01
    • US12648911
    • 2009-12-29
    • Chia-Liang HsuShu-Ting HsuMin-Hsun HsiehChih-Chiang LuAlexander Wang
    • Chia-Liang HsuShu-Ting HsuMin-Hsun HsiehChih-Chiang LuAlexander Wang
    • H01L33/00
    • H01L33/385H01L33/62H01L2224/32245H01L2224/32257H01L2224/48091H01L2224/48247H01L2224/73265H01L2924/00014H01L2924/00
    • The application discloses a light-emitting diode chip level package structure including: a permanent substrate having a first surface and a second surface; a first electrode on the first surface; a second electrode on the second surface; an adhesive layer on where the first surface of the permanent substrate is not covered by the first electrode; a growth substrate on the adhesive layer; a patterned semiconductor structure on the growth substrate; a third electrode and a fourth electrode on the patterned semiconductor structure and electrically connect with the patterned semiconductor structure; an electrical connecting structure on the sidewall of the patterned semiconductor structure electrically connecting the third electrode and the fourth electrode with the first electrode; and an insulation layer located on the side wall of the patterned semiconductor structure and between the electrical connecting structure for electrically insulating the patterned semiconductor structure.
    • 本申请公开了一种发光二极管芯片级封装结构,包括:具有第一表面和第二表面的永久基板; 第一表面上的第一电极; 在第二表面上的第二电极; 在永久性基板的第一表面未被第一电极覆盖的粘合剂层上; 粘合剂层上的生长衬底; 生长衬底上的图案化半导体结构; 图案化半导体结构上的第三电极和第四电极,并与图案化的半导体结构电连接; 所述图案化半导体结构的侧壁上的电连接结构将所述第三电极和所述第四电极与所述第一电极电连接; 以及位于图案化半导体结构的侧壁上以及用于使图案化半导体结构电绝缘的电连接结构之间的绝缘层。