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1. 发明授权

US08835935B2 Trench MOS transistor having a trench doped region formed deeper than the trench gate 有权
标题翻译：沟槽MOS晶体管具有比沟槽栅极更深的沟槽掺杂区域
公开(公告)号：US08835935B2
公开(公告)日：2014-09-16
申请号：US13433272
申请日：2012-03-28
申请人： Chien-Chung Hung , Young-Shying Chen , Cheng-Tyng Yen , Chwan-Ying Lee
发明人： Chien-Chung Hung , Young-Shying Chen , Cheng-Tyng Yen , Chwan-Ying Lee
IPC分类号： H01L29/24
CPC分类号： H01L21/0475 , H01L29/66227 , H01L29/7827
摘要： A trench metal oxide semiconductor transistor device and a manufacturing method thereof are described. The trench metal oxide semiconductor transistor device includes a substrate of a first conductivity type, a drift region of the first conductivity type, a deep trench doped region of a second conductivity type, an epitaxial region of the second conductivity type, a trench gate, a gate insulating layer, a source region, a drain electrode and a source electrode. The drift region has at least one deep trench therein, and the deep trench doped region is disposed in the deep trench. The trench gate passes through the epitaxial region, and a distance between a bottom of the trench gate and a bottom of the deep trench doped region is 0.5˜3 μm.
摘要翻译：描述了沟槽金属氧化物半导体晶体管器件及其制造方法。沟槽金属氧化物半导体晶体管器件包括第一导电类型的衬底，第一导电类型的漂移区，第二导电类型的深沟槽掺杂区，第二导电类型的外延区，沟槽栅，栅极绝缘层，源极区，漏极和源电极。漂移区域中具有至少一个深沟槽，并且深沟槽掺杂区域设置在深沟槽中。沟槽栅极通过外延区域，并且沟槽栅极的底部与深沟槽掺杂区域的底部之间的距离为0.5〜3μm。

2. 发明申请

US20130161736A1 TRENCH METAL OXIDE SEMICONDUCTOR TRANSISTOR DEVICE AND MANUFACTURING METHOD THEREOF 有权
标题翻译：铁氧体氧化物半导体晶体管器件及其制造方法
公开(公告)号：US20130161736A1
公开(公告)日：2013-06-27
申请号：US13433272
申请日：2012-03-28
申请人： Chien-Chung Hung , Young-Shying Chen , Cheng-Tyng Yen , Chwan-Ying Lee
发明人： Chien-Chung Hung , Young-Shying Chen , Cheng-Tyng Yen , Chwan-Ying Lee
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L21/0475 , H01L29/66227 , H01L29/7827
摘要： A trench metal oxide semiconductor transistor device and a manufacturing method thereof are described. The trench metal oxide semiconductor transistor device includes a substrate of a first conductivity type, a drift region of the first conductivity type, a deep trench doped region of a second conductivity type, an epitaxial region of the second conductivity type, a trench gate, a gate insulating layer, a source region, a drain electrode and a source electrode. The drift region has at least one deep trench therein, and the deep trench doped region is disposed in the deep trench. The trench gate passes through the epitaxial region, and a distance between a bottom of the trench gate and a bottom of the deep trench doped region is 0.5˜3 um.
摘要翻译：描述了沟槽金属氧化物半导体晶体管器件及其制造方法。沟槽金属氧化物半导体晶体管器件包括第一导电类型的衬底，第一导电类型的漂移区，第二导电类型的深沟槽掺杂区，第二导电类型的外延区，沟槽栅，栅极绝缘层，源极区，漏极和源电极。漂移区域中具有至少一个深沟槽，并且深沟槽掺杂区域设置在深沟槽中。沟槽栅极通过外延区域，并且沟槽栅极的底部和深沟槽掺杂区域的底部之间的距离为0.5〜3um。

3. 发明授权

US06436816B1 Method of electroless plating copper on nitride barrier 失效
标题翻译：在氮化物屏障上化学镀铜的方法
公开(公告)号：US06436816B1
公开(公告)日：2002-08-20
申请号：US09127463
申请日：1998-07-31
申请人： Chwan-Ying Lee , Tzuen-Hsi Huang
发明人： Chwan-Ying Lee , Tzuen-Hsi Huang
IPC分类号： H01L214763
CPC分类号： H05K3/108 , C23C18/1605 , C23C18/161 , C23C18/36 , C23C18/48 , H01L21/288 , H01L21/32053 , H01L21/76885 , H01L24/11 , H01L2224/05001 , H01L2224/05023 , H01L2224/0508 , H01L2224/05568 , H01L2224/1308 , H01L2224/13084 , H01L2224/13116 , H01L2224/13124 , H01L2224/13147 , H01L2224/13155 , H01L2224/13164 , H01L2924/00013 , H01L2924/01005 , H01L2924/01006 , H01L2924/01011 , H01L2924/01012 , H01L2924/01013 , H01L2924/01015 , H01L2924/0102 , H01L2924/01022 , H01L2924/01027 , H01L2924/01029 , H01L2924/0103 , H01L2924/01033 , H01L2924/01039 , H01L2924/01042 , H01L2924/01046 , H01L2924/01059 , H01L2924/01067 , H01L2924/01072 , H01L2924/01073 , H01L2924/01074 , H01L2924/01078 , H01L2924/01082 , H01L2924/014 , H01L2924/04941 , H01L2924/04953 , H01L2924/14 , H05K3/388 , H05K2203/072 , H01L2924/00014 , H01L2924/01014 , H01L2924/0105 , H01L2224/13099 , H01L2224/05664 , H01L2224/05124 , H01L2224/05164 , H01L2224/05166
摘要： A method with three embodiments of manufacturing metal lines and solder bumps using electroless deposition techniques. The first embodiment uses a PdSix seed layer 50 for electroless deposition. The PdSix layer 50 does not require activation. A metal line is formed on a barrier layer 20 and an adhesion layer 30. A Palladium silicide seed layer 50 is then formed and patterned. Ni, Pd or Cu is electroless deposited over the Palladium silicide layer 50 to form a metal line. The second embodiment selectively electrolessly deposits metal 140 over an Adhesion layer 130 composed of Poly Si, Al, or Ti. A photoresist pattern 132 is formed over the adhesion layer. A metal layer 140 of Cu or Ni is electrolessly deposited over the adhesion layer. The photoresist layer 132 is removed and the exposed portion of the adhesion layer 130 and the underlying barrier metal layer 120 are etched thereby forming a metal line. The third embodiment electroless deposits metal over a metal barrier layer that is roughen by chemical mechanical polishing. A solder bump is formed using an electroless deposition of Cu or Ni by: depositing an Al layer 220 and a barrier metal layer 230 over a substrate 10. The barrier layer 230 is polished and activated. Next, the aluminum layer 220 and the barrier metal layer 230 are patterned. A metal layer 240 is electroless deposited. Next a solder bump 250 is formed over the electroless metal layer 240.
摘要翻译：具有使用无电沉积技术制造金属线和焊料凸块的三个实施例的方法。第一实施例使用PdSix种子层50进行无电沉积。 PdSix层50不需要激活。在阻挡层20和粘合层30上形成金属线。然后形成硅化物种子层50并构图。在钯硅化物层50上无电沉积Ni，Pd或Cu以形成金属线。第二实施例选择性地将金属140沉积在由多晶硅，Al或Ti组成的粘附层130上。光致抗蚀剂图案132形成在粘附层上。 Cu或Ni的金属层140无电沉积在粘附层上。去除光致抗蚀剂层132，并且粘附层130和下面的阻挡金属层120的暴露部分被蚀刻从而形成金属线。第三实施例通过化学机械抛光粗糙化的金属阻挡层上的无电沉积金属。使用Cu或Ni的无电沉积形成焊料凸点：在衬底10上沉积Al层220和阻挡金属层230.阻挡层230被抛光和激活。接着，对铝层220和阻挡金属层230进行图案化。无电沉积金属层240。接下来，在无电金属层240上形成焊料凸点250。

4. 发明授权

US06660625B2 Method of electroless plating copper on nitride barrier 有权
标题翻译：在氮化物屏障上化学镀铜的方法
公开(公告)号：US06660625B2
公开(公告)日：2003-12-09
申请号：US10156635
申请日：2002-05-28
申请人： Chwan-Ying Lee , Tzuen-Hsi Huang
发明人： Chwan-Ying Lee , Tzuen-Hsi Huang
IPC分类号： H01L2144
CPC分类号： H05K3/108 , C23C18/1605 , C23C18/161 , C23C18/36 , C23C18/48 , H01L21/288 , H01L21/32053 , H01L21/76885 , H01L24/11 , H01L2224/05001 , H01L2224/05023 , H01L2224/0508 , H01L2224/05568 , H01L2224/1308 , H01L2224/13084 , H01L2224/13116 , H01L2224/13124 , H01L2224/13147 , H01L2224/13155 , H01L2224/13164 , H01L2924/00013 , H01L2924/01005 , H01L2924/01006 , H01L2924/01011 , H01L2924/01012 , H01L2924/01013 , H01L2924/01015 , H01L2924/0102 , H01L2924/01022 , H01L2924/01027 , H01L2924/01029 , H01L2924/0103 , H01L2924/01033 , H01L2924/01039 , H01L2924/01042 , H01L2924/01046 , H01L2924/01059 , H01L2924/01067 , H01L2924/01072 , H01L2924/01073 , H01L2924/01074 , H01L2924/01078 , H01L2924/01082 , H01L2924/014 , H01L2924/04941 , H01L2924/04953 , H01L2924/14 , H05K3/388 , H05K2203/072 , H01L2924/00014 , H01L2924/01014 , H01L2924/0105 , H01L2224/13099 , H01L2224/05664 , H01L2224/05124 , H01L2224/05164 , H01L2224/05166
摘要： A method with three embodiments of manufacturing metal lines and solder bumps using electroless deposition techniques. The first embodiment uses a PdSix seed layer 50 for electroless deposition. The PdSix layer 50 does not require activation. A metal line is formed on a barrier layer 20 and an adhesion layer 30. A palladium silicide seed layer 50 is then formed and patterned. Ni, Pd or Cu is electroless deposited over the palladium silicide layer 50 to form a metal line. The second embodiment selectively electrolessly deposits metal 140 over an adhesion layer 130 composed of poly Si, Al, or Ti. A photoresist pattern 132 is formed over the adhesion layer. A metal layer 140 of Cu or Ni is electrolessly deposited over the adhesion layer. The photoresist layer 132 is removed and the exposed portion of the adhesion layer 130 and the underlying barrier metal layer 120 are etched thereby forming a metal line. The third embodiment electroless deposits metal over a metal barrier layer that is roughen by chemical-mechanical polishing. A solder bump is formed using an electroless deposition of Cu or Ni by: depositing an Al layer 230 and a barrier metal layer 230 over a substrate 10. The barrier layer 230 is polished and activated. Next, the aluminum layer 220 and the barrier metal layer 230 are patterned. A metal layer 240 is electroless deposited. Next a solder bump 250 is formed over the electroless metal layer 240.
摘要翻译：具有使用无电沉积技术制造金属线和焊料凸块的三个实施例的方法。第一实施例使用PdSix种子层50进行无电沉积。 PdSix层50不需要激活。在阻挡层20和粘合层30上形成金属线。然后形成硅化钯种子层50并构图。在钯硅化物层50上无电沉积Ni，Pd或Cu以形成金属线。第二实施例选择性地将金属140沉积在由多晶Si，Al或Ti组成的粘附层130上。光致抗蚀剂图案132形成在粘附层上。 Cu或Ni的金属层140无电沉积在粘附层上。去除光致抗蚀剂层132，并且蚀刻粘附层130和下面的阻挡金属层120的暴露部分，从而形成金属线。第三实施例通过化学机械抛光将金属沉积在金属阻挡层上，粗糙化。使用Cu或Ni的无电沉积形成焊料凸点：在衬底10上沉积Al层230和阻挡金属层230.阻挡层230被抛光和激活。接着，对铝层220和阻挡金属层230进行图案化。无电沉积金属层240。接下来，在无电金属层240上形成焊料凸点250。

5. 发明授权

US06228733B1 Non-selective epitaxial depostion technology 有权
标题翻译：非选择性外延沉积技术
公开(公告)号：US06228733B1
公开(公告)日：2001-05-08
申请号：US09400632
申请日：1999-09-23
申请人： Chwan-Ying Lee , Tzuen-Hsi Huang
发明人： Chwan-Ying Lee , Tzuen-Hsi Huang
IPC分类号： H01L21331
CPC分类号： H01L29/66272
摘要： Base layer formation without the use of selective epitaxial deposition is described. The process begins with the deposition of a seed layer of polysilicon over both the field oxide and the wafer surface that lies between them. An opening in said seed layer is then formed, between the areas of field oxide (and overlying an N+ buried layer). Non-selective epitaxial growth is then used to deposit the transistor's base layer. This automatically results in the formation of self aligned butted contacts of polysilicon on either side of the base. Manufacture of the transistor is completed in the usual way—emitter formation, emitter poly contact formation, ILD deposition, etc.
摘要翻译：描述了不使用选择性外延沉积的基底层形成。该过程开始于沉积位于它们之间的场氧化物和晶片表面上的多晶硅种子层。然后在场氧化物的区域（并覆盖N +掩埋层）之间形成所述种子层中的开口。然后使用非选择性外延生长沉积晶体管的基极层。这自动导致在基底的任一侧上形成多晶硅自对准对接的接触。晶体管的制造以通常的方式完成 - 发射极形成，发射极多接触形成，ILD沉积等。

6. 发明授权

US5801100A Electroless copper plating method for forming integrated circuit structures 失效
标题翻译：用于形成集成电路结构的无电镀铜方法
公开(公告)号：US5801100A
公开(公告)日：1998-09-01
申请号：US813719
申请日：1997-03-07
申请人： Chwan-Ying Lee , Tzuen-Hsi Huang
发明人： Chwan-Ying Lee , Tzuen-Hsi Huang
IPC分类号： H01L21/02 , H01L21/288 , H01L21/768 , H05K1/16 , H05K3/24 , H05K3/46 , H01L21/44
CPC分类号： H01L28/10 , H01L21/288 , H01L21/76885 , H05K1/165 , H05K3/244 , H05K3/4644 , Y10S257/904
摘要： A method for fabricating a copper containing integrated circuit structure within an integrated circuit, and the copper containing integrated circuit structure formed through the method. There is first provided a substrate layer. There is then formed through a first electroless plating method a nickel containing conductor layer over the substrate layer. There is then activated the nickel containing conductor layer to form an activated nickel surface of the nickel containing conductor layer. Finally, there is then formed through a second electroless plating method a copper containing conductor layer upon the nickel containing conductor layer. Optionally, there may be formed a polysilicon layer over the substrate prior to forming the nickel containing conductor layer over the substrate, where the nickel containing conductor layer is formed upon the polysilicon layer. Optionally, there may also be formed a second nickel containing conductor layer upon the copper containing conductor layer. The method is useful in forming copper containing integrated circuit inductor structures within integrated circuits.
摘要翻译：一种在集成电路内制造含铜集成电路结构的方法，以及通过该方法形成的含铜集成电路结构。首先提供衬底层。然后通过第一无电镀法在基底层上形成含镍导体层。然后激活含镍导体层以形成含镍导体层的活化镍表面。最后，通过第二无电镀法在含镍导体层上形成含铜导体层。可选地，在衬底上形成含镍导体层之前，可以在衬底上形成多晶硅层，其中在多晶硅层上形成含镍导体层。可选地，也可以在含铜导体层上形成第二含镍导体层。该方法在集成电路中形成含铜集成电路电感器结构中是有用的。

7. 发明授权

US06406743B1 Nickel-silicide formation by electroless Ni deposition on polysilicon 失效
标题翻译：通过无电Ni沉积在多晶硅上形成硅化镍
公开(公告)号：US06406743B1
公开(公告)日：2002-06-18
申请号：US08891127
申请日：1997-07-10
申请人： Chwan-Ying Lee , Tzuen-Hsi Huang
发明人： Chwan-Ying Lee , Tzuen-Hsi Huang
IPC分类号： B05D512
CPC分类号： H01L21/32053 , C23C18/1608 , C23C18/1612 , C23C18/36 , H01L21/288
摘要： The present invention provides a method of manufacturing a nickel-silicide technology for polysilicon interconnects. Nickel 40 is deposited on polysilicon 30 using a electroless process. Using a rapid thermal anneal process, Ni 40 is transformed to NiSi at about 600° C. without any agglomeration. The method comprises forming a polysilicon layer 30 over a substrate 10. The surface 34 of the polysilicon layer is activated. Nickel 40 is selectively electroless deposited onto the surface of the polysilicon layer forming a Nickel layer over the polysilicon layer. The Ni layer 40 is rapidly thermally annealed forming a Nickel silicide layer 36 over the polysilicon layer 30. The rapid thermal anneal is performed at a temperature of about 600° C. for a time of about 40 sec. The Nickel silicide layer 36 preferably comprises NiSi 36B with a low resistivity.
摘要翻译：本发明提供一种制造用于多晶硅互连的硅化镍技术的方法。使用无电镀方法将镍40沉积在多晶硅30上。使用快速热退火工艺，Ni 40在约600℃下转化为NiSi，没有任何附聚。该方法包括在衬底10上形成多晶硅层30.多晶硅层的表面34被激活。镍40选择性地无电沉积在多晶硅层的表面上，在多晶硅层上形成镍层。 Ni层40快速热退火，在多晶硅层30上形成硅化镍层36.快速热退火在约600℃的温度下进行大约40秒的时间。镍硅化物层36优选地包括具有低电阻率的NiSi 36B。

8. 发明授权

US06333235B1 Method for forming SiGe bipolar transistor 有权
标题翻译：形成SiGe双极晶体管的方法
公开(公告)号：US06333235B1
公开(公告)日：2001-12-25
申请号：US09547871
申请日：2000-04-12
申请人： Chwan-Ying Lee , Tzuen-Hsi Huang
发明人： Chwan-Ying Lee , Tzuen-Hsi Huang
IPC分类号： H01L21331
CPC分类号： H01L29/66242
摘要： A method for fabricating bipolar transistor frequently used in high frequency circuit is disclosed herein. The foregoing method includes the following steps. First, a first oxide layer is formed on a p-type substrate, followed by developing a first photoresist pattern on the first oxide layer. A first, doped region is formed in the exposed substrate by a first implanting step. The first doped region comprises a n+ buried layer. Stripping of the first photoresist pattern, and annealing of the n+ buried layer follow. Removal of the first oxide layer to expose the n+ buried layer and a portion of the p-type substrate follows thereafter. These steps are followed by growing a first epitaxial layer on the n+ buried layer and a portion of the substrate, then a second epitaxial layer is formed on the first epitaxial layer. The first epitaxial layer is made of epitaxial n-type silicon, and the second epitaxial layer is made of in situ epitaxial p-type SiGe. Next, a plurality of first and second trench isolation are formed. A gate oxide layer is formed and the extrinsic base is formed in the second epitaxial layer. A polysilicon emitter pattern is formed and is connected to the intrinsic base, followed by the fabrication of a silicide pattern connected to the n+ buried layer, whereby the collector is formed. A portion of the gate oxide layer is etched, and the underlying extrinsic base as the well as the intrinsic base acting as the base of the bipolar transistor is connected to a metal pattern.
摘要翻译：本文公开了一种频繁地用于高频电路中制造双极晶体管的方法。上述方法包括以下步骤。首先，在p型基板上形成第一氧化物层，然后在第一氧化物层上显影第一光致抗蚀剂图案。通过第一注入步骤在暴露的衬底中形成第一掺杂区域。第一掺杂区包括n +掩埋层。剥离第一光致抗蚀剂图案，并且n +掩埋层的退火遵循。此后除去第一氧化物层以露出n +掩埋层和一部分p型衬底。这些步骤之后是在n +掩埋层和衬底的一部分上生长第一外延层，然后在第一外延层上形成第二外延层。第一外延层由外延n型硅制成，第二外延层由原位外延p型SiGe制成。接下来，形成多个第一和第二沟槽隔离。形成栅氧化层，在第二外延层中形成非本征基。形成多晶硅发射极图案并连接到本征基极，随后制造连接到n +掩埋层的硅化物图案，由此形成集电极。栅极氧化物层的一部分被蚀刻，并且作为充当双极晶体管的基极的本征基极的基本外部基极连接到金属图案。

9. 发明授权

US06030877A Electroless gold plating method for forming inductor structures 失效
标题翻译：用于形成电感器结构的无电镀金方法
公开(公告)号：US06030877A
公开(公告)日：2000-02-29
申请号：US944498
申请日：1997-10-06
申请人： Chwan-Ying Lee , Tzuen-Hsi Huang
发明人： Chwan-Ying Lee , Tzuen-Hsi Huang
IPC分类号： H01L21/02 , H01L21/288 , H01L27/08 , H01L21/44
CPC分类号： H01L28/10 , H01L27/08 , H01L21/288
摘要： The present invention provides a method of manufacturing an inductor element 46 using an electroless Au plating solution. The invention has three embodiments for forming the inductor. In the first embodiment, a first insulating layer 30 is formed over a semiconductor structure 10 20. An adhesion layer 34 composed of polysilicon is formed over the first insulating layer 30. A first barrier layer 36 comprised of Ni is selectively formed using an Ni electroless plating process over the adhesion layer 34. In an important step, a gold layer 40 is electroless plated over the first barrier layer 36 using an Au electroless plating process. A second barrier layer 44 is formed over the gold layer 40 using an electroless Ni deposition technique. A planarization layer is formed over the second barrier layer. A novel core metal layer composed of a Fe--Co alloy is electroless plated over the planarization layer. The second and third embodiments vary in the process of defining the gold electroless inductor by forming the inductor in a trench. The gold electroless inductor 46 can withstand high current densities without suffering from electromigration effects and is highly corrosion resistant.
摘要翻译：本发明提供使用无电镀Au溶液制造电感元件46的方法。本发明具有形成电感器的三个实施例。在第一实施例中，在半导体结构体10上形成第一绝缘层30.在第一绝缘层30之上形成由多晶硅构成的粘附层34.由Ni化学镀选择性地形成由Ni构成的第一阻挡层36 在重要的步骤中，金层40使用Au无电镀方法在第一阻挡层36上无电镀。使用无电Ni沉积技术在金层40之上形成第二阻挡层44。在第二阻挡层上形成平坦化层。由Fe-Co合金构成的新颖的芯金属层在平坦化层上无电镀。第二和第三实施例在通过在沟槽中形成电感器来限定金无电感电感器的过程中变化。金化学电感器46可以承受高电流密度而不会受到电迁移效应，并且具有高度耐腐蚀性。

10. 发明授权

US5795619A Solder bump fabricated method incorporate with electroless deposit and dip solder 失效
标题翻译：焊接凸块制造方法结合无电沉积和浸焊
公开(公告)号：US5795619A
公开(公告)日：1998-08-18
申请号：US571401
申请日：1995-12-13
申请人： Kwang-Lung Lin , Chwan-Ying Lee
发明人： Kwang-Lung Lin , Chwan-Ying Lee
IPC分类号： C23C18/31 , C23C18/50 , B05D5/12
CPC分类号： C23C18/50 , C23C18/31
摘要： A process for preparing a solder bump can be prepared by the following procedure. The chip package was cleaned with an alkali or acid solution followed by Zn displacement (zincating)in a displacement solution which comprises NaOH, Z.sub.n o, potassium sodium tartrate and sodium nitrate. After zinc displacement the chip package was performed the electroless Ni--Cu--P deposit in the strong reducing solution which contains NaH.sub.2 PO.sub.2. The chip package deposited with Ni--Cu--P was then dipped into an organic solution as flux which is a mixture of the stearic acid and glutamic acid. Finally, dip soldering of the Ni--Cu--P deposited chip packages in a molten solder bath at a temperature 40.degree..about.80.degree. C. higher than the melting point of the corresponding Pb--Sn alloy.
摘要翻译：制备焊料凸点的方法可以通过以下步骤制备。用碱或酸溶液清洗芯片包装，然后在包含NaOH，Zno，酒石酸钾钠和硝酸钠的置换溶液中进行Zn置换（锌化）。锌置换后，在含有NaH2PO2的强还原溶液中进行无电解Ni-Cu-P沉积物的芯片封装。然后将沉积有Ni-Cu-P的芯片封装浸入作为硬脂酸和谷氨酸的混合物的助熔剂的有机溶液中。最后，将Ni-Cu-P沉积的芯片封装浸入熔融焊料浴中，比相应的Pb-Sn合金的熔点高40℃。

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